We found a charger detection error on RK3566 Tablet.
1. Plug in a Type-C to Type-A cable and connect to PC USB Host
or USB charger, then the charger detection is normal.
2. Plug out the cable, then the charger disconnection detection
is normal.
3. Plug in a Type-C to Type-A receptacle and plug out again. Then
the charger is detected unexpectedly.
To fix this issue, reinitialize the cable state of USB charger to
EXTCON_NONE when USB charger is disconnected.
Signed-off-by: William Wu <william.wu@rock-chips.com>
Change-Id: Ic56e4ee865af129c222f4c90c3d6e753f4e785bd
Because phy1 is sata mode by default, and phy2 is pcie mode by default, when using qsgmii on phy1, it needs to be configured as pcie mode, because pcie mode is compatible with K28.1 and K28.5, while sata only has K28.5. If phy1 is in sata mode, qsgmii will not work, and both K codes need to be used at the same time. Based on this, we unified configuration into pcie mode.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: I4a9e5a2cdcee448ec3457778bf4ee7135be70087
If the OTG work in Host mode, delay power off phy in OTG_STATE_B_IDLE
state when unplug OTG cable, this can fix the xHCI deregistered error
with the following log on RK356x platforms:
[ 16.856295] xhci-hcd xhci-hcd.5.auto: remove, state 4
[ 16.856340] usb usb8: USB disconnect, device number 1
[ 16.857778] xhci-hcd xhci-hcd.5.auto: USB bus 8 deregistered
[ 16.858108] xhci-hcd xhci-hcd.5.auto: remove, state 4
[ 16.858146] usb usb7: USB disconnect, device number 1
[ 16.878109] xhci-hcd xhci-hcd.5.auto: Host halt failed, -110
[ 16.878151] xhci-hcd xhci-hcd.5.auto: Host controller not halted, aborting reset.
[ 16.878853] xhci-hcd xhci-hcd.5.auto: USB bus 7 deregistered
Change-Id: I4467afdd3fe20839a9ec967624868ce3773e048c
Signed-off-by: William Wu <william.wu@rock-chips.com>
This patch sets the bvalid and id filter time to 10ms for rk356x
USB 2.0 PHY0 which is used for OTG. The filter count is base on
the USB 2.0 PHY GRF pclk 100MHz.
With this patch, it can avoid trigger the bvalid rising edge irq
when unplug the OTG cable.
Change-Id: I95794510921e6c065f4ec1102ab6c1f35994bf42
Signed-off-by: William Wu <william.wu@rock-chips.com>
We have move p30x1 and p30x2 reset signal to corresponding
controller drivers. So we need to remove them in PHY driver
in order not to add misleading debug message.
Change-Id: I5f180bf51a449ce2db6c49f937d3898a61d7c4d9
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
divide rk3568 mipi csi2 dphy dev into three logic dev:
dphy0 for full mode, dphy1 and dphy2 for split mode
Signed-off-by: Allon Huang <allon.huang@rock-chips.com>
Change-Id: Icd4b282b72aa90ca7acd2e02625ae56830c3b12a
Check the phy status after deassert phy reset for USB 3.0
mode, and wait at most 1ms for phy ready. If wait for phy
status ready timeout, just print warning log and continue
phy init for the time being.
Change-Id: I2677679a99153cf9ee0a043ab6cfb56d9e8dfdf2
Signed-off-by: William Wu <william.wu@rock-chips.com>
Set SSC downward spread spectrum for PCIe and set proper
RMJ for inner 100M and external 100M refclk.
Change-Id: Ic7d9d1651f7687858e6c5e399bc98ee03b5ee964
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
This patch adds a new function rockchip_combphy_parse_dt()
to parse devicetree for combphy, and get reset properties
for later reset control.
Change-Id: I41821ec9c99a866b04c4514f0fbca55d118b7175
Signed-off-by: William Wu <william.wu@rock-chips.com>
This patch creates an usb2 phy attribute group and
provides an attribute "otg_mode" for otg port to
force otg mode independently of the voltage of otg
id pin.
In order to implement the force mode function, we can
select otg plug indicator output (AKA iddig) from GRF,
and set GRF USB otg plug indicator to "0" or "1" to
control iddig status.
Attention, we set iddig to "0" by disable idpullup rather
than set GRF, the otg_suspendm will be set to 1 to enable
the disconnect detection module, and the LS_PAR_EN will be
set to 1 to enable low speed device enumerate.
Usage:
[1] Force host mode
echo host > /sys/devices/platform/<u2phy dev name>/otg_mode
[2] Force peripheral mode
echo peripheral > /sys/devices/platform/<u2phy dev name>/otg_mode
[3] Force otg mode
echo otg > /sys/devices/platform/<u2phy dev name>/otg_mode
For RV1109 and RV1126 EVB, the <u2phy dev name> is ff4c0000.usb2-phy.
Change-Id: Icba5e4a3d2aae6cd1df5435d64fd0caea4348ec2
Signed-off-by: Ren Jianing <jianing.ren@rock-chips.com>
Signed-off-by: William Wu <william.wu@rock-chips.com>
Since RK356x, the USB PHY GRF adds new registers to select
bvalid from USB PHY or GRF. And in RK356x Maskrom USB driver,
it selects the bvalid from GRF and sets the bvalid value to 1,
it aims to improve the compatibility of various USB circuits
for Maskrom USB. However, the charger detection and USB PHY
power consumption control depends on the bvalid of USB PHY.
So this patch selects bvalid from USB PHY for otg port.
Change-Id: I3fc9faf06f30e0a3390bc4fd40c732fb856131f8
Signed-off-by: William Wu <william.wu@rock-chips.com>
This patch adds a new vbus_detect helper function to control
the vbus voltage level detection for rk3568 otg port. And
fix the issue that the bvalid irq status and id irq status
are not handled in the rockchip_usb2phy_irq() for otg host
mode when force mode via the sys interface "otg_mode".
Change-Id: I75a102034e8dd3ad47de67da4e5120e28564368e
Signed-off-by: William Wu <william.wu@rock-chips.com>
pipe clock settings were done before PCIe's and SATA's catch-all
pipe settings. So it would be covered by con1_for_pcie and
con1_for_sata. Fix this by moving pipe clock settings to the end.
Change-Id: I19a8943b6a99d8e4ef198345ec3f62bdac491c58
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Change AUX amplitude level to 300mV.
Fixes: 6110f21e08 ("phy/rockchip: naneng-edp: Update for Compliance Test Pass")
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
Change-Id: I7a38407eb7d54389f3648f523616c7027c221545
The pipe clk of rk3568 is used for PIPE_GRF module, we
need to manage this clk so that the USB IP can access
the registers of PIPE_GRF.
Change-Id: I9ebfd5d25bdf1e95a9c5a3390b1030aed5f5c7ba
Signed-off-by: William Wu <william.wu@rock-chips.com>
This patch support to disable u3 root port for USB3.0 controller
if needed. Such as RK3568 EVB6 USB3.0 OTG1 xHCI controller, it
only used USB2.0 PHY, so we need to disable u3 port by set the
xHCI u3 port number to zero and select the clk_usb3otg0_utmi for
source clk at the same time.
Change-Id: I4aee7cc0d2947e478ff7437e47e329411e67297c
Signed-off-by: William Wu <william.wu@rock-chips.com>
RK3568 USB2.0 PHY0 Host port is used for USB3.0 Host interface.
When USB3.0 Host controller is working at super speed, it may
still need the USB2.0 PHY0 to work in normal mode and get clks
from the PHY0. So we select PHY suspend control from USB3.O
Host controller utmi interface.
Change-Id: I66df057e200d04f66082257d26120764c54af3cf
Signed-off-by: William Wu <william.wu@rock-chips.com>
This patch enable the adaptive Continuous Time Linear Equalizer (CTLE)
for RK3568 USB3.0 to improve compatibility.
Change-Id: I04d3077e37f15a8d41df875b8d84dc7e6c8aeda9
Signed-off-by: William Wu <william.wu@rock-chips.com>
We turn off the differential reciver in suspend mode, which can
save about 300uA at AVCC_1V8 in suspend mode.
Signed-off-by: Ren Jianing <jianing.ren@rock-chips.com>
Change-Id: Ic9f2b931d7ee3fc687d8bb3f3e9dfe2d966c6542
1. Add clks enable and disable control.
2. Do PCIe/USB3/SATA phy init in their own helper.
3. Select ref clk according to ref clk rate for RK3568
4. Set SSC clk rate and SSC derection for the USB3 of RK3568.
Signed-off-by: William Wu <william.wu@rock-chips.com>
Signed-off-by: Ren Jianing <jianing.ren@rock-chips.com>
Change-Id: If2959147cfe9f799c88c31ef7cefbccc872a3bf4
The *USB_DCP* should be updated when the cable plug out from dedicated
charging port. As a result, the charger could set the charging current
by *EXTCON_CHG_USB_DCP*.
Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Change-Id: I478e584552a627de928378c6da1e6392a8fb04c4
This patch fixes the following issues for rk3568 usb2 phy.
1. Set utmi opmode to normal mode for rk3568 usb phy when usb
phy enter suspend mode via usb phy grf. It can help to avoid
the DM/DP floating and the line state be detected as 2'b11.
2. Fix the offset of INT_STATUS_CLR. It can help to avoid
triggering the linestate irq constantly.
Signed-off-by: Ren Jianing <jianing.ren@rock-chips.com>
Change-Id: Iba53e416c44a45baa180ad3abcc91d1d71900158
This patch select pipe_txcompliance and pipe_l0_txelecidle
from usb3 controller for usb3 mode.
Change-Id: I6d354a974e431079e0f11fe84b75df583125818b
Signed-off-by: William Wu <william.wu@rock-chips.com>
This patch fixes the following issues for rk3568 usb2 phy.
1. Only enable the id irq and bvalid irq for the port of combphy
which used shared interrupt and work as otg/peripheral mode.
2. Enable the DP/DM pulldown resistors for the port of combphy
if the port is used for usb host controller.
3. Set utmi opmode to no-driving for rk3568 usb phy when usb
phy enter suspend mode via usb phy grf. It can help to
avoid triggering the linestate irq constantly.
Change-Id: I3efe964c79865bef8ba70047f2ee20c59901ca6c
Signed-off-by: William Wu <william.wu@rock-chips.com>
DPTPHYT22ULP is designed for chips that perform eDP/DP data
communication while operating at low power consumption.
The main link is a multi-gigabit transmitter macro which
enable speed up to 4.0Gbps data transmitter with optimized
power and die size, also it can be easily fabricated and
implemented in a video system. The AUX channel is a halfduplex,
bidirectional channel consisting of one differential pair,
supporting the bit rate of about 1Mbps.
Macro consists of multi-main link transmitter channels,
AUX channel, one PLL and bias-gen unit. The main link
transmitter performs dedicated P2S, clock generator,
driver with preemphasis and self-test. Each of the channels
can be turned off individually.
Change-Id: Idf58991ff1bdd4557c4cfadf2dc047e95eca7668
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
This patch refactor the combphy_reg so that we can init
PCIe/USB3.0/SATA/QSGMII separately.
Change-Id: I8febce777a5b29948acdb66a1640245983cfe6cd
Signed-off-by: William Wu <william.wu@rock-chips.com>
The function param_read() and param_exped() do the same thing,
so this patch uses the more general param_read() instead of
the param_exped(), and delete the param_exped() directly.
Change-Id: Ic097069c28a717ff5f70ceaa36a22ea1bd26b76f
Signed-off-by: William Wu <william.wu@rock-chips.com>
RK3568 has two USB 2.0 PHYs, and each PHY has two ports, the
OTG port of PHY0 support OTG mode with charging detection
function, they are similar to previous Rockchip SoCs.
However, there are three different designs for RK3568 USB 2.0 PHY.
1. RK3568 uses independent USB GRF module for each USB 2.0 PHY.
2. RK3568 accesses the registers of USB 2.0 PHY IP directly by APB.
3. The two ports of USB 2.0 PHY share one interrupt.
Signed-off-by: William Wu <william.wu@rock-chips.com>
Change-Id: Id05718e25a20abdf9a4cb353b0fb94f0cb8b2d75
Add common helper function rockchip_usb2phy_port_irq_init() for
both otg port and host port to init their own irqs. It can help
to reduce redundant code, and also fix a issue that the id irq
isn't enabled for otg port if the vbus_always_on flag is true.
This patch introduces a combined irq for some inno usb2 phys
which combined the irqs of otg port and host port. We will used
it for RK3568 later.
Signed-off-by: William Wu <william.wu@rock-chips.com>
Change-Id: Ifa74ec72e2b9d4ed62ee69e916b8ab2e8ae665b3
This patch implements a combo phy driver for Rockchip SoCs
with NaNeng IP block. This phy can be used as pcie-phy, usb3-phy,
sata-phy or sgmii-phy.
Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
Change-Id: I86726e7eee643ea4cb3fadc56b0ee729903afc4f
