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phy: rockchip: naneng-combphy: Add external refclk support

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Change-Id: Iac968aa7ffd862533c7ca76dea82e083e957345c
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
This commit is contained in:
Shawn Lin 2020-12-08 14:28:37 +08:00 committed by Tao Huang
parent 9b269cfbcf
commit c07bd0ba5e
1 changed files with 5 additions and 0 deletions
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5
drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
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@ -44,6 +44,7 @@ struct rockchip_combphy_grfcfg {
struct combphy_reg pipe_sel_qsgmii;
struct combphy_reg pipe_clk_25m;
struct combphy_reg pipe_clk_100m;
struct combphy_reg pipe_clk_ext;
struct combphy_reg con0_for_pcie;
struct combphy_reg con1_for_pcie;
struct combphy_reg con2_for_pcie;
@ -397,6 +398,9 @@ static int rk3568_combphy_cfg(struct rockchip_combphy_priv *priv)
return -EINVAL;
}
if (device_property_read_bool(priv->dev, "rockchip,ext-refclk"))
param_write(priv->phy_grf, &cfg->pipe_clk_ext, true);
return 0;
}
@ -414,6 +418,7 @@ static const struct rockchip_combphy_grfcfg rk3568_combphy_grfcfgs = {
.pipe_sel_qsgmii = { 0x000c, 14, 13, 0x00, 0x03 },
.pipe_clk_25m = { 0x0004, 14, 13, 0x00, 0x01 },
.pipe_clk_100m = { 0x0004, 14, 13, 0x00, 0x02 },
.pipe_clk_ext = { 0x000c, 9, 8, 0x02, 0x01 },
.con0_for_pcie = { 0x0000, 15, 0, 0x00, 0x1000 },
.con1_for_pcie = { 0x0004, 15, 0, 0x00, 0x0000 },
.con2_for_pcie = { 0x0008, 15, 0, 0x00, 0x0101 },