Commit Graph

1129919 Commits

Author SHA1 Message Date
qctecmdr
749d60cba7 Merge "sched/walt: append carriage return to not_preferred output" 2022-11-02 21:55:02 -07:00
qctecmdr
010a200ec4 Merge "sched/walt: expand cpu arrays" 2022-11-02 21:55:02 -07:00
qctecmdr
e618ed7298 Merge "clk: qcom: clk-debug: Fix accessing mux when it is NULL" 2022-11-02 21:55:01 -07:00
qctecmdr
c4eeb0bb7d Merge "build: Add support for custom userspace toolchain" 2022-11-02 21:55:01 -07:00
qctecmdr
0d93c59727 Merge "defconfig: Enable MHI bus driver for msm-pineapple" 2022-11-02 21:55:01 -07:00
qctecmdr
ebd3b76455 Merge "kernel/sched/walt: ensure em_pd creation before rebuild_sched_domains" 2022-11-02 21:55:01 -07:00
qctecmdr
0a87ecd6c9 Merge "clk: qcom: clk-rpmh: Fix overflow in BCM vote" 2022-11-02 21:55:00 -07:00
qctecmdr
60d2b5697e Merge "coresight: funnel: Fix the duplicate-funnel enable crash issue" 2022-11-02 21:54:59 -07:00
Lazarus Motha
bce8246de0 defconfig: Enable MHI bus driver for msm-pineapple
Enable MHI bus,MISC and DEBUG drivers for msm-pineapple.

Change-Id: If909879b41f7e150358dcf32076d177b7f7a736a
Signed-off-by: Lazarus Motha <quic_lmotha@quicinc.com>
2022-10-29 14:40:28 -07:00
Veera Vegivada
4856d5b443 clk: qcom: clk-debug: Fix accessing mux when it is NULL
When debugcc did not register, measure/mux will be NULL.
Avoid accessing it.

Change-Id: I037151e258ae85c89c9db87254e5b8ea850157a0
Signed-off-by: Veera Vegivada <quic_vvegivad@quicinc.com>
2022-10-28 15:54:28 -07:00
qctecmdr
67fde14ade Merge "dma-heap: qcom: Add the UBWC-P heap" 2022-10-28 12:25:10 -07:00
qctecmdr
3e91d7e606 Merge "defconfig: pineapple-gki: enable sdcard driver" 2022-10-28 12:25:09 -07:00
qctecmdr
723e6ee54d Merge "net: qrtr: Handle error from skb_put_padto" 2022-10-28 12:25:09 -07:00
qctecmdr
c3dde5a97d Merge "phy: qualcomm: Add UFS PHY support for pineapple" 2022-10-28 12:25:09 -07:00
qctecmdr
9b60653498 Merge "android: abi_gki_aarch64_qcom: Add thermal_cdev_update" 2022-10-28 10:17:39 -07:00
jianzhou
8262f51a91 Merge keystone/android-mainline-keystone-qcom-release.6.0 (11a22ea) into msm-pineapple
* refs/heads/tmp-11a22e:
  ANDROID: bazel: add GKI consolidate Bazel build
  ANDROID: arch_topology: Add android_rvh_update_thermal_stats
  ANDROID: kernel/sched: rebuild_sched_domains export
  ANDROID: sched: gki: add padding to some structs to support WALT

Change-Id: Ia38f0a4d97c585af50d246f9e1c20525448560d4
Upstream-Build:ks_qcom-android-mainline-keystone-qcom-release@9228327 SKQ4.221027.002
Signed-off-by: jianzhou <quic_jianzhou@quicinc.com>
2022-10-27 22:25:40 -07:00
Android Build Coastguard Worker
11a22ea195 Snap for 9228065 from e32903b9a6 to android-mainline-keystone-qcom-release
Change-Id: I6540c44f432fc77ffe1c366e1aa25f653ed5fbe7
2022-10-28 00:00:17 +00:00
Stephen Dickey
8327be044c kernel/sched/walt: ensure em_pd creation before rebuild_sched_domains
rebuild_sched_domains() is called during walt_init with the assumption
that cpufreq_online has actually completed before the execution of
walt_init. This is only partially true.

cpufreq_online() will notify update_topology_flags_workfn once the
policies have been created. However, the em creation is after this
point in time.

This creates a race condition between cpufreq_online's creation
of the energy model through it's call to register_em(policy), and
walt's execution of rebuild_sched_domains. If walt init completes
quickly, and rebuild_sched_domains() is executed quickly, it is
possible it will complete before the energy model is registered.
Thus, the perf domains will still be unpopulated, and the error
detection for perf domains will cause the system to crash.

Address this by ensuring that the energy model has run for each
cpu in the system by checking the same field that em_create_pd
must populate for build_perf_domains to work properly, the
em_pd field in the cpu device.

Additionally ensure that this is only attempted if the domains are
not yet setup properly and it is known that corrective action
must take place.

Change-Id: I8f5150fe4e2e37b3820e809232f26ff207723601
Signed-off-by: Stephen Dickey <quic_dickey@quicinc.com>
2022-10-27 15:28:47 -07:00
Shaleen Agrawal
c15a0101ac sched/walt: Update cpu capacity during thermal pressure
Ensure that all thermal pressure gets accounted in capacity_orig
as soon as it is set, rather than during the window rollover period.

Change-Id: Ia22cb87f0d1fcb23f1a932f9b70637861b56ae33
Signed-off-by: Shaleen Agrawal <quic_shalagra@quicinc.com>
2022-10-27 15:28:46 -07:00
Stephen Dickey
5ca19b7ae1 kernel/sched/walt: rd->pd not getting updated soon enough
If the energy model is not updated by the time rebalance_domains
is called for the first time, the root domain -> perf_domain
values will get erased completely, and will be invalid. The
responsibility for this race is outside of the walt module.

walt_find_energy_efficient_cpu() relies upon rd->pd being valid
and cannot function properly without it. This is critical to
proper walt functionality and it cannot move forward without it.

Decisvely catch the failure.

Change-Id: Iee8030afd487dcee1d9cc18c2d655ecc26938279
Signed-off-by: Stephen Dickey <quic_dickey@quicinc.com>
2022-10-27 15:28:46 -07:00
Stephen Dickey
427c7e27f6 kernel/sched/walt: start domain rebuilding and wait
There is a race condition in cpufreq.c in which the energy model
is not updated until after rebuild domains has completed. If
this is performed out of order, the rebuild domains will fail and
the perf domains will be freed, causing
walt_find_energy_efficient_cpu to fail to perform active migration.

After topology update is complete and walt initialization moves
forward, rebuild the domains waiting for the completion of the
rebuild before performing the walt update of the toplogy,
guranteeing that the perf domains are populated properly even if
cpufreq builds the domains the first time, out of order.

Change-Id: I28499c4318580da54735347be0ea00867e68d94b
Signed-off-by: Stephen Dickey <quic_dickey@quicinc.com>
2022-10-27 15:28:45 -07:00
Shaleen Agrawal
a09a292a85 sched/walt: expand cpu arrays
Build_cpu_array function is rewritten to setup the cpu arrays
manually rather than automatically based on cluster id and capacity.

This allows for more flexible setup of cpu arrays. While at it also
start supporting four cluster systems.

Change-Id: I3932d9bbd0de95d6356ee298e733e7c5e799974f
Signed-off-by: Shaleen Agrawal <quic_shalagra@quicinc.com>
Signed-off-by: Abhijeet Dharmapurikar <quic_adharmap@quicinc.com>
2022-10-27 15:12:47 -07:00
Abhijeet Dharmapurikar
eb867a1f36 sched/walt: update load balancer for multiple cluster
Currently the code it setup for specific number of clusters. Make it
generic for N clusters.

Change-Id: I6ad1c068e8e5645afd61e111783d981381a710b2
Signed-off-by: Abhijeet Dharmapurikar <quic_adharmap@quicinc.com>
2022-10-27 15:08:09 -07:00
Abhijeet Dharmapurikar
cd5ecacb5b sched/walt: use individual cpu early up/down threshold
Currently the code is using up/down thresholds based on clusters.
With number of clusters changing, it will be best if we populate
a per cpu value and use it.

Change-Id: Id16aef6f9cecb485fefe4d4e56f2b07852aa6e1c
Signed-off-by: Abhijeet Dharmapurikar <quic_adharmap@quicinc.com>
2022-10-27 15:08:09 -07:00
Abhijeet Dharmapurikar
87f1fd9d34 sched/walt: fix handling of up/down migrate
The code currently unnecessarily checks for cap_margin_levels > 1.
In SMP systems where num_sched_clusters = 1 we still use a single
sched_cluster with all the cpus. So we dont have to handle
num_sched_cluster =1 (or 2) separately.

Change-Id: Ie9a8dda70555f02d64df11b310fd56727f149633
Signed-off-by: Abhijeet Dharmapurikar <quic_adharmap@quicinc.com>
2022-10-27 15:08:09 -07:00
Abhijeet Dharmapurikar
0b76f7d59d sched/walt: don't pass capacity to task_fits_max
There is no need for the callsites to pass the capacity of the new cpu.
It is best if task_fits_max() gets it as it is the only one that uses
it.

Also take this opportunity to change the variable name "cpu" to "dst_cpu".

Change-Id: I836f779b31a4c8f7bc5f9c87c40f4fa5caf786f2
Signed-off-by: Abhijeet Dharmapurikar <quic_adharmap@quicinc.com>
2022-10-27 15:08:09 -07:00
Stephen Dickey
a569117648 sched/walt: update walt_get_indicies for 4 clusters
walt_get_indices() was written for a 3 cluster system. In
the future it is necessary to support 2, 3 and 4 cluster
systems.

Make the appropriate changes to walt_get_indices such that
cpus are visited in the correct order for each of these
topologies.

Change-Id: Iae60c152aaa561326adccc0e92056e598dde2679
Signed-off-by: Stephen Dickey <quic_dickey@quicinc.com>
2022-10-27 15:08:09 -07:00
Stephen Dickey
9003596e0b sched/walt: Update MAX_CLUSTERS to 4
In preparation of a 4 cluster system, indicate our
maximum number of clusters as 4.

Change-Id: I06e097581d737b56f2cbdc20460264801e29ffa2
Signed-off-by: Stephen Dickey <quic_dickey@quicinc.com>
Signed-off-by: Abhijeet Dharmapurikar <quic_adharmap@quicinc.com>
2022-10-27 15:08:09 -07:00
Stephen Dickey
10120e444a sched/walt/core_ctl: wait for masks initialization
The core control masks must be initialized before core control
can be used. Prepare core control to validate the masks before
allowing core control check to proceed.

Change-Id: I86e7a51a009ba03347ecb0814b0122247bd54d74
Signed-off-by: Stephen Dickey <quic_dickey@quicinc.com>
Signed-off-by: Abhijeet Dharmapurikar <quic_adharmap@quicinc.com>
2022-10-27 15:08:09 -07:00
Stephen Dickey
aff07c50a1 sched/walt/core_ctl: make the cpumasks writable
The user should be able to determine how this particular soc
has setup the cpumasks for controlling core control. Make
those visible and allow them to be written by postboot.

Change-Id: Icb74ab9573dbe392481032a8a460ba6938bf287a
Signed-off-by: Stephen Dickey <quic_dickey@quicinc.com>
Signed-off-by: Abhijeet Dharmapurikar <quic_adharmap@quicinc.com>
2022-10-27 15:08:09 -07:00
Stephen Dickey
f1d0a9ba42 sched/walt/core_ctl: create cpu masks for core control
Core Control programatically determins its behavior, in terms
of what other clusters this particular cluster would pay attention
to, to decide whether to unpause a cpu. This is inflexible, and
prevents an easy path to utilizing more clustersto allow unpausing
of cpus to assist clusters in unique ways to support power and
performance goals.

In preparation for using 4 clusters with core control, increase
the flexibility of core control in terms of how it chooses which
clusters to assist, for this cluster.

With this change there are 4 classes of cpus each cluster pays
attention to. Cpus being monitored for nrrun, nrrun misfits,
assist, and assist missfits. This allows the code to replicate
previous core control behavior, while introducing the ability
to specify any cpu to monitor for each of these behaviors.

For example, a typical configuration for a typical 3 cluster
system would be as below, replicating previous core control
behavior but using these masks.

                   nrrun             assist
 cluster | nrrun | misfit | assist | misfit |
 --------------------------------------------
 silver  | 0xFF  | 0x00   | 0x00   | 0x00   |
 --------------------------------------------
 gold    | 0xF8  | 0x07   | 0x00   | 0x00   |
 --------------------------------------------
 prime   | 0x80  | 0x78   | 0x78   | 0x07   |
 --------------------------------------------

This means, for example, when prime computes nrrun it will only
consider itself, for nrrun misfits, golds, and assisting, golds,
and for assisting with misfits, silvers.

This gets expanded to a 4 entry table for a 4 cluster system as
the clusters are fed into core control initialization, allowing
for an extremely flexible definition of how core control operates.

Change-Id: Ic372da9a453ef593144172524ae1d99e056dd45f
Signed-off-by: Stephen Dickey <quic_dickey@quicinc.com>
Signed-off-by: Abhijeet Dharmapurikar <quic_adharmap@quicinc.com>
2022-10-27 15:08:09 -07:00
John Moon
8e5c9866a0 build: Add support for custom userspace toolchain
When using build_with_bazel.py, users may want to build extra
userspace cc_binary targets with a different toolchain.

Enable this capability by adding the --userspace_cross_toolchain
option.

Change-Id: I9eaaaa71ba483132fb68124e713a05d2918f9aa1
Signed-off-by: John Moon <quic_johmoo@quicinc.com>
2022-10-27 14:54:31 -07:00
Chris Lew
4ed377ec29 net: qrtr: Handle error from skb_put_padto
skb_put_padto() will free the skb if it fails to add the requested
padding to the skb. Drop the packet if we are unable to allocate a new
skb with the requested padding.

Change-Id: I5503c99679c7e6ecf767d3f632d72da5315988f1
Signed-off-by: Jay Jayanna <jayanna@codeaurora.org>
Signed-off-by: Chris Lew <quic_clew@quicinc.com>
2022-10-27 11:09:03 -07:00
Chris Lew
c4a21244f3 net: qrtr: Change error logging in callback
Print error logs in the callback by using pr_err_ratelimited
so that watchdog bark will not occur due to excessive logging
when the callback is triggered before probe is completed.

Change-Id: I82bb84b7812cef5cb8a37e99c5cf1a54411cbdb8
Signed-off-by: Sarannya S <sarannya@codeaurora.org>
Signed-off-by: Chris Lew <quic_clew@quicinc.com>
2022-10-27 11:08:55 -07:00
Chris Lew
0079417ad7 net: qrtr: Allow isr context to get service details
Allow isr context to get service details.

Change-Id: I782a2c80883252ce614a0a05df6d4fc1a1304b32
Signed-off-by: Arun Prakash <app@codeaurora.org>
Signed-off-by: Chris Lew <quic_clew@quicinc.com>
2022-10-27 11:08:48 -07:00
Chris Lew
e2b39c0d6e net: qrtr: Make wakeup timeout configurable
The qrtr driver can guarantee that the packet gets queued to the socket
but cannot guarantee the client process will get time to run if auto
sleep is enabled. This config will help mitigate missed packets on
systems where auto sleep is too aggressive.

Use the pm_wakeup_ws_event() api so a hard wakeup can be specified.
This will ensure a resume occurs if the data coming in happens while
the device is going into suspend.

Change-Id: Ic596e06e585b3479a6faa1d0210c016fc9138c6e
Signed-off-by: Chris Lew <quic_clew@quicinc.com>
2022-10-27 11:07:54 -07:00
Chris Lew
533788bfca net: qrtr: Add pm_wakeup_event() support
In some cases system enters into suspend state before handling
incoming packets and cause delay in communication.

Add pm_wakup_event() to abort the suspend when a packet is received.

Force a wakeup when queueing packets to a socket. This is needed to
give userspace clients a chance to run if the device is going into
system suspend. The wakeup event should force the device to abort
suspend.

The only node that should not behave this way is the SLPI node because
sensor stream race conditions cause suspend issues and power drain
issues.

There was an update to add a device parameter into
wakeup_source_register().

Change-Id: Ie69be3a46309f6a05cfbff0642b95194c2d6e955
Signed-off-by: Chris Lew <quic_clew@quicinc.com>
2022-10-27 11:07:47 -07:00
Chris Lew
a34e1c5cea net: qrtr: Add backup skb pool
Add a pool of SKBs that can be used when the system is in low memory
conditions. This pool will be shared between all nodes and replenished
by a worker function.

Change-Id: I639a9ac76db726dc8ad46b12d3b3d560c674939c
Signed-off-by: Jay Jayanna <jayanna@codeaurora.org>
Signed-off-by: Chris Lew <quic_clew@quicinc.com>
2022-10-27 11:07:38 -07:00
Chris Lew
08de359d99 net: qrtr: Add dynamic node id configuration
Add support to configure the node id through defconfig. This is useful
for targets that are unable to configure the node id through qrtr-ns
because of security reasons. The local node id can still be overridden
by the ns if it is capable.

Change-Id: Ie9fec2ae276948340f4f5a7e0374d554502a0ee1
Signed-off-by: Chris Lew <quic_clew@quicinc.com>
2022-10-27 11:07:29 -07:00
Chris Lew
67789fda41 net: qrtr: hold ept sem lock before node lookup
Node ref count decrement and test is performed inside ept
sem lock while node lookup is done inside node spin lock.
This can sometime cause node lookup to succeed while parallely
node can be freed in node release function. This will further
use of node and will result in use after free.

Additionally hold ept smem lock before performing node lookup.

Change-Id: Iaa5781c56ebee51611dfea9fddcde50f1367dfea
Signed-off-by: Deepak Kumar Singh <deesin@codeaurora.org>
Signed-off-by: Jay Jayanna <jayanna@codeaurora.org>
Signed-off-by: Chris Lew <quic_clew@quicinc.com>
2022-10-27 11:07:12 -07:00
Hao Zhang
cf18d0685f coresight: funnel: Fix the duplicate-funnel enable crash issue
When enable the duplicate-funnel, it would crash due to missing the
initialization of the struct csdev_access in the funnel probe.

Change-Id: Iaedfdf300f35e0c7f1b2da7f7ede26aa84bae395
Signed-off-by: Hao Zhang <quic_hazha@quicinc.com>
2022-10-27 03:10:52 -07:00
John Moon
e32903b9a6 ANDROID: bazel: add GKI consolidate Bazel build
Adds //common:kernel_aarch64_consolidate Bazel build target.

Bug: 255878221
Change-Id: I76b44a2764d461d6267ff217e8914298fe560544
Signed-off-by: John Moon <quic_johmoo@quicinc.com>
2022-10-26 23:26:28 -07:00
Bao D. Nguyen
f16d49239e phy: qualcomm: Add UFS PHY support for pineapple
Add UFS PHY support for Pineapple.

Change-Id: I8b2829a6c5ea571b6aa2dbd1fc09ea21869bf1c3
Signed-off-by: Bao D. Nguyen <quic_nguyenb@quicinc.com>
2022-10-26 21:43:59 -07:00
qctecmdr
2b0465b6c3 Merge "coresight-stm: fix list_add double add issue" 2022-10-26 09:48:14 -07:00
qctecmdr
6ab101b62e Merge "coresight: etr: Don't allocate the new buffer when etr is enabled" 2022-10-26 09:48:13 -07:00
qctecmdr
3c7f6a083d Merge "coresight: byte-cntr: Add the length check in reading data" 2022-10-26 09:48:12 -07:00
qctecmdr
504a2af1e9 Merge "clk: qcom: pineapple: Update clock drivers with latest frequency plans" 2022-10-26 09:48:12 -07:00
qctecmdr
eb636f450b Merge "defconfig: pineapple-gki: Enable our IOMMU debug module" 2022-10-26 09:48:11 -07:00
qctecmdr
c58ed8a737 Merge "build.config.msm.common: Fix corner case in copy_dist_bins()" 2022-10-26 09:48:10 -07:00
qctecmdr
a23281d498 Merge "soc: qcom: Add v18 support for socinfo" 2022-10-26 09:48:09 -07:00