Configure and enable the WCNSS which provides WiFi and Bluetooth on this
device using the WCN3660B chip.
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Cristian Cozzolino <cristian_ci@protonmail.com>
Link: https://lore.kernel.org/r/20260331-rimob-new-features-v5-4-5fcf42a29c12@protonmail.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Add the description for the display panel found on this phone.
And with this done we can also enable the GPU and set the zap shader
firmware path.
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Cristian Cozzolino <cristian_ci@protonmail.com>
Link: https://lore.kernel.org/r/20260331-rimob-new-features-v5-3-5fcf42a29c12@protonmail.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
On many Qualcomm platforms the PMIC RTC control and time registers are
read-only so that the RTC time can not be updated. Instead an offset
needs be stored in some machine-specific non-volatile memory, which a
driver can take into account.
On platforms where the offset is stored in a Qualcomm specific UEFI
variable the variables are also accessed in a non-standard way, which
means that the OS cannot assume that the variable service is available
by the time the RTC driver probes.
Use the new 'qcom,uefi-rtc-info' property to indicate that the offset is
stored in a UEFI variable so that the OS can determine whether to wait
for it to become available.
[1]: https://lore.kernel.org/r/20250423075143.11157-4-johan+linaro@kernel.org
Fixes: 16a7fed117 ("arm64: dts: qcom: sc8280xp-blackrock: dt definition for WDK2023")
Signed-off-by: Jens Glathe <jens.glathe@oldschoolsolutions.biz>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260501-blackrock-rtc-v1-1-bddf3e37fa94@oldschoolsolutions.biz
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Add support for building an EL2 combined DTB for the talos-evk
in the Qualcomm DTS Makefile.
The new talos-evk-el2.dtb is generated by combining the base
talos-evk.dtb with the talos-el2.dtbo overlay, enabling EL2-specific
configurations required by the platform.
Signed-off-by: Xin Liu <xin.liu@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260427082325.1895450-1-xin.liu@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Configure and enable the node for IPA which enables mobile data on this
device.
Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260410-milos-ipa-v2-2-c699b6b8cf27@fairphone.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Add the description of the IPA block in the Milos SoC.
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
Link: https://lore.kernel.org/r/20260410-milos-ipa-v2-1-c699b6b8cf27@fairphone.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
USB controller on Kaanapali SoC is capable of switching role betwen device
and host and also is a wakeup capable device. Add usb-role-switch and
wakeup-source properties to the controller node accordingly.
Signed-off-by: Krishna Kurapati <krishna.kurapati@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260702184440.442037-1-krishna.kurapati@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
USB controller on SM8750 can be configured as a wakeup capable device.
Add wakeup-source property indicating the same.
Signed-off-by: Krishna Kurapati <krishna.kurapati@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260702184511.442129-1-krishna.kurapati@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
We know the driver is reporting s3706b, introduce the compatible so we
can more easily introduce quirks for weird touchscreen replacements in
followup series.
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: David Heidelberg <david@ixit.cz>
Link: https://lore.kernel.org/r/20260523-synaptics-rmi4-dt-v2-2-0645122babdc@ixit.cz
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Add a default pin configuration for CAM_MCLK3 (GPIO97), which is used
as a master clock for camera sensors on SM8250 boards.
Signed-off-by: Xin Xu <xxsemail@qq.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/tencent_47473BB31C9142449F8C7C1BE69D9071510A@qq.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Add the pm8008 PMIC node on i2c15 with seven LDOs,
using GPIO84 as interrupt and GPIO76 as reset.
Signed-off-by: Xin Xu <xxsemail@qq.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/tencent_D4AB219A942591742C3A6DA4DFB0EBA49505@qq.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Add SoC ID for Qualcomm Snapdragon SDM850.
Signed-off-by: David Heidelberg <david@ixit.cz>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260627-sda850-v2-1-44bf46ade42e@ixit.cz
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Add label properties to TPDM and CTI nodes in the hamoa device tree to
provide human-readable identifiers for each CoreSight device. These
labels allow userspace tools and the CoreSight framework to identify
devices by name rather than by base address.
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260414-add-label-to-coresight-device-v2-7-5017d07358f2@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Add label properties to TPDM and CTI nodes in the sm8750 device tree to
provide human-readable identifiers for each CoreSight device. These
labels allow userspace tools and the CoreSight framework to identify
devices by name rather than by base address.
Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260414-add-label-to-coresight-device-v2-6-5017d07358f2@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Add label properties to TPDM nodes in the kaanapali device tree to
provide human-readable identifiers for each CoreSight device. These
labels allow userspace tools and the CoreSight framework to identify
devices by name rather than by base address.
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260414-add-label-to-coresight-device-v2-5-5017d07358f2@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Add label properties to TPDM and CTI nodes in the kodiak device tree to
provide human-readable identifiers for each CoreSight device. These
labels allow userspace tools and the CoreSight framework to identify
devices by name rather than by base address.
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260414-add-label-to-coresight-device-v2-4-5017d07358f2@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Add label properties to TPDM and CTI nodes in the monaco device tree to
provide human-readable identifiers for each CoreSight device. These
labels allow userspace tools and the CoreSight framework to identify
devices by name rather than by base address.
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260414-add-label-to-coresight-device-v2-3-5017d07358f2@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Add label properties to CTI and TPDM nodes in the talos device tree to
provide human-readable identifiers for each CoreSight device. These
labels allow userspace tools and the CoreSight framework to identify
devices by name rather than by base address.
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260414-add-label-to-coresight-device-v2-2-5017d07358f2@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Add label properties to TPDM and CTI nodes in the lemans device tree to
provide human-readable identifiers for each CoreSight device. These
labels allow userspace tools and the CoreSight framework to identify
devices by name rather than by base address.
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260414-add-label-to-coresight-device-v2-1-5017d07358f2@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Add cooling-cells property to the CPU nodes to support cpufreq
cooling devices.
Signed-off-by: Dipa Mantre <dipa.mantre@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Gaurav Kohli <gaurav.kohli@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260415-cpufreq_kaanapali-v1-1-1fa94105d5c2@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Add gpio device nodes in pm8010*.dtsi files for any consumers to be
able to use the GPIOs.
Signed-off-by: Fenglin Wu <fenglin.wu@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260507-pm8010_gpio-v1-3-3bce9da8d2ba@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Move generic IPA-related properties to the base DTSI file. The herobrine
has special software configuration, so delete the memory-region property
which wasn't set for it beforehand. Also delete the property for several
IoT devices, which don't enable IPA memory at this point (and don't
seem to have IPA supported by the modem firmware).
Co-developed-by: Stanislav Zaikin <zstaseg@gmail.com>
Signed-off-by: Stanislav Zaikin <zstaseg@gmail.com>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Reviewed-by: Alex Elder <elder@riscstar.com>
Link: https://lore.kernel.org/r/20260517-ipa-loader-v1-6-3c3764c1b4a3@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
The sa8775p-ride board development mostly happened back to year 2023,
and it hadn't got any major update since then, except Wasim's refactor[1]
last year which had no functional change for the board.
Propose to stop maintaining the board for reasons below.
- The Lemans development had moved to QCS9100/9075 EVK and Ride board
for a long time.
- Qualcomm stopped maintaining Meta Build (NHLOS firmware) for this target
years ago. There is not too much point to continuing maintaining the DT,
as DT usually depends on NHLOS firmware.
Link: https://lore.kernel.org/all/20250803110113.401927-1-wasim.nazir@oss.qualcomm.com/ [1]
Cc: Wasim Nazir <wasim.nazir@oss.qualcomm.com>
Cc: Shazad Hussain <shazad.hussain@oss.qualcomm.com>
Cc: Andrew Halaney <ahalaney@redhat.com>
Cc: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260520141457.988130-1-shengchao.guo@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Add the kaanpali nodes for the True Random Number Generator (TRNG).
Signed-off-by: Kuldeep Singh <kuldeep.singh@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260423-knp_rng-v1-1-9df6c0391a8f@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
The Inline Crypto Engine (ICE) exists as a standalone DT node, but the
UFS node lacks the required qcom,ice phandle reference.
Add the qcom,ice property to explicitly associate the UFS controller
with its ICE instance.
Fixes: d288abc3a7 ("arm64: dts: qcom: sm8750: Add UFS nodes for SM8750 SoC")
Signed-off-by: Kuldeep Singh <kuldeep.singh@oss.qualcomm.com>
Tested-by: Wenjia Zhang <wenjia.zhang@oss.qualcomm.com> # on sm8750-mtp
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260429-sm8750_ice_dt_fix-v1-1-2540dc337082@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Remove reservations from reserved-memory which are already covered by
the EFI memmap. AFAICT there is no need to have these in the DT and chances
are that they might change with a BIOS update, so lets drop them.
hyp_elf_package_mem + ncc_mem are together covered by
efi: 0x000080800000-0x000080dfffff [Reserved |
xbl_dtlog_mem is covered by:
efi: 0x000081a00000-0x000081a3ffff [Reserved |
pdp_ns_shared_mem is covered by:
efi: 0x000081e00000-0x000081efffff [Reserved |
gpu_prr_mem + tpm_control_mem are together covered by:
efi: 0x000081f00000-0x000081f1ffff [Reserved |
usb_ucsi_shared_mem is covered by:
efi: 0x000081f20000-0x000081f2ffff [Reserved |
pld_pep_mem + pld_gmu_mem + pld_pdp_mem are together covered by:
efi: 0x000081f30000-0x000081f37fff [Reserved |
tz_stat_mem is covered by:
efi: 0x000082700000-0x0000827fffff [Reserved |
xbl_tmp_buffer_mem is covered by:
efi: 0x000082800000-0x0000829bffff [Reserved |
Signed-off-by: Hans de Goede <johannes.goede@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260525114749.5939-3-johannes.goede@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
The EFI memtable (shown when booting with efi=debug) shows that the
xbl_tmp_buffer_mem region size is 0x1c0000 bytes large not 0xc00000 bytes:
efi: 0x000082800000-0x0000829bffff [Reserved |
efi: 0x0000829c0000-0x000083efffff [Conventional|
This fix aligns the size with the EFI reported size and makes /proc/iomem
correctly show mem blocks matching the EFI memmap:
82800000-829bffff : reserved
829c0000-83efffff : System RAM
Instead of:
82800000-833fffff : reserved
83400000-83efffff : System RAM
before this change
Signed-off-by: Hans de Goede <johannes.goede@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260525114749.5939-2-johannes.goede@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Add embedded controller node for Hamoa IOT EVK boards which adds fan
control, temperature sensors, access to EC internal state changes and
suspend entry/exit notifications to the EC.
Signed-off-by: Sibi Sankar <sibi.sankar@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Gaurav Kohli <gaurav.kohli@oss.qualcomm.com>
Tested-by: Gaurav Kohli <gaurav.kohli@oss.qualcomm.com>
Co-developed-by: Anvesh Jain P <anvesh.p@oss.qualcomm.com>
Signed-off-by: Anvesh Jain P <anvesh.p@oss.qualcomm.com>
Tested-by: Anthony Ruhier <aruhier@mailbox.org>
Link: https://lore.kernel.org/r/20260511-add-driver-for-ec-v9-5-e5437c39b7f8@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Add embedded controller node for Hamoa/Purwa CRDs which adds fan control,
temperature sensors, access to EC internal state changes and suspend
entry/exit notifications to the EC.
Signed-off-by: Sibi Sankar <sibi.sankar@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
Co-developed-by: Anvesh Jain P <anvesh.p@oss.qualcomm.com>
Signed-off-by: Anvesh Jain P <anvesh.p@oss.qualcomm.com>
Tested-by: Anthony Ruhier <aruhier@mailbox.org>
Link: https://lore.kernel.org/r/20260511-add-driver-for-ec-v9-4-e5437c39b7f8@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Add embedded controller node for Glymur CRDs which adds fan control,
temperature sensors, access to EC state changes through SCI events
and suspend entry/exit notifications to the EC.
Signed-off-by: Sibi Sankar <sibi.sankar@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
Co-developed-by: Anvesh Jain P <anvesh.p@oss.qualcomm.com>
Signed-off-by: Anvesh Jain P <anvesh.p@oss.qualcomm.com>
Tested-by: Anthony Ruhier <aruhier@mailbox.org>
Link: https://lore.kernel.org/r/20260511-add-driver-for-ec-v9-3-e5437c39b7f8@oss.qualcomm.com
[bjorn: Added i2c alias for &i2c9]
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Add the interconnect paths to enable drivers to vote on them, ensuring
the necessary NoC bandwidth is available.
This hasn't been done before, as prior to commit 05566ebcc0
("clk: qcom: gcc-x1e80100: Keep GCC USB QTB clock always ON"), this
would cause an inexplicable crash upon resume from system suspend.
Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260410-topic-hamoa_usb_icc-v1-1-461e64304067@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
The RB5gen2 is an embedded development platform for the
QCS8550, based on the Snapdragon 8 Gen 2 SoC (SM8550).
This change implements the main board, the vision mezzanine
will be supported in a follow up patch.
The main board has the following features:
- Qualcomm Dragonwing QCS8550 SoC
- Adreno GPU 740
- Spectra ISP
- Adreno VPU 8550
- Adreno DPU 1295
- 1 x 1GbE Ethernet (USB Ethernet)
- WIFI 7 + Bluetooth 5.4
- 1 x USB 2.0 Micro B (Debug)
- 1 x USB 3.0 Type C (ADB, DP out)
- 2 x USB 3.0 Type A
- 1 x HDMI 1.4 Type A
- 1 x DP 1.4 Type C
- 2 x WSA8845 Speaker amplifiers
- 2 x Speaker connectors
- 1 x On Board PDM MIC
- Accelerometer + Gyro Sensor
- 96Boards compatible low-speed and high-speed connectors [1]
- 7 x LED indicators (4 user, 2 radio, 1 power)
- Buttons for power, volume up/down, force USB boot
- 3 x Dip switches
On-Board PMICs:
- PMK8550 2.1
- PM8550 2.0
- PM8550VS 2.0 x4
- PM8550VE 2.0
- PM8550B 2.0
- PMR735D 2.0
- PM8010 1.1 x2
Product Page: [2]
[1] https://www.96boards.org/specifications/
[2] https://www.thundercomm.com/product/qualcomm-rb5-gen-2-development-kit
The default msi-map from sm8550.dtsi is deleted for both pcie0 and
pcie1. The QPS615 PCIe switch on each port exposes more than two
devices (1 USP + 3 DSPs), but Gunyah currently limits ITS device
mappings to two per root complex to save memory. With msi-map
present, the ITS MAPD command times out.
Deleting msi-map causes the DWC controller to fall back to its
internal iMSI-RX module, which handles MSIs without this limitation.
Signed-off-by: Joe Sandom <jsandom@axon.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260420-rb5gen2-dts-v4-5-b461909c2de8@axon.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Move qcom,gsi-loader and memory-region properties from individual board
DTS files into the SoC DTSI, since these are common to all SM8550-based
boards.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Joe Sandom <jsandom@axon.com>
Link: https://lore.kernel.org/r/20260420-rb5gen2-dts-v4-3-b461909c2de8@axon.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Add labels to the root port nodes (pcie0_port0, pcie1_port0) to
allow board DTS files to reference them for adding endpoint devices
to each pcie root port.
Update the pcieport0 reference to pcie0_port0 in sm8550-hdk.dts and
sm8550-qrd.dts to match the label rename in sm8550.dtsi.
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Joe Sandom <jsandom@axon.com>
Link: https://lore.kernel.org/r/20260420-rb5gen2-dts-v4-2-b461909c2de8@axon.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Add the MHI register regions to the pcie0 and pcie1 controller nodes
to expose link power state transition counters (L0s/L1/L1.1/L1.2/L2)
via debugfs. The PCIe host driver uses this region to read the
link_transition_count from the MHI registers.
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Joe Sandom <jsandom@axon.com>
Link: https://lore.kernel.org/r/20260420-rb5gen2-dts-v4-1-b461909c2de8@axon.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Add an IMEM on glymur which falls back to mmio-sram and define the
PIL relocation info region as its child, for post mortem tools to
locate the loaded remoteprocs.
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Ananthu C V <ananthu.cv@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260424-glymur-imem-v5-2-18ede63cf063@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Add compatible for Qualcomm's glymur IMEM, a block of sram which
can fall back to mmio-sram.
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Ananthu C V <ananthu.cv@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260424-glymur-imem-v5-1-18ede63cf063@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Add the mode-switch property to the QMP combo PHY so that mode-switch
events are routed to it, allowing the PHY to enter DisplayPort Alternate
Mode. Expand the DP data-lanes assignment from two to four lanes to make
use of the full link bandwidth available in this configuration.
Signed-off-by: Mahadevan P <mahadevan.p@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260420-kodiak_4k-v1-1-83dfc66b8f06@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Enable secondary USB controller in host mode on lemans EVK Platform.
Secondary USB controller is connected to a Genesys Logic USB HUB GL3590
having 4 ports. The ports of hub that are present on lemans EVK standalone
board are used as follows:-
1) port-1 is connected to HD3SS3220 Type-C port controller.
2) port-4 is used for the M.2 E key on corekit. Standard core kit uses UART
for Bluetooth. This port is to be used only if user optionally replaces the
WiFi card with the NFA765 chip which uses USB for Bluetooth.
Remaining 2 ports will become functional when the interface plus mezzanine
board is stacked on top of corekit:
3) port-2 is connected to another hub which is present on the mezz through
which 4 type-A ports are connected.
4) port-3 is used for the M.2 B key for a 5G card when the mezz is
connected.
Secondary USB Controller
↓
GL3590 USB Hub (4 ports)
|
|-- Port 1 → HD3SS3220 Type‑C Port Controller → USB‑C Connector
|
|-- Port 2 → Mezzanine USB Hub (when mezz attached)
|
|-- Port 3 → M.2 B‑Key Slot (when mezz attached)
|
|-- Port 4 → M.2 E‑Key Slot
(Default: BT via UART;
USB only if NFA765 module is installed)
Mark the second USB controller as host only capable and add the HD3SS3220
Type-C port controller along with Type-C connector for controlling vbus
supply.
Signed-off-by: Swati Agarwal <swati.agarwal@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260406110113.1709886-3-swati.agarwal@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Rename the hd3ss3220_ instance to improve clarity and simplify usage when
adding a secondary port controller.
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Swati Agarwal <swati.agarwal@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260406110113.1709886-2-swati.agarwal@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
