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arm64: dts: qcom: glymur-crd: Add Embedded controller node
Add embedded controller node for Glymur CRDs which adds fan control, temperature sensors, access to EC state changes through SCI events and suspend entry/exit notifications to the EC. Signed-off-by: Sibi Sankar <sibi.sankar@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Co-developed-by: Anvesh Jain P <anvesh.p@oss.qualcomm.com> Signed-off-by: Anvesh Jain P <anvesh.p@oss.qualcomm.com> Tested-by: Anthony Ruhier <aruhier@mailbox.org> Link: https://lore.kernel.org/r/20260511-add-driver-for-ec-v9-3-e5437c39b7f8@oss.qualcomm.com [bjorn: Added i2c alias for &i2c9] Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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@ -22,6 +22,7 @@ aliases {
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i2c0 = &i2c0;
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i2c1 = &i2c4;
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i2c2 = &i2c5;
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i2c3 = &i2c9;
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spi0 = &spi18;
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};
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@ -444,6 +445,22 @@ vreg_l4h_e0_1p2: ldo4 {
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};
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};
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&i2c9 {
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clock-frequency = <400000>;
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status = "okay";
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embedded-controller@76 {
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compatible = "qcom,glymur-crd-ec", "qcom,hamoa-crd-ec";
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reg = <0x76>;
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interrupts-extended = <&tlmm 66 IRQ_TYPE_EDGE_FALLING>;
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pinctrl-0 = <&ec_int_n_default>;
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pinctrl-names = "default";
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};
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};
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&pcie3b {
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vddpe-3v3-supply = <&vreg_nvmesec>;
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@ -596,6 +613,12 @@ hall_int_n_default: hall-int-n-state {
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bias-disable;
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};
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ec_int_n_default: ec-int-n-state {
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pins = "gpio66";
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function = "gpio";
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bias-disable;
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};
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pcie4_default: pcie4-default-state {
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clkreq-n-pins {
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pins = "gpio147";
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