Enable CPU pause cooling device driver which is able to pause a CPU
from being scheduled and hence allow the CPU to power collapse.
Change-Id: If4f194d3ae2d47d0ec48bcb8e39ed88b9667e39d
Signed-off-by: Rashid Zafar <quic_rzafar@quicinc.com>
Enable userspace cooling device driver to be used by userspace
clients for pineapple.
Change-Id: Ib2b58a4cc6b7e8fe0f003c025cfa032c252d94c9
Signed-off-by: Rashid Zafar <quic_rzafar@quicinc.com>
Enable CPU hotplug and CPU voltage cooling device drivers for
pineapple-gki. This cooling device will perform CPU cooling under
thermal conditions.
Change-Id: I850ac710e0acd4b32dd228276df92b24792562d1
Signed-off-by: Rashid Zafar <quic_rzafar@quicinc.com>
The canonical location of msm_kernel_extensions.bzl is changing.
Update the load() calls to the new location.
Change-Id: I27df6131de155cd0592cad5d57202ca01c4affb5
Signed-off-by: John Moon <quic_johmoo@quicinc.com>
Add Config and make rules for panel_event_notifier
driver.
Change-Id: Id8975ac19e3201a1ac7396821c1be0288bfa8617
Signed-off-by: Bruce Levy <quic_blevy@quicinc.com>
When __full_va_sweep(), __rand_va_sweep() and __tlb_stress_sweep(), do
their cleanup, they assume that the entire iova range 0..4G was mapped
correctly (i.e assigned iova starts at 0 and goes to 4G).
But if for some reason the iova starts at a different address (eg: with
fastmap, it could start at 0xFFFFF000), we end up with the following
warning from iommu_dma_unmap_page() because the iova 0 was never mapped.
898 phys = iommu_iova_to_phys(domain, dma_handle);
899 if (WARN_ON(!phys))
900 return;
Worse, since the cleanup tries to unmap the entire 0..4G range, this
warning is repeated a large number of times, making the device unusable.
Instead, report an error on the unexpected and unmap the incorrect dma
address immediately. And when unmapping the iova range, make sure to only
unmap regions that were correctly (when iova == dma_addr) mapped.
Change-Id: Ia0ab4fd49ba5021d4866daf69fb9a3fa7e61928d
Signed-off-by: Sukadev Bhattiprolu <quic_sukadev@quicinc.com>
Current codes may don't consider the 32-bit possibility, some
compilation errors happen when try to enable smmu on sdxbaagha:
1. arm-smmu-qcom.c:
"error: shift count is negative" reports at
"FIELD_GET(QTB_OVR_ECATS_OUTFLD0_PA, val)".
2. qcom-iommu-debug-user.c:
"error: incompatible pointer types passing" reports at
"if (kstrtox_from_user(ubuf, count, 0, &iova))".
3. qcom-io-pgtable-arm.c:
"error: implicit declaration of function 'FIELD_GET'"
reports at "FIELD_GET(TOP_IGNORED_MASK, table_pte)".
4. qcom-iommu-debug-user.c:
"error: implicit declaration of function 'FIELD_GET'"
reports at "FIELD_GET(ARM_SMMU_SMR_ID, fwspec->ids[0])".
5. qcom-iommu-debug.c:
"error: implicit declaration of function 'FIELD_GET'"
reports at "FIELD_GET(ARM_SMMU_SMR_ID, (fwspec->ids[0]))".
Change-Id: I38b96e411eaf37d87e48b4c9fe860a94643bc5b7
Signed-off-by: Qingqing Zhou <quic_qqzhou@quicinc.com>
Add support for charge control via the following power supply
properties.
charge_control_end_threshold: SOC threshold at which the charging
should be terminated.
charge_control_start_threshold: SOC threshold at which the charging
should be resumed.
"/sys/class/qcom-battery/charge_control_en" controls the feature.
E.g. To enable this feature to stop charging @ 80% and resume
charging @ 77%.
echo 1 > /sys/class/qcom-battery/charge_control_en
echo 80 > /sys/class/power_supply/battery/charge_control_end_threshold
echo 77 > /sys/class/power_supply/battery/charge_control_start_threshold
If charge_control_start_threshold is not set, then a delta_soc of
5 (i.e. charge_control_end_threshold - 5) would be configured.
Write "echo 0 > /sys/class/qcom-battery/charge_control_en" to
disable the charge control feature.
Change-Id: I02eef6bf9a23f313c661cbddb4feefa37639d520
Signed-off-by: Subbaraman Narayanamurthy <quic_subbaram@quicinc.com>
Replace the hyp_assign_phys with upstream friendly qcom_scm_assign_mem.
dsm memory region is needed by MPSS PDs, this call reassigns the
ownership to MPSS.
Change-Id: I1ae7e61d1bc74d45bb1bc58b762c5d3d59e12501
Signed-off-by: Gokul krishna Krishnakumar <quic_gokukris@quicinc.com>
Some targets don't have dsm region to be setup by
remoteproc, so add a flag to check if we need to setup
the dsm region or not and enable for pineapple.
Change-Id: I1cdfa7ef05c3a59878ae4b07d5e0c776962a075b
Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
Signed-off-by: Gokul krishna Krishnakumar <quic_gokukris@quicinc.com>
MPSS DSM mem region is needed by Modem PDs. This change
sets it up before bringing MPSS out of reset.
Change-Id: Ic882b678f373deb5c61e250f8620b5dd4c092ee2
Signed-off-by: Satya Durga Srinivasu Prabhala <quic_satyap@quicinc.com>
Signed-off-by: Gokul krishna Krishnakumar <quic_gokukris@quicinc.com>
wakeup_enable bit sets the corresponding bit in the INTR_CFG register.
Also correct target bit to reflect its true position within the
INTR_CFG register.
This adds back a portion of commit 5ea61b95b8 ("pinctrl: qcom: Add
support to set wakeup_enable bit").
Change-Id: I50c4212c15cca02aff495c4af9ed5f91bc9cfa40
Signed-off-by: John Moon <quic_johmoo@quicinc.com>
Show max_avail_current to MAX_FLASH_CURRENT_MA when there is no
battery power supply device available.
Change-Id: I6a854509d0432cf4b234bbb39422ce0d3031913b
Signed-off-by: Anjelique Melendez <quic_amelende@quicinc.com>
Enable the following modules on pineapple, required
to use HWKM operations in TME.
CONFIG_MSM_TMECOM_QMP=m
CONFIG_QTI_HW_KEY_MANAGER=m.
Change-Id: If587bdd8e0c9d351e26c8fccea5807b01d7231b5
Signed-off-by: Gaurav Kashyap <quic_gaurkash@quicinc.com>
Set StopOnFl bit for etf to stop trace when FLUSH
is completed.
Change-Id: Idda16fcf1190960ac225c42ef41eaf01d8c286f2
Signed-off-by: Yuanfang Zhang <quic_yuanfang@quicinc.com>
Signed-off-by: Mao Jinlong <quic_jinlmao@quicinc.com>
Since not all the platforms have multi_ch_reg, the usage of
devm_platform_ioremap_resource_byname will cause "invalid resource"
error, split it and ioremap resource only when multi_ch_reg exists
to avoid the error message.
Change-Id: I2f11eb139c3d9626685206eb3707917d70d3592d
Signed-off-by: Huang Yiwei <quic_hyiwei@quicinc.com>
Update logic used in immediate reading path to ensure that
immediate reads performed on channels monitored in ADC_TM
on all SDAMs work correctly.
Fixes: 2b91fcd524b0 ("iio: qcom-spmi-adc5-gen3: update API for immediate conversions")
Change-Id: I4a5b44c493058eed5d43ebed4d7a91cdf0fef29b
Signed-off-by: Jishnu Prakash <quic_jprakash@quicinc.com>
we are specifically enabling an IRQ at resume/suspend time, hence
keep it disabled while registering for an interrupt. Else this
results into double enablement and kernel dumps stack.
Change-Id: I6a0675d34ba307bbbd76f6e958bc1ffe7bfb2c66
Signed-off-by: Mukesh Kumar Savaliya <quic_msavaliy@quicinc.com>
Add support for version 19 in socinfo which introduces fields
for reading fuse values to determine number of clusters,
boot cluster and boot core.
Change-Id: I0cce5109785fdd7b649b2185da7a9aff3cbdf5d0
Signed-off-by: Naman Jain <quic_namajain@quicinc.com>
This is a snapshot of the LLCC EDAC driver as of msm-5.15
commit <9f8b15103606> ("Merge "defconfig: autogvm: Enable
QCOM_LAZY_MAPPING for LVGVM"").
Change-Id: Ifba74ce95923e9e0e4f2d195b3eff88af263c111
Signed-off-by: Huang Yiwei <quic_hyiwei@quicinc.com>
Enable the SPMI PMIC arbiter debug driver so that all PMIC
peripheral registers can be accessed for debugging purposes.
Change-Id: I55438db91688c200caa043621c32d00db49ba93b
Signed-off-by: David Collins <quic_collinsd@quicinc.com>
Enable CONFIG_REGULATOR_QTI_OCP_NOTIFIER so that consumers can
receive notifications about regulator over-current (OCP) events.
Change-Id: I617c16aaba2d45bdc67721a9edb4880b63786e7e
Signed-off-by: David Collins <quic_collinsd@quicinc.com>
