Add ipc logging support for pmic_glink devices so that logs can
be obtained for debugging.
Change-Id: I3710ac0fb5b9d53d5db8d28967ed02f501364e64
Signed-off-by: Subbaraman Narayanamurthy <quic_subbaram@quicinc.com>
If the notification clients are taking too long or are stuck somewhere we
want to be notified of such problems. This change adds the notification
timeout logic that either causes a panic or dumps the stack when a timeout
occurs.
Change-Id: Ifaa7e20a697f920ffffd7345c9794d39a718f9b0
Signed-off-by: Gokul krishna Krishnakumar <gokukris@codeaurora.org>
[quic_gurus@quicinc.com: Fix Minor merge conflict]
Signed-off-by: Guru Das Srinagesh <quic_gurus@quicinc.com>
Support multi enter for unregister path.
Change-Id: I3dd37604e740582ee851c208a4c67fe08f20d83f
Signed-off-by: Maria Yu <quic_aiquny@quicinc.com>
[quic_clew@quicinc.com: This is a work around until remoteproc resolves
a race where unregister is called from multiple contexts]
Signed-off-by: Chris Lew <quic_clew@quicinc.com>
The change to defer excessive glink processing to threaded irq context
uses the IRQF_ONESHOT flags and assumes the hardirq handler will never
run when the threaded irq is running.
There are a couple instances where this does not hold true. One known
instance is during irq_resend() where an interrupt is resent in tasklet
context. In this case, it has been observed that the hard irq handler
will run even if the threaded portion of the interrupt is running.
Add a lock and state to check if the irq is running. If it is already
running, then bail out of the irq.
If threaded handler is already in execution when suspend happens and
next glink interrupt is received in suspend, interrupt handler returns
without waking up system.
Move wakeup logic in the beginning of interrupt handler.
Change-Id: Ied7808962e525ff0b7430d3fac666f7fee032722
Signed-off-by: Chris Lew <clew@codeaurora.org>
Used to indicate preferred userspace to external scripts which help pack
the kernel images.
Change-Id: If453042506198208160c85d214ee1700c8d65930
Signed-off-by: Peng Yang <quic_penyan@quicinc.com>
Add new reset_source_sink node to be able to disable all
active coresight devices.
Change-Id: Ic9daeb35d7aacd334911683d41a2f0f278719725
Signed-off-by: Tingwei Zhang <tingwei@codeaurora.org>
Signed-off-by: Mao Jinlong <jinlmao@codeaurora.org>
Currently the hw_regs->base array size is hardcoded to 3,
but some chips have more frequency domains than this,
which will result in buffer overflows
The array size should be dynamically allocated according
to hw_regs->domain_cnt, not hardcoded directly.
Change-Id: Ida14766fe77195aef41c6e754f2875b5a24fe742
Signed-off-by: Xubin Bai <quic_xubibai@quicinc.com>
This driver provides support for monitoring and tracing Coresight
Hardware Event across STM interface. It configures Coresight
Hardware Event mux control registers to select hardware events
based on user input.
Change-Id: I5c3c5ca70015abe7448b25777aedeeb289b8e2d3
Signed-off-by: Tao Zhang <taozha@codeaurora.org>
Signed-off-by: Mao Jinlong <quic_jinlmao@quicinc.com>
This driver provides support for Trigger Generation Unit that is
used to detect patterns or sequences on a given set of signals.
TGU is used to monitor a particular bus within a given region to
detect illegal transaction sequences or slave responses. It is also
used to monitor a data stream to detect protocol violations and to
provide a trigger point for centering data around a specific event
within the trace data buffer.
Change-Id: I84378e6134eb0e6eefb483004acabc73736200a2
Signed-off-by: Tao Zhang <taozha@codeaurora.org>
Signed-off-by: Mao Jinlong <quic_jinlmao@quicinc.com>
Enables support for ETM trace collection on remote processor using
CoreSight framework. Enabling this will allow turning on ETM
tracing on remote processor via sysfs by configuring the required
CoreSight components.
Change-Id: I46b7c31eb81bd3b6623b71cf6c4811ba2d99d360
Signed-off-by: Tao Zhang <taozha@codeaurora.org>
Signed-off-by: Mao Jinlong <quic_jinlmao@quicinc.com>
Some Coresight devices that HLOS does not have permission to access
or configure. Such as Coresight sink EUD, some TPDMs etc.
So there needs driver to register dummy devices as Coresight devices.
Provide Coresight API for dummy devices operations, such as enable
and disable dummy devices.
Build the Coresight path for dummy sink or dummy source for debugging.
Change-Id: I93b24a84f0b463f92c5e5cb69b53a86bf873e7a6
Signed-off-by: Tao Zhang <taozha@codeaurora.org>
Signed-off-by: Mao Jinlong <quic_jinlmao@quicinc.com>
Add the local clock gcc_ddrss_ubwcp_clk for the icc node
qnm_ubwc_p, then gcc_ddrss_ubwcp_clk can be scaled along
with the bandwidth of qnm_ubwc_p.
Change-Id: I47fe30106f07c10efa18aac5f5fa5f42b1f5ab2b
Signed-off-by: Xubin Bai <quic_xubibai@quicinc.com>
Enable the USB PHY drivers used on pineapple. This includes the QMP PHY
for SSUSB and EUSB2 PHY + repeater for HSUSB.
Change-Id: I9f4176c3628e14e10a1719ebfedbb99be86770d5
Signed-off-by: Wesley Cheng <quic_wcheng@quicinc.com>
Add support to scale local clocks along with BW votes using
the clk framework, as opposed to only voting shared clocks
through BCM and then voting to DFS to scale clocks.
Change-Id: I62190e08a382551b2759cee22ce4bd50e760604f
Signed-off-by: Xubin Bai <quic_xubibai@quicinc.com>
On newer chipsets there is an increase in traffic generated from the
remote for new usecases, this is resulting in the glink interrupt
handler running for an extended amount of time. In combination with the
IPCC architecture, this can starve out other users of IPCC including
other GLINKs.
Change the interrupt to a threaded interrupt to prevent the glink ISR
from starving the CPU with interrupts disabled. In order to make sure
performance for latency sensitive clients is preserved, handle up to
10 packets in hard irq context. Defer the remaining work to the
threaded interrupt if required.
Change-Id: I2f1b085c38c02d231f9a3da2fcce32b129be2012
Signed-off-by: Chris Lew <clew@codeaurora.org>
This snapshot is taken as of msm-5.15 'commit <c79afcd18535>
("va_minidump: Add md_unregister support for clients")'.
Change-Id: Ifb19f2867c40d91b108d90437be0b4ccd936664c
Signed-off-by: Chris Lew <quic_clew@quicinc.com>
Add dma_buf_vmap/vunmap to allow for DMA-BUF heap testing.
Change-Id: I75f0b27b2a143983117e2cc631f00a250ceb1c03
Signed-off-by: Chris Goldsworthy <quic_cgoldswo@quicinc.com>
Limiting to 4096, assuming this is used for virtual io block device. The
default maximum (256kB) would result in overflowing of bounce buffers
and stalling of IO (max_segments of 254 for block device and max
bounce size of 256kB could result in block layer submitting a huge IO
request that can never be finished successfully). With 4096, we have
the max size of request set to 254*4096, which is a reasonable space
to set aside per block device.
Change-Id: I8a3b0ec6d26a1b7f5ccdcee649f02c3556bce93b
Signed-off-by: Srivatsa Vaddagiri <vatsa@codeaurora.org>
Handled changed DT format to extract memory region address.
Change-Id: Ia6b2d77c018d8639fe5eeaf6883e472f477bacc7
Signed-off-by: Srivatsa Vaddagiri <vatsa@codeaurora.org>
Setting swiotlb_force to SWIOTLB_FORCE would force non virtual io
drivers also to use swiotlb. So avoid it.
Change-Id: I419700e9f38b0b00da22c8522f94edffd2fd8f52
Signed-off-by: Sreenad Menon <sreemeno@codeaurora.org>
In some cases, its possible that most of a VM's memory is not
accessible to virtual io backend drivers that run in the context of a
separate VM. A hypervisor could pre-share some limited memory between
both the VMs. Use such pre-arranged shared memory to allow data
exchange between front-end and back-end drivers. DMA ops are added to
virtual io (mmio) devices, which bounces buffers to and from the
pre-shared region.
Change-Id: I6cf61cd1ca4c8b848a6d6d1aa1d5023ce9341174
Signed-off-by: Sreenad Menon <sreemeno@codeaurora.org>
Signed-off-by: Srivatsa Vaddagiri <vatsa@codeaurora.org>
Remove the use of msi_finish function pointer as it is
removed from the msi.h header file.
Change-Id: I2a0972271e818efc387415cef7067124abeda422
Signed-off-by: Prudhvi Yarlagadda <quic_pyarlaga@quicinc.com>
