The phone seems to randomly crash when more than 1 CPU is enabled, which
is probably related to lack of some driver.
Restrict the device to only use a single core until this is solved.
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220319174645.340379-4-konrad.dybcio@somainline.org
The sleep clock name expected by GCC is actually "sleep" and not
"sleep_clk". Fix the clock-names value for it to make sure it is
provided.
Fixes: 9204da57cd65 ("arm64: dts: qcom: msm8994: Provide missing "xo_board" and "sleep_clk" to GCC")
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Reviewed-by: Petr Vorel <petr.vorel@gmail.com>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220319174645.340379-2-konrad.dybcio@somainline.org
The number of interrupt cells for the mdss interrupt controller is 1,
meaning there should only be one cell for the interrupt number, not two.
Drop the second cell containing (unused) irq flags.
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Fixes: 7c1dffd471 ("arm64: dts: qcom: sm8250.dtsi: add display system nodes")
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220302225411.2456001-5-dmitry.baryshkov@linaro.org
The number of interrupt cells for the mdss interrupt controller is 1,
meaning there should only be one cell for the interrupt number, not two.
Drop the second cell containing (unused) irq flags.
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Fixes: 08c2a076d1 ("arm64: dts: qcom: sdm845: Add dpu to sdm845 dts file")
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220302225411.2456001-4-dmitry.baryshkov@linaro.org
The number of interrupt cells for the mdss interrupt controller is 1,
meaning there should only be one cell for the interrupt number, not two.
Drop the second cell containing (unused) irq flags.
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Fixes: ab29028439 ("arm64: dts: qcom: sdm660: Add required nodes for DSI1")
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220302225411.2456001-3-dmitry.baryshkov@linaro.org
The number of interrupt cells for the mdss interrupt controller is 1,
meaning there should only be one cell for the interrupt number, not two.
Drop the second cell containing (unused) irq flags.
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Fixes: b52555d590 ("arm64: dts: qcom: sdm630: Add MDSS nodes")
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220302225411.2456001-2-dmitry.baryshkov@linaro.org
The number of interrupt cells for the mdss interrupt controller is 1,
meaning there should only be one cell for the interrupt number, not two.
Drop the second cell containing (unused) irq flags.
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Fixes: 12d5403757 ("arm64: dts: qcom: msm8996: Add DSI0 nodes")
Fixes: 3a4547c1fc ("arm64: qcom: msm8996.dtsi: Add Display nodes")
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220302225411.2456001-1-dmitry.baryshkov@linaro.org
Add device tree node for the first PCIe host found on the Qualcomm
SM8450 platform.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220301061500.2110569-3-dmitry.baryshkov@linaro.org
The LPASS(Low Power Audio Subsystem) clock provider have a bunch of generic
properties that are needed in a device tree. Also add clock ids for
LPASS core clocks and audio clock IDs for LPASS client to request for
the clocks.
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220223172248.18877-1-tdas@codeaurora.org
The huawei-g7 uses the msm8916-wcd-digital/analog audio codecs similar
to apq8016-sbc, so we can mostly copy paste it from there to make audio
work correctly. The main difference is the hphl-jack-type-normally-open
property, which is needed to avoid inverted audio jack detection.
Note that at least on my device the jack detection is not fully
reliable: sometimes headphones are detected as headsets (with
microphone). However, this is not a big problem for typical usage.
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220410195113.13646-3-stephan@gerhold.net
The comment with installation instructions in the huawei-g7 device tree
is a bit misleading and does not describe the recommended installation
steps very well. The bootloader is actually not patched; to avoid all
trouble with the vendor bootloader it is easier to bypass it completely
by jumping to a custom bootloader (e.g. based on the open-source LK
released by Qualcomm).
To avoid confusion, simplify the comment to state only the problem
and then refer to the wiki article which contains detailed suggested
installation instructions. This will also make it easier to keep it
up to date with new developments in the future.
Fixes: 55056b2291 ("arm64: dts: qcom: msm8916: Add device tree for Huawei Ascend G7")
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220410195113.13646-2-stephan@gerhold.net
Fix the following 'make dtbs_check' warning(s) by
using phy@ instead of lanes@ and by moving '#clock-cells' to
sub-node:
arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dt.yaml: ssphy@78000:
'lane@78200' does not match any of the regexes: '^phy@[0-9a-f]+$', 'pinctrl-[0-9]+'
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Rob Herring <robh@kernel.org>
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
Reviewed-by: Shawn Guo <shawn.guo@linaro.org>
[bjorn: s/clock-names/clock-cells/ per Shawn's feedback]
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220228123019.382037-7-bhupesh.sharma@linaro.org
Fix the 'make dtbs_check' warning:
arch/arm64/boot/dts/qcom/sm8450-qrd.dt.yaml: phy@1d87000:
'lanes@1d87400' does not match any of the regexes: '^phy@[0-9a-f]+$', 'pinctrl-[0-9]+'
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Rob Herring <robh@kernel.org>
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
Reviewed-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220228123019.382037-6-bhupesh.sharma@linaro.org
Fix the 'make dtbs_check' warning:
arch/arm64/boot/dts/qcom/sc7280-idp.dt.yaml: phy@1c0e000:
'lanes@1c0e200' does not match any of the regexes: '^phy@[0-9a-f]+$', 'pinctrl-[0-9]+'
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Rob Herring <robh@kernel.org>
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
Reviewed-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220228123019.382037-5-bhupesh.sharma@linaro.org
The following properties are not supported and causing dtbs_check
warnings.
- vdda-phy-max-microamp
- vdda-pll-max-microamp
- vddp-ref-clk-max-microamp
- vddp-ref-clk-always-on
arch/arm64/boot/dts/qcom/msm8996-xiaomi-gemini.dt.yaml: phy@627000:
'vdda-phy-max-microamp', 'vddp-ref-clk-always-on', 'vddp-ref-clk-max-microamp'
do not match any of the regexes: '^phy@[0-9a-f]+$', 'pinctrl-[0-9]+'
Drop them from QMP PHY nodes for 'msm8996-xiaomi' dts.
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Rob Herring <robh+dt@kernel.org>
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220228123019.382037-4-bhupesh.sharma@linaro.org
The BAM Data Multiplexer provides access to the network data channels
of modems integrated into many older Qualcomm SoCs, including MSM8916.
Add the nodes for the BAM DMA engine and BAM-DMUX to enable using WWAN
on smartphones/tablets based on MSM8916. This should work out of the box
with open-source WWAN userspace such as ModemManager.
The nodes are disabled by default to avoid loading unnecessary drivers
on devices that cannot use BAM-DMUX (e.g. DragonBoard 410c). However,
strictly speaking the nodes could be enabled by default since both the
bam_dma and bam_dmux driver will simply do nothing if the modem does
not announce any BAM-DMUX channels.
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220228225400.146555-3-stephan@gerhold.net
Most of SoC device trees do not provide the thermal_zones label. Thus
stop depending on it and use the full path to the thermal zones nodes.
Fixes: 7a3544e5d4 ("arm64: dts: qcom: pmr735a: Add temp-alarm support")
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220226205035.1826360-6-dmitry.baryshkov@linaro.org
Most of SoC device trees do not provide the thermal_zones label. Thus
stop depending on it and use the full path to the thermal zones nodes.
Fixes: 3795fe7d49 ("arm64: dts: qcom: pm8350c: Add temp-alarm support")
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220226205035.1826360-5-dmitry.baryshkov@linaro.org
Add temp-alarm device tree node and a default configuration for the
corresponding thermal zone for this PMIC. Temperatures are based on
downstream values.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220226205035.1826360-4-dmitry.baryshkov@linaro.org
Add temp-alarm device tree node and a default configuration for the
corresponding thermal zone for this PMIC. Temperatures are based on
downstream values.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220226205035.1826360-3-dmitry.baryshkov@linaro.org
Add temp-alarm device tree node and a default configuration for the
corresponding thermal zone for this PMIC. Temperatures are based on
downstream values.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220226205035.1826360-2-dmitry.baryshkov@linaro.org
The OnePlus 5/5T both have an NXP PN553 which is supported by the
nxp-nci-i2c driver in mainline. It detects/reads NFC tags using
"nfctool" and with the NearD test scripts data can also be written
to be received by another device.
Signed-off-by: Jami Kettunen <jami.kettunen@somainline.org>
Reviewed-by: Caleb Connolly <caleb@connolly.tech>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220225215642.3916-1-jami.kettunen@somainline.org
Rename the edp_out label in the sc7280 platform to mdss_edp_out
so that the nodes related to mdss are all grouped together in
the board specific files.
Signed-off-by: Sankeerth Billakanti <quic_sbillaka@quicinc.com>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/1647452154-16361-2-git-send-email-quic_sbillaka@quicinc.com
Enable the ethernet node, add the phy node and pinctrl for ethernet.
[bhsharma: Correct ethernet/rgmii related pinmuxs, specify multi-queues and
plug in the PHY interrupt for WOL]
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220325163537.1579969-3-bhupesh.sharma@linaro.org
Following sm8150/sm8250 update sdm845 capacity-dmips-mhz and
dynamic-power-coefficient based on the measurements [1], [2].
The energy model dynamic-power-coefficient values were calculated with
DPC = µW / MHz / V^2
for each OPP, and averaged across all OPPs within each cluster for the
final coefficient. Voltages were obtained from the qcom-cpufreq-hw
driver that reads voltages from the OSM LUT programmed into the SoC.
Normalized DMIPS/MHz capacity scale values for each CPU were calculated
from CoreMarks/MHz (CoreMark iterations per second per MHz), which
serves the same purpose. For each CPU, the final capacity-dmips-mhz
value is the C/MHz value of its maximum frequency normalized to
SCHED_CAPACITY_SCALE (1024) for the fastest CPU in the system.
For more details on measurement process see the commit message for the
commit 6aabed5526 ("arm64: dts: qcom: sm8250: Add CPU capacities and
energy model").
[1] https://github.com/kdrag0n/freqbench
[2] https://github.com/kdrag0n/freqbench/tree/master/results/sdm845/main
Cc: Danny Lin <danny@kdrag0n.dev>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220315141104.730235-1-dmitry.baryshkov@linaro.org
Several wakeup gpios supported by the Top Level Mode Multiplexer (TLMM)
block on sm8150 can be used as interrupt sources and these interrupts
are routed to the PDC interrupt controller.
So, specify PDC as the interrupt parent for the TLMM block.
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Vinod Koul <vkoul@kernel.org>
Cc: Rob Herring <robh@kernel.org>
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220226184028.111566-5-bhupesh.sharma@linaro.org
Enable the audio, compute, sensor and modem remoteproc and specify
firmware path for these on the Qualcomm SM8450 HDK.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220410205901.1672089-2-dmitry.baryshkov@linaro.org
On MSM8996 PCI controller bindings are not compatible with snps,dw-pcie
binding. The platform doesn't provide second (global) IRQ, it requires
additional glue code. To prevent it from probing against the dw-pcie
driver, remove corresponding compatible.
Fixes: ed965ef892 ("arm64: dts: qcom: msm8996: add support to pcie")
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220411115808.1976500-2-dmitry.baryshkov@linaro.org
