Commit Graph

1598 Commits

Author SHA1 Message Date
Elaine Zhang
1ce367190e clk: rockchip: rv1106: export pclk_mailbox clk id
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Change-Id: I84c8d8e3987af45b72db8eccbf97b7fc842f6205
2022-03-01 11:14:02 +08:00
Elaine Zhang
33b5055b63 clk: rockchip: add dt-binding header for rv1106
Add the dt-bindings header for the rv1106, that gets shared between
the clock controller and the clock references in the dts.
Add softreset ID for rv1106.

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Change-Id: Ia5bd903c6dc9caf925277fd42f873d8e8d6f643a
2022-01-25 17:55:08 +08:00
Elaine Zhang
6926e98d70 clk: rockchip: rk3588: export hdmirx_biu soft reset id
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Change-Id: I37c1f67bd62eabe3b0cfa2e1b304a3ae1950b66e
2022-01-25 16:41:58 +08:00
Tao Huang
f6909c028f Merge tag 'ASB-2021-12-05_12-5.10' of https://android.googlesource.com/kernel/common
https://source.android.com/security/bulletin/2021-12-01
CVE-2021-33909
CVE-2021-38204
CVE-2021-0961

* tag 'ASB-2021-12-05_12-5.10': (3010 commits)
  ANDROID: workqueue: export symbol of the function wq_worker_comm()
  ANDROID: GKI: Update symbols to symbol list
  ANDROID: vendor_hooks: Add hooks for binder proc transaction
  ANDROID: GKI: Add symbols abi for USB IP kernel modules.
  ANDROID: GKI: Fix file mode on mtk abi file
  UPSTREAM: erofs: fix deadlock when shrink erofs slab
  ANDROID: init_task: Init android vendor and oem data
  UPSTREAM: sched/core: Mitigate race cpus_share_cache()/update_top_cache_domain()
  ANDROID: Update symbol list for mtk
  UPSTREAM: erofs: fix unsafe pagevec reuse of hooked pclusters
  UPSTREAM: erofs: remove the occupied parameter from z_erofs_pagevec_enqueue()
  UPSTREAM: usb: dwc3: gadget: Fix null pointer exception
  ANDROID: fips140: support "evaluation testing" builds via build.sh
  FROMGIT: sched/scs: Reset task stack state in bringup_cpu()
  ANDROID: dma-buf: heaps: fix dma-buf heap pool pages stat
  ANDROID: ABI: Add several spi_mem related symbols
  UPSTREAM: spi: spi-mem: add spi_mem_dtr_supports_op()
  ANDROID: gki_defconfig: enable CONFIG_SPI_MEM
  ANDROID: ABI: Add several iio related symbols
  ANDROID: ABI: Update symbol list for IMX
  ...

Change-Id: I09cddc92fa34553b944e62cc5cbbba94a84e5437

Conflicts:
	arch/arm/boot/dts/rk322x.dtsi
	arch/arm64/boot/dts/rockchip/rk3399.dtsi
	drivers/dma-buf/heaps/system_heap.c
	drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c
	drivers/gpu/drm/rockchip/rockchip_drm_vop.c
	drivers/gpu/drm/rockchip/rockchip_lvds.c
	drivers/gpu/drm/rockchip/rockchip_vop_reg.c
	drivers/mtd/nand/spi/core.c
	drivers/pci/controller/pcie-rockchip-host.c
	drivers/soc/rockchip/Kconfig
	drivers/usb/dwc3/core.c
	drivers/usb/dwc3/core.h
2021-12-14 17:09:02 +08:00
Elaine Zhang
1f57d9eb1b clk: rockchip: rk3588: export clk_phy0/1_ref_alt_p/m clk id
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Change-Id: I149c43cd77f777c9d45c095be8c0c77c126b56d2
2021-12-02 18:10:18 +08:00
Wyon Bi
6f62dc64fe Revert "clk: rockchip: rk3588: export pclk_vopgrf id for vop"
This reverts commit 9c9db5fd41.

Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
Change-Id: I11ef7f3e52cb7512acbc638a67e75c9295ddbbdd
2021-11-25 15:10:00 +08:00
Wyon Bi
9c9db5fd41 clk: rockchip: rk3588: export pclk_vopgrf id for vop
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
Change-Id: I1d1d2b8d0a87763f1671ce0bc6f9933caaac3800
2021-11-23 20:59:23 +08:00
Elaine Zhang
d3a274cb5e Revert "clk: rockchip: rk3588: export clk_gmac id"
This reverts commit de8a7dc11e.

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Change-Id: I10be8115666498baf872a40fc9c72964744f3243
2021-11-05 11:32:52 +08:00
Elaine Zhang
9528bfc14a clk: rockchip: rk3588: export clk_aux16m_x id for dp
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Change-Id: Iec7deb4005d4ce3b842eccd89018a7d9f335434c
2021-10-28 16:31:46 +08:00
Wyon Bi
3082499844 clk/rockchip/regmap: rk628: Add support for clk_testout
Change-Id: I71f5ca1d4002d45438ff9d038ccc7eef5a28a857
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
2021-10-18 16:56:42 +08:00
Elaine Zhang
de8a7dc11e clk: rockchip: rk3588: export clk_gmac id
The mux of Clk_gmac is special and is in the php_grf register.

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Change-Id: I678f87a48b04a9701029f455d2e67378ca9072b6
2021-09-06 19:18:27 +08:00
Elaine Zhang
5df480db6f clk: rockchip: rk3588: rename some clks
1) rename pvtm clks name;
2) usbdp and mipidphy share one ref clk;
3) hdmitx, hdmirx, and usb2phy share one ref clk;

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Change-Id: I2c85609359424ed388a051f4bb04b0d401c05d12
2021-08-27 17:42:18 +08:00
Elaine Zhang
4834c511d2 clk: rockchip: rk3399: fix up the spi softrst ID
fix up the spi3 and spi5 softrst ID.

Change-Id: Ib8870ef765284e04674ce80acf0b4702ed77cebc
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
2021-08-25 17:58:42 +08:00
Mark Yao
21dc499588 rockchip: clk: rk3399: default enable dual pll for vop
Change-Id: I88a2a549eaafa91e4159f262a5f5838c834a89e9
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
2021-08-25 17:07:22 +08:00
Elaine Zhang
958d13f841 arm64: dts: rockchip: rk3588: fix up the clocks
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Change-Id: I4136922bea4e4e47e580a644593f7b98310623e7
2021-08-23 19:16:56 +08:00
Elaine Zhang
9a7bdd5455 clk: rockchip: add dt-binding header for rk3588
Add the dt-bindings header for the rk3588, that gets shared between
the clock controller and the clock references in the dts.
Add softreset ID for rk3588.

Change-Id: I9fa9d27a187a6951c5c1cf210b0eff988a41457e
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
2021-08-20 15:11:16 +08:00
Tao Huang
4bb7503ad3 dt-bindings: clock: Remove unused rockchip files
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
Change-Id: I9a528f75413a7376407afff4e0737747d6f66a87
2021-08-11 16:32:38 +08:00
Randy Li
3eddd5dd86 clk: rockchip: rk3036: export the sfc clocks
The serial Flash controller on the rk3036 would request
two clock nodes.

Change-Id: Iaa50c4a25602a68241b0b9b2f186e4c7e55bc3da
Signed-off-by: Randy Li <randy.li@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
2021-08-04 21:26:51 +08:00
Caesar Wang
54a9bb2c72 clk: rockchip: export SCLK_I2S_PRE and SCLK_I2S_FRAC of i2s on rk3036
Change-Id: I627c8c2582be2b27414e7b82e9d56dd560f68e64
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
2021-08-04 21:26:51 +08:00
Randy Li
e35fd036b3 clk: rockchip: rk3036: export the hevc core clock
The clock hevc core will be used to drive the hevc decoder.

Change-Id: Ic1298ce1edd07f86e5c243e3a2c9876481f4cba9
Signed-off-by: Randy Li <randy.li@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
2021-08-04 21:26:51 +08:00
Finley Xiao
f467c0ecb0 clk: rockchip: rk3066a: Rename i2s hclk id
Change-Id: I0a5ccf1846950353ea6fc6980c1c4a4fb3457fd1
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
2021-08-04 20:40:34 +08:00
Elaine Zhang
3151edc8a4 clk: rockchip: Avoid __clk_lookup() calls
clk pointer gets cached in the driver's private data and
can be used later instead of a __clk_lookup() call.

clk provider clk_data.clks[] and we can reference
the clk pointers directly rather than using __clk_lookup()
with global names.

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Change-Id: I058413a912e0eaf5bf551d2515ad55ae28709985
2021-07-22 16:08:56 +08:00
Lucas Stach
581098969c clk: imx8mq: remove SYS PLL 1/2 clock gates
[ Upstream commit c586f53ae1 ]

Remove the PLL clock gates as the allowing to gate the sys1_pll_266m breaks
the uSDHC module which is sporadically unable to enumerate devices after
this change. Also it makes AMP clock management harder with no obvious
benefit to Linux, so just revert the change.

Link: https://lore.kernel.org/r/20210528180135.1640876-1-l.stach@pengutronix.de
Fixes: b04383b6a5 ("clk: imx8mq: Define gates for pll1/2 fixed dividers")
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Abel Vesa <abel.vesa@nxp.com>
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
2021-07-14 16:56:20 +02:00
Sugar Zhang
2b1b3a5b70 clk: rockchip: px30: Export clk id for sclk_i2s0_tx/rx mux
Change-Id: I697d20fb0c69f9dcd76aaf2d18d666db2241360d
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
2021-07-02 17:17:40 +08:00
Elaine Zhang
35e637b1a5 clk: rockchip: rk3128: add hclk_sfc
Change-Id: I20d0975156dc73bcdd02c09b7ecb815d5aca6bc6
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
2021-05-18 20:33:37 +08:00
Elaine Zhang
9322b4700a clk: rockchip: rk3288: export PCLK_PD_PMU and PCLK_PD_ALIVE clock id
Change-Id: Ie0550d9528367fa070328562fad2e597a5d6d7f7
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
2021-05-18 20:33:36 +08:00
Elaine Zhang
b1d64bdb31 clk: rockchip: rk3368: add aclk_cci_pre ID
Change-Id: I855e79023a9e244c2db37af88a075a4ef4c36aec
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
2021-05-18 20:33:36 +08:00
Elaine Zhang
64f77336b9 clk: rockchip: rk3399: fix up the clk tree description for clk_uart4
slove clk_uart4 set rate error.

Change-Id: Icf8f36a5c68658ed92a1b794dc68f37c729d2646
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
2021-04-02 11:51:49 +08:00
Elaine Zhang
7b581139c3 clk: rockchip: rk3399: fix up some regs description error
Change-Id: Ia992b20f13ba7037b93fcd2fbd67a4d6b3fd1266
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
2021-04-02 11:51:07 +08:00
Elaine Zhang
9de42c75ff clk: rockchip: rk3399: export SCLK_I2SOUT_SRC clk ID for i2s
Change-Id: Ifbcea830e5f49946c1feea3f51d125e6ed566d5f
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
2021-04-02 11:50:54 +08:00
Elaine Zhang
d658ee9626 clk: rockchip: rk3399: export CIF_OUT_SRC clock id for cif
Change-Id: I77423891821dae0412dda4414222ba64bd0a4a4a
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
2021-04-02 11:50:37 +08:00
Elaine Zhang
1f7732bedf clk: rockchip: rk3399: make the cpll as parent just for vop
others clk change it's parent from cpll to dummy_cpll.
the vop's parent just vpll and cpll,
make sure each vop have it's own pll as parent.

Change-Id: Ia61e10918e14a69c053455018ddf0183ff15ea19
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
2021-04-02 11:49:52 +08:00
Xing Zheng
fda5ee0f9a clk: rockchip: rk3399: export 480M_SRC clock id for usbphy0/usbphy1
Change-Id: Icd566864d3651e7b64ee8209b66e8a326011422f
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
2021-04-02 11:49:52 +08:00
Tao Huang
bc69b758ef Merge remote branch 'android12-5.10' of https://android.googlesource.com/kernel/common
* android12-5.10: (176331 commits)
  ANDROID: GKI: Enable bounds sanitizer
  ANDROID: Allow HAS_LTO_CLANG with KASAN_HW_TAGS
  ANDROID: abi_gki_aarch64_qcom: Add cpufreq related symbols
  ANDROID: cpufreq: Add a restricted vendor hook for freq transition
  ANDROID: scsi: ufs: add hooks to track ufs commands
  ANDROID: Fix compilation error when CPU_FREQ is disabled
  BACKPORT: kasan, arm64: allow using KUnit tests with HW_TAGS mode
  Revert "FROMGIT: kasan, arm64: allow using KUnit tests with HW_TAGS mode"
  Revert "BACKPORT: kasan: remove redundant config option"
  UPSTREAM: arm/kasan: fix the array size of kasan_early_shadow_pte[]
  FROMGIT: KVM: arm64: Workaround firmware wrongly advertising GICv2-on-v3 compatibility
  FROMGIT: KVM: arm64: Rename __vgic_v3_get_ich_vtr_el2() to __vgic_v3_get_gic_config()
  FROMGIT: KVM: arm64: Don't access PMSELR_EL0/PMUSERENR_EL0 when no PMU is available
  FROMGIT: KVM: arm64: Turn kvm_arm_support_pmu_v3() into a static key
  FROMGIT: KVM: arm64: Fix nVHE hyp panic host context restore
  FROMGIT: KVM: arm64: Avoid corrupting vCPU context register in guest exit
  FROMLIST: arm64: cpufeatures: Fix handling of CONFIG_CMDLINE for idreg overrides
  ANDROID: sched: Add vendor hook for uclamp_eff_value
  ANDROID: abi_gki_aarch64_qcom: Add CFS scheduler symbols
  ANDROID: GKI: Add mempool APIs to the symbol list
  ...

Change-Id: I4ed13984b97bc531d1dae61920457f31b84190e9

Conflicts:
	Documentation/devicetree/bindings/nvmem/rockchip-otp.txt
	arch/arm64/boot/dts/rockchip/px30.dtsi
	arch/arm64/boot/dts/rockchip/rk3308.dtsi
	arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dts
	drivers/clk/rockchip/Kconfig
	drivers/clk/rockchip/clk-rk3308.c
	drivers/gpu/drm/rockchip/rk3066_hdmi.c
	drivers/gpu/drm/rockchip/rockchip_rgb.c
	drivers/media/i2c/imx219.c
	drivers/nvmem/rockchip-otp.c
	drivers/power/supply/cw2015_battery.c
	sound/soc/codecs/cx2072x.c
	sound/soc/codecs/cx2072x.h
	sound/soc/codecs/rk3328_codec.c
2021-03-17 18:07:51 +08:00
Tao Huang
251c226c35 rk: revert to v4.19
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
Change-Id: I502dce68b639df4ebf5a1688e0dc2e5c5763ebc2
2021-03-17 18:05:39 +08:00
Sugar Zhang
7ddb8b2d97 clk: rockchip: rk3568: Allow config i2s mclk as out/in
This patch exports I2Sx_IOE to allow user to config mclk
direction from DT.

e.g.

i2s2 mclk as output:

&ext_codec {
	clocks = <&cru I2S2_MCLKOUT>;
	clock-names = "mclk";
	assigned-clocks = <&cru I2S2_MCLK_IOE>, <&cru I2S2_MCLKOUT>;
	assigned-clock-rates = <0>, <12288000>;
	assigned-clock-parents = <&cru I2S2_MCLKOUT>;
};

clk summary:

gpll                           6        9        0  1188000000
  clk_i2s2_2ch_src             0        0        0   594000000
    clk_i2s2_2ch_frac          0        0        0    12288000
      clk_i2s2_2ch             0        0        0    12288000
        mclk_i2s2_2ch          0        0        0    12288000
          i2s2_mclkout         0        0        0    12288000
            i2s2_mclk_ioe      0        0        0    12288000

i2s2 mclk as input:

&ext_codec {
	clocks = <&i2s2_mclkin>;
	clock-names = "mclk";
	assigned-clocks = <&cru I2S2_MCLK_IOE>, <&cru CLK_I2S2_2CH>;
	assigned-clock-parents = <&i2s2_mclkin>, <&i2s2_mclkin>;
};

clk summary:

i2s2_mclkin                    0        0        0    12288000
  clk_i2s2_2ch                 0        0        0    12288000
    mclk_i2s2_2ch              0        0        0    12288000
  i2s2_mclk_ioe                0        0        0    12288000

Change-Id: I57d10ea02b65bf14d2c2f9ff403f06ec4c33c610
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
2021-03-11 12:08:29 +08:00
Tao Huang
3dccc182fe dt-bindings: clock: Remove rk_system_status.h
Which is replaced by rockchip-system-status.h.

Signed-off-by: Tao Huang <huangtao@rock-chips.com>
Change-Id: Iaebf0f7f15b0becae05193f73d4b6d6816175b2e
2020-12-30 20:29:19 +08:00
YouMin Chen
19f9ea4b8e dt-bindings: clock: rk3568-cru: add clock ID SCLK_DDRCLK
Change-Id: Ie029065bda4de0fb764acf328c058c545c4176d6
Signed-off-by: YouMin Chen <cym@rock-chips.com>
2020-12-23 12:53:49 +08:00
Elaine Zhang
0657602584 clk: rockchip: rk3568: export cpll_xxx clk id for more function
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Change-Id: I5f310f9b857623a5a204ab9b5f0a4befde894684
2020-12-07 09:18:27 +08:00
Finley Xiao
3256732d55 clk: rockchip: rv1126: Add CLK_32K_IOE support
Add clk_32k_ioe to select 32k io as input or output.

Change-Id: I2c32af4bded53c91280a0dbbd54af17f2f90e843
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
2020-11-30 17:37:45 +08:00
Elaine Zhang
e13a0ea1af clk: rockchip: rk3568: export SCLK_32K_IOE clock id
Add clk_32k_ioe to select 32k io as input or output.

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Change-Id: I8347b34b43244b1dca0217d9af56fcf9c414d18e
2020-11-18 15:18:26 +08:00
Elaine Zhang
7e7e372271 dt-bindings: clock: rk3568: update the pcie soft reset id
Updates missing parts of the TRM.

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Change-Id: Ia24cd2986f7b0f11884260132aa4f5782eb58c52
2020-11-12 18:23:05 +08:00
Elaine Zhang
23dfbd105e clk: rockchip: rk3568 export clk id CPLL_333M
cpll_333m need change rate by ebc.

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Change-Id: I39cf3b436d0822c5e9be74f0fa181a74960c3e57
2020-11-12 17:28:31 +08:00
Sugar Zhang
b2b6762e9a clk: rockchip: rk3568: Export id for CLK_I2Sx MUX
Change-Id: I19245516504c06a4bc484cc4b20816ba9490c4fc
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
2020-11-10 14:44:39 +08:00
Elaine Zhang
3ea0c615c9 dt-bindings: clock: rk3568: fix up the clk_hdmic_cec id repeat definition
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Change-Id: I2ec34d4c27d6b8dbac884fa01bcd66a2918b59ad
2020-11-10 14:36:54 +08:00
Elaine Zhang
925dc1b993 clk: rockchip: rk3568: update the pmucru ref clk
Pmucru updates missing parts of the TRM.

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Change-Id: Idee0b51064c7579dfaeb03118e9d1eaae716d9e7
2020-11-09 10:02:51 +08:00
Linus Torvalds
e533cda12d ARM: Devicetree updates
As usual, most of the changes are to devicetrees. Besides smaller fixes,
 some refactorings and cleanups, some of the new platforms and chips
 (or significant features) supported are below:
 
 Broadcom boards:
  - Cisco Meraki MR32 (BCM53016-based)
  - BCM2711 (RPi4) display pipeline support
 
 Actions Semi boards:
  - Caninos Loucos Labrador SBC (S500-based)
  - RoseapplePi SBC (S500-based)
 
 Allwinner SoCs/boards:
  - A100 SoC with Perf1 board
  - Mali, DMA, Cetrus and IR support for R40 SoC
 
 Amlogic boards:
  - Libretch S905x CC V2 board
  - Hardkernel ODROID-N2+ board
 
 Aspeed boards/platforms:
  - Wistron Mowgli (AST2500-based, Power9 OpenPower server)
  - Facebook Wedge400 (AST2500-based, ToR switch)
 
 Hisilicon SoC:
  - SD5203 SoC
 
 Nvidia boards:
  - Tegra234 VDK, for pre-silicon Orin SoC
 
 NXP i.MX boards:
  - Librem 5 phone
  - i.MX8MM DDR4 EVK
  - Variscite VAR-SOM-MX8MN SoM
  - Symphony board
  - Tolino Shine 2 HD
  - TQMa6 SoM
  - Y Soft IOTA Orion
 
 Rockchip boards:
  - NanoPi R2S board
  - A95X-Z2 board
  - more Rock-Pi4 variants
 
 STM32 boards:
  - Odyssey SOM board (STM32MP157CAC-based)
  - DH DRC02 board
 
 Toshiba SoCs/boards:
  - Visconti SoC and TPMV7708 board
 -----BEGIN PGP SIGNATURE-----
 
 iQJDBAABCgAtFiEElf+HevZ4QCAJmMQ+jBrnPN6EHHcFAl+TVacPHG9sb2ZAbGl4
 b20ubmV0AAoJEIwa5zzehBx37MMP/imMO5e0QY1/7xxXWm4Kgc/Uffqw2Dvhj74a
 4Nrudwz6oUFGpZzIFYxqeCeWwotjA0nXmvM4Nl/SbxtlbV6nY/JrOL1OJToaGY0z
 Oc1jdA0MdXITdi6Xl5PTRqDeIHTSUmTclZWi5gvT7LFEvHog3mquJ7PiNTrjyuV0
 9BmHipwfmH6V5gDJZvN2dDlkhy0cpQKJFw7ylKCL89UNiEAd2QtNG0d0RLdz7yPX
 IGdecFelOhG9MSZyuFYYB2HOI33ukjZ9dA+yFy7BWOqegf/Z5hI02mxpke7Sys/5
 4XEN7ksSSYr6sm3h9XNW++IYkapZ9y/ZW+sQdiBZ3GMOwMXj02TdRkpC7f+FgAPo
 Hl7yXodGmXynL6ULu7/lIbBvqfWkLcwfVCYZx6PoWRE2q5g5ifoYp9b8kI5cLXrb
 BJn85XIuIaoO0cgrq7EzZnksaiwY1CNL84mYgkKRCGbBoJKHRiU+8Ilm5SKzk3kq
 KJ0gmbwFMjvTYxs3g6LPCo0jUNLjmLQMr0tL7iHDWkk5uqA+gfjKSLQfPby3jrMr
 6RDZBzMB+tPz1e++RWo41XD/Mm2kw8MGstsCOLzk2TdLh7e3fPfU4g7m0aqs/Q1y
 +LCqshffF/XVzV2uTFHDUGWufIM9nY6rdzuBc+JACJ5E+QyDg1tGKtMB3TYqgdN2
 aRY3NLSv
 =xjfB
 -----END PGP SIGNATURE-----

Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

Pull ARM Devicetree updates from Olof Johansson:
 "As usual, most of the changes are to devicetrees.

  Besides smaller fixes, some refactorings and cleanups, some of the new
  platforms and chips (or significant features) supported are below:

  Broadcom boards:
   - Cisco Meraki MR32 (BCM53016-based)
   - BCM2711 (RPi4) display pipeline support

  Actions Semi boards:
   - Caninos Loucos Labrador SBC (S500-based)
   - RoseapplePi SBC (S500-based)

  Allwinner SoCs/boards:
   - A100 SoC with Perf1 board
   - Mali, DMA, Cetrus and IR support for R40 SoC

  Amlogic boards:
   - Libretch S905x CC V2 board
   - Hardkernel ODROID-N2+ board

  Aspeed boards/platforms:
   - Wistron Mowgli (AST2500-based, Power9 OpenPower server)
   - Facebook Wedge400 (AST2500-based, ToR switch)

  Hisilicon SoC:
   - SD5203 SoC

  Nvidia boards:
   - Tegra234 VDK, for pre-silicon Orin SoC

  NXP i.MX boards:
   - Librem 5 phone
   - i.MX8MM DDR4 EVK
   - Variscite VAR-SOM-MX8MN SoM
   - Symphony board
   - Tolino Shine 2 HD
   - TQMa6 SoM
   - Y Soft IOTA Orion

  Rockchip boards:
   - NanoPi R2S board
   - A95X-Z2 board
   - more Rock-Pi4 variants

  STM32 boards:
   - Odyssey SOM board (STM32MP157CAC-based)
   - DH DRC02 board

  Toshiba SoCs/boards:
   - Visconti SoC and TPMV7708 board"

* tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (638 commits)
  ARM: dts: nspire: Fix SP804 users
  arm64: dts: lg: Fix SP804 users
  arm64: dts: lg: Fix SP805 clocks
  ARM: mstar: Fix up the fallout from moving the dts/dtsi files
  ARM: mstar: Add mstar prefix to all of the dtsi/dts files
  ARM: mstar: Add interrupt to pm_uart
  ARM: mstar: Add interrupt controller to base dtsi
  ARM: dts: meson8: remove two invalid interrupt lines from the GPU node
  arm64: dts: ti: k3-j7200-common-proc-board: Add USB support
  arm64: dts: ti: k3-j7200-common-proc-board: Configure the SERDES lane function
  arm64: dts: ti: k3-j7200-main: Add USB controller
  arm64: dts: ti: k3-j7200-main.dtsi: Add USB to SERDES lane MUX
  arm64: dts: ti: k3-j7200-main: Add SERDES lane control mux
  dt-bindings: ti-serdes-mux: Add defines for J7200 SoC
  ARM: dts: hisilicon: add SD5203 dts
  ARM: dts: hisilicon: fix the system controller compatible nodes
  arm64: dts: zynqmp: Fix leds subnode name for zcu100/ultra96 v1
  arm64: dts: zynqmp: Remove undocumented u-boot properties
  arm64: dts: zynqmp: Remove additional compatible string for i2c IPs
  arm64: dts: zynqmp: Rename buses to be align with simple-bus yaml
  ...
2020-10-24 10:44:18 -07:00
Stephen Boyd
5f56888fad Merge branches 'clk-ingenic', 'clk-at91', 'clk-kconfig', 'clk-imx', 'clk-qcom', 'clk-prima2' and 'clk-bcm' into clk-next
- Support qcom SM8150/SM8250 video and display clks
 - Change how qcom's display port clks work

* clk-ingenic:
  clk: ingenic: Respect CLK_SET_RATE_PARENT in .round_rate
  clk: ingenic: Don't tag custom clocks with CLK_SET_RATE_PARENT
  clk: ingenic: Don't use CLK_SET_RATE_GATE for PLL
  clk: ingenic: Use readl_poll_timeout instead of custom loop
  clk: ingenic: Use to_clk_info() macro for all clocks

* clk-at91:
  clk: at91: sam9x60: support only two programmable clocks
  clk: at91: clk-sam9x60-pll: remove unused variable
  clk: at91: clk-main: update key before writing AT91_CKGR_MOR
  clk: at91: remove the checking of parent_name

* clk-kconfig:
  clk: Restrict CLK_HSDK to ARC_SOC_HSDK

* clk-imx:
  clk: imx8mq: Fix usdhc parents order
  clk: imx: imx21: Remove clock driver
  clk: imx: gate2: Fix a few typos
  clk: imx: Fix and update kerneldoc
  clk: imx: fix i.MX7D peripheral clk mux flags
  clk: imx: fix composite peripheral flags
  clk: imx: Correct the memrepair clock on imx8mp
  clk: imx: Correct the root clk of media ldb on imx8mp
  clk: imx: vf610: Add CRC clock
  clk: imx: Explicitly include bits.h
  clk: imx8qxp: Support building i.MX8QXP clock driver as module
  clk: imx8m: Support module build
  clk: imx: Add clock configuration for ARMv7 platforms
  clk: imx: Support building i.MX common clock driver as module
  clk: composite: Export clk_hw_register_composite()
  clk: imx6sl: Use BIT(x) to avoid shifting signed 32-bit value by 31 bits

* clk-qcom:
  clk: qcom: gdsc: Keep RETAIN_FF bit set if gdsc is already on
  clk: qcom: Add display clock controller driver for SM8150 and SM8250
  dt-bindings: clock: add QCOM SM8150 and SM8250 display clock bindings
  clk: qcom: add video clock controller driver for SM8250
  clk: qcom: add video clock controller driver for SM8150
  dt-bindings: clock: add SM8250 QCOM video clock bindings
  dt-bindings: clock: add SM8150 QCOM video clock bindings
  dt-bindings: clock: combine qcom,sdm845-videocc and qcom,sc7180-videocc
  clk: qcom: gcc-msm8994: Add missing clocks, resets and GDSCs
  clk/qcom: fix spelling typo
  clk: qcom: gcc-sdm660: Fix wrong parent_map
  clk: qcom: dispcc: Update DP clk ops for phy design
  clk: qcom: gcc-msm8939: remove defined but not used variables
  clk: qcom: ipq8074: make pcie0_rchng_clk_src static

* clk-prima2:
  clk: clk-prima2: fix return value check in prima2_clk_init()

* clk-bcm:
  clk: bcm2835: add missing release if devm_clk_hw_register fails
  clk: bcm: rpi: Add register to control pixel bvb clk
2020-10-20 11:47:07 -07:00
Stephen Boyd
3ab9a54f76 Merge branches 'clk-simplify', 'clk-ti', 'clk-tegra', 'clk-rockchip' and 'clk-mediatek' into clk-next
- Small non-critical fixes for TI clk driver
 - Support Mediatek MT8167 clks

* clk-simplify:
  clk: mediatek: fix platform_no_drv_owner.cocci warnings
  clk: mediatek: mt7629: simplify the return expression of mtk_infrasys_init
  clk: mediatek: mt6797: simplify the return expression of mtk_infrasys_init

* clk-ti:
  clk: ti: dra7: add missing clkctrl register for SHA2 instance
  clk: ti: clockdomain: fix static checker warning
  clk: ti: autoidle: add checks against NULL pointer reference
  clk: keystone: sci-clk: add 10% slack to set_rate
  clk: keystone: sci-clk: cache results of last query rate operation
  clk: keystone: sci-clk: fix parsing assigned-clock data during probe

* clk-tegra:
  clk: tegra: Drop !provider check in tegra210_clk_emc_set_rate()

* clk-rockchip:
  clk: rockchip: Initialize hw to error to avoid undefined behavior
  clk: rockchip: rk3399: Support module build
  clk: rockchip: fix the clk config to support module build
  clk: rockchip: Export some clock common APIs for module drivers
  clk: rockchip: Export rockchip_register_softrst()
  clk: rockchip: Export rockchip_clk_register_ddrclk()
  clk: rockchip: Use clk_hw_register_composite instead of clk_register_composite calls
  clk: rockchip: rk3308: drop unused mux_timer_src_p

* clk-mediatek:
  clk: mediatek: Add MT8167 clock support
  dt-bindings: clock: mediatek: add bindings for MT8167 clocks
  clk: mediatek: add UART0 clock support
2020-10-20 11:46:47 -07:00
Stephen Boyd
9d3261628a Merge branches 'clk-renesas', 'clk-amlogic', 'clk-allwinner', 'clk-samsung', 'clk-doc' and 'clk-unused' into clk-next
- Remove various unused variables in clk drivers

* clk-renesas:
  clk: renesas: rcar-gen3: Update description for RZ/G2
  clk: renesas: cpg-mssr: Add support for R-Car V3U
  clk: renesas: cpg-mssr: Add register pointers into struct cpg_mssr_priv
  clk: renesas: cpg-mssr: Use enum clk_reg_layout instead of a boolean flag
  dt-bindings: clock: renesas,cpg-mssr: Document r8a779a0
  dt-bindings: clock: Add r8a779a0 CPG Core Clock Definitions
  dt-bindings: power: Add r8a779a0 SYSC power domain definitions
  clk: renesas: rcar-gen2: Rename vsp1-(sy|rt) clocks to vsp(s|r)
  clk: renesas: r8a7742: Add clk entry for VSPR

* clk-amlogic:
  clk: meson: make shipped controller configurable
  clk: meson: g12a: mark fclk_div2 as critical
  clk: meson: axg-audio: fix g12a tdmout sclk inverter
  clk: meson: axg-audio: separate axg and g12a regmap tables
  clk: meson: add sclk-ws driver

* clk-allwinner:
  clk: sunxi-ng: sun8i: r40: Use sigma delta modulation for audio PLL
  clk: sunxi-ng: add support for the Allwinner A100 CCU
  dt-bindings: clk: sunxi-ccu: add compatible string for A100 CCU and R-CCU

* clk-samsung:
  clk: s2mps11: initialize driver via module_platform_driver
  clk: samsung: Use cached clk_hws instead of __clk_lookup() calls
  clk: samsung: exynos5420/5250: Add IDs to the CPU parent clk definitions
  clk: samsung: Add clk ID definitions for the CPU parent clocks
  clk: samsung: exynos5420: Avoid __clk_lookup() calls when enabling clocks
  clk: samsung: exynos5420: Add definition of clock ID for mout_sw_aclk_g3d
  clk: samsung: Keep top BPLL mux on Exynos542x enabled

* clk-doc:
  clk: davinci: add missing kerneldoc
  clk: fixed: add missing kerneldoc

* clk-unused:
  clk: socfpga: agilex: Remove unused variable 'cntr_mux'
  clk: si5341: drop unused 'err' variable
  clk: mmp: pxa1928: drop unused 'clk' variable
  clk: at91: drop unused at91sam9g45_pcr_layout
2020-10-20 11:46:34 -07:00