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clk: rockchip: rk3568: export cpll_xxx clk id for more function

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Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Change-Id: I5f310f9b857623a5a204ab9b5f0a4befde894684
This commit is contained in:
Elaine Zhang 2020-12-07 09:18:27 +08:00
parent 3b060980d1
commit 0657602584
2 changed files with 15 additions and 7 deletions
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14
drivers/clk/rockchip/clk-rk3568.c
View File

@ -483,28 +483,28 @@ static struct rockchip_clk_branch rk3568_clk_branches[] __initdata = {
COMPOSITE_NOMUX(0, "gpll_20m", "gpll", CLK_IGNORE_UNUSED,
RK3568_CLKSEL_CON(78), 0, 6, DFLAGS,
RK3568_CLKGATE_CON(35), 6, GFLAGS),
COMPOSITE_NOMUX(0, "cpll_500m", "cpll", CLK_IGNORE_UNUSED,
COMPOSITE_NOMUX(CPLL_500M, "cpll_500m", "cpll", CLK_IGNORE_UNUSED,
RK3568_CLKSEL_CON(78), 8, 5, DFLAGS,
RK3568_CLKGATE_CON(35), 7, GFLAGS),
COMPOSITE_NOMUX(CPLL_333M, "cpll_333m", "cpll", CLK_IGNORE_UNUSED,
RK3568_CLKSEL_CON(79), 0, 5, DFLAGS,
RK3568_CLKGATE_CON(35), 8, GFLAGS),
COMPOSITE_NOMUX(0, "cpll_250m", "cpll", CLK_IGNORE_UNUSED,
COMPOSITE_NOMUX(CPLL_250M, "cpll_250m", "cpll", CLK_IGNORE_UNUSED,
RK3568_CLKSEL_CON(79), 8, 5, DFLAGS,
RK3568_CLKGATE_CON(35), 9, GFLAGS),
COMPOSITE_NOMUX(0, "cpll_125m", "cpll", CLK_IGNORE_UNUSED,
COMPOSITE_NOMUX(CPLL_125M, "cpll_125m", "cpll", CLK_IGNORE_UNUSED,
RK3568_CLKSEL_CON(80), 0, 5, DFLAGS,
RK3568_CLKGATE_CON(35), 10, GFLAGS),
COMPOSITE_NOMUX(0, "cpll_62p5", "cpll", CLK_IGNORE_UNUSED,
COMPOSITE_NOMUX(CPLL_62P5M, "cpll_62p5", "cpll", CLK_IGNORE_UNUSED,
RK3568_CLKSEL_CON(80), 8, 5, DFLAGS,
RK3568_CLKGATE_CON(35), 11, GFLAGS),
COMPOSITE_NOMUX(0, "cpll_50m", "cpll", CLK_IGNORE_UNUSED,
COMPOSITE_NOMUX(CPLL_50M, "cpll_50m", "cpll", CLK_IGNORE_UNUSED,
RK3568_CLKSEL_CON(81), 0, 5, DFLAGS,
RK3568_CLKGATE_CON(35), 12, GFLAGS),
COMPOSITE_NOMUX(0, "cpll_25m", "cpll", CLK_IGNORE_UNUSED,
COMPOSITE_NOMUX(CPLL_25M, "cpll_25m", "cpll", CLK_IGNORE_UNUSED,
RK3568_CLKSEL_CON(81), 8, 6, DFLAGS,
RK3568_CLKGATE_CON(35), 13, GFLAGS),
COMPOSITE_NOMUX(0, "cpll_100m", "cpll", CLK_IGNORE_UNUSED,
COMPOSITE_NOMUX(CPLL_100M, "cpll_100m", "cpll", CLK_IGNORE_UNUSED,
RK3568_CLKSEL_CON(82), 0, 5, DFLAGS,
RK3568_CLKGATE_CON(35), 14, GFLAGS),
COMPOSITE_NOMUX(0, "clk_osc0_div_750k", "xin24m", CLK_IGNORE_UNUSED,

8
include/dt-bindings/clock/rk3568-cru.h
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@ -471,6 +471,14 @@
#define CLK_I2S2_2CH 408
#define CLK_I2S3_2CH_TX 409
#define CLK_I2S3_2CH_RX 410
#define CPLL_500M 411
#define CPLL_250M 412
#define CPLL_125M 413
#define CPLL_62P5M 414
#define CPLL_50M 415
#define CPLL_25M 416
#define CPLL_100M 417
#define PCLK_CORE_PVTM 450
#define CLK_NR_CLKS (PCLK_CORE_PVTM + 1)