In addition, add log to check the result of enabling
TPI mode and initializing sii902x.
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
Change-Id: Id09c7e40d7706bd3cfcbb34b775ad5450d703fec
In order to avoid the invalid settings of display mode,
assign crtc atomic API mode_valid as vop_crtc_mode_valid.
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
Change-Id: I9abc1e93308d18bde55027163b4c01f32a8429a4
VP share same vop aclk, so only when have one active vp we can adjust aclk
rate in psr mode.
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: I6c3ea84f5ab8a33d7c48e3c49c4426344e644a8a
Fixed VOP_OUTPUT_IF_MIPI being turned off when switching resolution
Signed-off-by: Lei Chen <lei.chen@rock-chips.com>
Change-Id: I4f432a7d352578baa9351e2f859afd67b4ea0152
If FRAME_SEND_CLR_P was set, cec packets may be sent incomplete.
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Change-Id: Ic67518ea0c794fe6f997c87e45dedbfd6fb1fde3
This reverts commit e5cb1f01cd.
This function is not stable.
u-boot should also revert this commit:
0b728e80d451 ("drm/rockchip: vop2: disabled aclk of video port when unused")
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Change-Id: I8f3b1180c29a670433a12993f18b33716bef288f
* LPCM: BPCUV insertion by hw
* NLPCM/HBR: BPCUV insertion from stream
when BPCUV is from stream, we should not enable hw channel
status override which will replace CS with the hw one.
This fixes DD+ bitstream.
when BPCUV generated from HW, PBIT_FORCE_EN should be set
for Parity bit calculated internally.
This fixes no sound on some display devices.
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: I3aa0390d9dd7d217853394c74576749c36b84720
Increasing the sending frequency of infoframe improves
compatibility.
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Change-Id: I095495d8d6641e7263de6cf2d3359f645aac2d6b
It support skip reference fb at vop driver by
adding add skip-ref-fb at vop dt node.
Change-Id: I7a0a91d905ba4907f8f0720e1997e9ee9c5c65c7
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
When video port output image under 4K@60Hz(dclk less than 600MHz),
The dclk parent use hdmi0 phy pll or hdmi1 phy pll. In some cases
the hdmi0 phy pll or hdmi1 phy pll is not enough for all output
interface. For example, hdmi0 and hdmi0 connect to video port0 and
dp connect to video port1. In this case, It need the video port1
need use default dclk parent.
Signed-off-by: Zhang Yubing <yubing.zhang@rock-chips.com>
Change-Id: Icdf050bb1e7a9f36022f5dd196358136c1d9242c
If use savedefconfig to update defconfig, PM_DEVFREQ and DEVFREQ_THERMAL
will be removed, and dmc and opp_select also depend on PM_DEVFREQ,
enable them default.
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Change-Id: Ied5ac8e70fe195294df2752160ce6e56360f2db8
The internal PD of VOP2 on rk3588 take effect immediately
for power up and take effect by vsync for power down.
And the PD_CLUSTER0 is a parent PD of PD_CLUSTER1/2/3,
we may have this use case:
Cluster0 is attached to VP0 for HDMI output,
Cluster1 is attached to VP1 for MIPI DSI,
When we enable Cluster1 on VP1, we should enable PD_CLUSTER0 as
it is the parent PD, event though HDMI is plugout, VP1 is disabled,
the PD of Cluster0 should keep power on.
When system go to suspend:
(1) Power down PD of Cluster1 before VP1 standby(the power down is take
effect by vsync)
(2) Power down PD of Cluster0
But we have problem at step (2), Cluster0 is attached to VP0. bus VP0
is in standby mode, as it is never used or hdmi plugout. So there is
no vsync, the power down will never take effect.
According to IC designer: We must power down all internal PD of VOP
before we power down the global PD_VOP.
So we get this workaround:
We we found a VP is in standby mode when we want power down a PD is
attached to it, we release the VP from standby mode, than it will
run a default timing and generate vsync. Than we can power down the
PD by this vsync. After all this is done, we standby the VP at last.
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Change-Id: Ib9be8628f07d783c6bc3b7678c5eebfc63aabe1c
PD_ESMART is shared between Esmart1/2/3, Esmart0 has
no PD
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Change-Id: I5d11ec065f6226e130c93469b1757e4c4fe82067
To solve the problem that the flag bits of other interfaces are
overwritten after mipi is enabled in the co-display case
Signed-off-by: Lei Chen <lei.chen@rock-chips.com>
Change-Id: I9eeea20165cb43da38879456eb10f6253e60bccb
Both DP and MIPI get pixelclk from dclk_out as follow:
DP: dclkx_out(DIV)->dpn_pixelclk(MUX)
MIPI:dclkx_out(DIV)->mipi_clk_src(MUX)->mipi_pixelclk(DIV)
When a video port coonect DP, it will calculate dclk rate first,
then dclk out rate, finally dp pixelclk rate. When a video Port
connect to MIPI it will calculate mipi_pixelclk rate first.
The different calculation method may get different dclk rate or
divider ratio. When a video port connect to a DP and MIPI, DP
or MIPI may get the wrong pixel rate. So they need use the same
method to calculate pixelclk.
When A video port connect DP and MIPI, the mipi_pixelclk
is set first, and set the mipi_pixelclk divide value. Then
dp_pixelclk is set, which will modify dclk_out divide value
and cause the mipi_pixelclk change.
So when calculate the mipi_pixelclk, we calculate the dclk_out
first to avoid the mipi_pixelclk be modified when DP set
dp_pixelclk.
For uboot logo display, Depend on commit from u-boot(branch:
next-dev):
(I6037e12d8b6 drm/rockchip: vop2: change dclk calculate method
for mipi)
Signed-off-by: Zhang Yubing <yubing.zhang@rock-chips.com>
Change-Id: I53c3247ce1eb728dad7f480d86b65d3f922ab6d4
In order to get target read margin and scmi clk earlier,
and it will also be used in later submissions.
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Change-Id: I75bd79dc4963fa0dcc73d7c66a696e1cc0c177b7
In order to modify the logic, check whether the standby
function is supported by (*crtc_standby). And add the
universal function rockchip_drm_crtc_standby().
Replace vop2_standby() by rockchip_drm_crtc_standby() in
dsi2 driver.
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
Change-Id: I974780c441fe0e9a8a81f933b3070a727321b589
rv1126 does not support VOP2, so add config options to
reduce memory usage.
./ksize.sh drivers/gpu/drm/
before ksize: 487941 Bytes
after kszie: 380303 Bytes
save about: 107628 Bytes
In addition, improve the format of space and tab, and remove
extra "depends on DRM_ROCKCHIP".
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
Change-Id: I2b29a543a7e52e4e4b72112980e2c6dc6c6cce92
Add the reg shift of vop_pipe_bypass. Lcd lower pins(0~7)
and hsync/vsync/den belong to VCCIO6 which controlled
by venc_grf. And lcd higher pins(8~17) belong to VCCIO5
which depend on vo_grf.
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
Change-Id: If7eab4570cbba12f5ff38eafe826112a44ea90c9
In some condition, only 1 hdmi phy is enabled. The strategy
need judge which hdmi phy pll can be used.
Signed-off-by: Zhang Yubing <yubing.zhang@rock-chips.com>
Change-Id: Ia36d3f3cf010a0322e4d51a85f980012b5ee2231
