Commit Graph

37 Commits

Author SHA1 Message Date
Linus Torvalds
6589b3d76d soc: devicetree updates for 7.0
There are a handful of new SoCs this time, all of these are
 more or less related to chips in a wider family:
 
  - SpacemiT Key Stone K3 is an 8-core risc-v chip, and the first
    widely available RVA23 implementation. Note that this is
    entirely unrelated with the similarly named Texas Instruments
    K3 chip family that follwed the TI Keystone2 SoC.
 
  - The Realtek Kent family of SoCs contains three chip models
    rtd1501s, rtd1861b and rtd1920s, and is related to their earlier
    Set-top-box and NAS products such as rtd1619, but is built
    on newer Arm Cortex-A78 cores.
 
  - The Qualcomm Milos family includes the Snapdragon 7s Gen 3
    (SM7635) mobile phone SoC built around Armv9 Kryo cores of the Arm
    Cortex-A720 generation. This one is used in the Fairphone Gen 6
 
  - Qualcomm Kaanapali is a new SoC based around eight high
    performance Oryon CPU cores
 
  - NXP i.MX8QP and i.MX952 are both feature reduced versions of
    chips we already support, i.e. the i.MX8QM and i.MX952, with
    fewer CPU cores and I/O interfaces.
 
 As part of a cleanup, a number of SoC specific devicetree files got
 removed because they did not have a single board using the .dtsi files
 and they were never compile tested as a result: Samsung s3c6400,
 ST spear320s, ST stm32mp21xc/stm32mp23xc/stm32mp25xc, Renesas
 r8a779m0/r8a779m2/r8a779m4/r8a779m6/r8a779m7/r8a779m8/r8a779mb/
 r9a07g044c1/r9a07g044l1/r9a07g054l1/r9a09g047e37, and TI am3703/am3715.
 All of these could be restored easily if a new board gets merged.
 
 Broadcom/Cavium/Marvell ThunderX2 gets removed along with its only
 machine, as all remaining users are assumed to be using ACPI
 based firmware.
 
 A relatively small number of 43 boards get added this time, and
 almost all of them for arm64. Aside from the reference boards for
 the newly added SoCs, this includes:
 
  - Three server boards use 32-bit ASpeed BMCs
 
  - One more reference board for 32-bit Microchip LAN9668
 
  - 64-bit Arm single-board computers based on Amlogic s905y4,
    CIX sky1, NXP ls1028a/imx8mn/imx8mp/imx91/imx93/imx95,
    Qualcomm qcs6490/qrb2210 and Rockchip rk3568/rk3588s
 
  - Carrier board for SOMs using Intel agilex5, Marvell Armada 7020,
    NXP iMX8QP, Mediatek mt8370/mt8390 and rockchip rk3588
 
  - Two mobile phones using Snapdragon 845
 
  - A gaming device and a NAS box, both based on Rockchips rk356x
 
 On top of the newly added boards and SoCs, there is a lot of
 background activity going into cleanups, in particular towards
 getting a warning-free dtc build, and the usual work on adding
 support for more hardware on the previously added machines.
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Merge tag 'soc-dt-7.0' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

Pull SoC devicetree updates from Arnd Bergmann:
 "There are a handful of new SoCs this time, all of these are more or
  less related to chips in a wider family:

   - SpacemiT Key Stone K3 is an 8-core risc-v chip, and the first
     widely available RVA23 implementation. Note that this is entirely
     unrelated with the similarly named Texas Instruments K3 chip family
     that follwed the TI Keystone2 SoC.

   - The Realtek Kent family of SoCs contains three chip models
     rtd1501s, rtd1861b and rtd1920s, and is related to their earlier
     Set-top-box and NAS products such as rtd1619, but is built on newer
     Arm Cortex-A78 cores.

   - The Qualcomm Milos family includes the Snapdragon 7s Gen 3 (SM7635)
     mobile phone SoC built around Armv9 Kryo cores of the Arm
     Cortex-A720 generation. This one is used in the Fairphone Gen 6

   - Qualcomm Kaanapali is a new SoC based around eight high performance
     Oryon CPU cores

   - NXP i.MX8QP and i.MX952 are both feature reduced versions of chips
     we already support, i.e. the i.MX8QM and i.MX952, with fewer CPU
     cores and I/O interfaces.

  As part of a cleanup, a number of SoC specific devicetree files got
  removed because they did not have a single board using the .dtsi files
  and they were never compile tested as a result: Samsung s3c6400, ST
  spear320s, ST stm32mp21xc/stm32mp23xc/stm32mp25xc, Renesas
  r8a779m0/r8a779m2/r8a779m4/r8a779m6/r8a779m7/r8a779m8/r8a779mb/
  r9a07g044c1/r9a07g044l1/r9a07g054l1/r9a09g047e37, and TI
  am3703/am3715. All of these could be restored easily if a new board
  gets merged.

  Broadcom/Cavium/Marvell ThunderX2 gets removed along with its only
  machine, as all remaining users are assumed to be using ACPI based
  firmware.

  A relatively small number of 43 boards get added this time, and almost
  all of them for arm64. Aside from the reference boards for the newly
  added SoCs, this includes:

   - Three server boards use 32-bit ASpeed BMCs

   - One more reference board for 32-bit Microchip LAN9668

   - 64-bit Arm single-board computers based on Amlogic s905y4, CIX
     sky1, NXP ls1028a/imx8mn/imx8mp/imx91/imx93/imx95, Qualcomm
     qcs6490/qrb2210 and Rockchip rk3568/rk3588s

   - Carrier board for SOMs using Intel agilex5, Marvell Armada 7020,
     NXP iMX8QP, Mediatek mt8370/mt8390 and rockchip rk3588

   - Two mobile phones using Snapdragon 845

   - A gaming device and a NAS box, both based on Rockchips rk356x

  On top of the newly added boards and SoCs, there is a lot of
  background activity going into cleanups, in particular towards getting
  a warning-free dtc build, and the usual work on adding support for
  more hardware on the previously added machines"

* tag 'soc-dt-7.0' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (757 commits)
  dt-bindings: intel: Add Agilex eMMC support
  arm64: dts: socfpga: agilex: add emmc support
  arm64: dts: intel: agilex5: Add simple-bus node on top of dma controller node
  ARM: dts: socfpga: fix dtbs_check warning for fpga-region
  ARM: dts: socfpga: add #address-cells and #size-cells for sram node
  dt-bindings: altera: document syscon as fallback for sys-mgr
  arm64: dts: altera: Use lowercase hex
  dt-bindings: arm: altera: combine Intel's SoCFPGA into altera.yaml
  arm64: dts: socfpga: agilex5: Add IOMMUS property for ethernet nodes
  arm64: dts: socfpga: agilex5: add support for modular board
  dt-bindings: intel: Add Agilex5 SoCFPGA modular board
  arm64: dts: socfpga: agilex5: Add dma-coherent property
  arm64: dts: realtek: Add Kent SoC and EVB device trees
  dt-bindings: arm: realtek: Add Kent Soc family compatibles
  ARM: dts: samsung: Drop s3c6400.dtsi
  ARM: dts: nuvoton: Minor whitespace cleanup
  MAINTAINERS: Add Falcon DB
  arm64: dts: a7k: add COM Express boards
  ARM: dts: microchip: Drop usb_a9g20-dab-mmx.dtsi
  arm64: dts: rockchip: Fix rk3588 PCIe range mappings
  ...
2026-02-10 21:11:08 -08:00
Dinh Nguyen
e0f489a52a ARM: dts: socfpga: fix dtbs_check warning for fpga-region
soc (simple-bus): base_fpga_region: 'ranges' is a required property
	from schema $id: http://devicetree.org/schemas/simple-bus.yaml

base_fpga_region (fpga-region): $nodename:0: 'base_fpga_region' does not match
'^fpga-region(@.*|-([0-9]|[1-9][0-9]+))?$'
	from schema $id: http://devicetree.org/schemas/fpga/fpga-region.yaml

Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2026-01-30 09:27:12 -06:00
Dinh Nguyen
6ba5f9b424 ARM: dts: socfpga: add #address-cells and #size-cells for sram node
Add #address-cells and #size-cells for sram node to fix below DTB_CHECK
warnings:

socfpga_arria5_socdk.dtb: sram@ffff0000 (mmio-sram): '#size-cells' is a
required property from schema $id: http://devicetree.org/schemas/sram/sram.yaml

Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2026-01-30 09:27:12 -06:00
Linus Walleij
ececfba255 ARM: dts: ixp4xx: Fix up Actiontec MI424WR DTS files
The KS8995 switch was unconditionally wired to EthC (eth1)
on both MI424WR variants, this is wrong: the D revision has
the switch connected to EthB (eth0) so pull this assingment
out of the generic MI424WR DTSI file and make it a property
of the respective variants instead.

Signed-off-by: Linus Walleij <linusw@kernel.org>
Link: https://patch.msgid.link/20251211-ixp4xx-actiontec-dts-fix-v1-1-97af8e79d474@kernel.org
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2025-12-15 21:15:36 +01:00
Lothar Rubusch
91b97ca3d4 ARM: dts: socfpga: add Enclustra SoM dts files
Add the approach to set up a combination of Enclustra's SoM on a carrier
board and corresponding boot-mode as single device-tree target.

Signed-off-by: Lothar Rubusch <l.rubusch@gmail.com>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2025-10-20 11:26:34 -05:00
Lothar Rubusch
adacc09225 ARM: dts: socfpga: removal of generic PE1 dts
Remove the older socfpga_arria10_mercury_pe1.dts, since it is duplicate,
the hardware is covered by the combination of Enclustra's .dtsi files.

The older .dts was limited to only the case of having an Enclustra
Mercury+ AA1 on a Mercury+ PE1 base board, booting from sdmmc. This
functionality is provided also by the generic Enclustra dtsi and dts
files, in particular socfpga_arria10_mercury_aa1_pe1_sdmmc.dts. Since
both .dts files cover the same, the older one is to e replaced in
favor of the more modularized approach.

Signed-off-by: Lothar Rubusch <l.rubusch@gmail.com>
Acked-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2025-10-20 11:25:43 -05:00
Lothar Rubusch
26a0157f4c ARM: dts: socfpga: add Mercury AA1 variants
Introduce support for Enclustra's Mercury+ AA1 SoM, based on Intel
Arria10. This is a flexible approach to allow for combining SoM
with carrier board .dtsi and boot-mode .dtsi in a device-tree file.

Signed-off-by: Andreas Buerkler <andreas.buerkler@enclustra.com>
Signed-off-by: Lothar Rubusch <l.rubusch@gmail.com>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2025-10-20 11:24:03 -05:00
Lothar Rubusch
9fbc22b3c5 ARM: dts: socfpga: add Enclustra Mercury+ SA2
Introduce Enclustra's Mercury+ SA2 SoM based on Intel Cyclone5
technology as a .dtsi file.

Signed-off-by: Andreas Buerkler <andreas.buerkler@enclustra.com>
Signed-off-by: Lothar Rubusch <l.rubusch@gmail.com>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2025-10-20 11:23:29 -05:00
Lothar Rubusch
66243445fd ARM: dts: socfpga: add Enclustra Mercury SA1
Introduce support for Enclustra's Mercury SA1 SoM based on Intel Cyclone5
technology as a .dtsi file.

Signed-off-by: Andreas Buerkler <andreas.buerkler@enclustra.com>
Signed-off-by: Lothar Rubusch <l.rubusch@gmail.com>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2025-10-20 11:22:36 -05:00
Lothar Rubusch
2d7ef02f1e ARM: dts: socfpga: add Enclustra base-board dtsi
Add generic Enclustra base-board support for the Mercury+ PE1, the
Mercury+ PE3 and the Mercury+ ST1 board. The carrier boards can be
freely combined with the SoMs Mercury+ AA1, Mercury SA1 and
Mercury+ SA2.

Signed-off-by: Andreas Buerkler <andreas.buerkler@enclustra.com>
Signed-off-by: Lothar Rubusch <l.rubusch@gmail.com>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2025-10-20 11:16:49 -05:00
Lothar Rubusch
fad0dcaf37 ARM: dts: socfpga: add Enclustra boot-mode dtsi
Add generic boot-mode support to Enclustra Arria10 and Cyclone5 boards.
Some Enclustra carrier boards need hardware adjustments specific to the
selected boot-mode.

Enclustra's Arria10 SoMs allow for booting from different media. By
muxing certain IO pins, the media can be selected. This muxing can be
done by gpios at runtime e.g. when flashing QSPI from off the
bootloader. But also to have statically certain boot media available,
certain adjustments to the DT are needed:
- SD: QSPI must be disabled
- eMMC: QSPI must be disabled, bus width can be doubled to 8 byte
- QSPI: any mmc is disabled, QSPI then defaults to be enabled

The boot media must be accessible to the bootloader, e.g. to load a
bitstream file, but also to the system to mount the rootfs and to use
the specific performance.

Signed-off-by: Andreas Buerkler <andreas.buerkler@enclustra.com>
Signed-off-by: Lothar Rubusch <l.rubusch@gmail.com>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2025-10-20 11:15:25 -05:00
Linus Torvalds
0f048c878e soc: dt changes for 6.18
There are five sets of new SoCs that get added in existing families,
 all of them being either upgrades or cut-down versions of the older chips:
 
  - Apple M2 Pro, M2 Max and M2 Ultra, used in the 2022/2023 generation of
    high-end workstations and laptops from Apple.  Linux has been working
    on these for a while but stil requires patches.
 
  - Axis Artpec8 is an Armv8 chip based on Samsung Exynos design,
    unlike the earlier Armv7 Artpec6 from the same company that
    was part of a separate family of chips.
 
  - NXP i.MX91 is a cut-down version of i.MX93, using only a single
    Cortex-A55 core.
 
  - Qualcomm Lemans Auto is a variant of the Lemans SoC that was
    originally merged under the sa8775p name, the differences
    being mostly the firmware configuration of the platform.
 
  - Four new Renesas SoCs RZ/T2H (r9a09g077m44), RZ/N2H (r9a09g087m44),
    RZ/T2H (r9a09g077), and RZ/N2H (r9a09g087) are all industrial bedded
    SoCs based on Cortex-A55 cores
 
 In total, there are 65 new machines, including:
 
  - Industrial embedded system and single-board computers based on NXP,
    Allwinner, TI, Rockchips, Marvell, Xilinx Spacemit, Starfive chips.
 
  - Reference boards for the newly added Renesas, Qualcomm, NXP and Axis
    ARMv8 chips as well as Microchip's MPFS RISC-V SoC
 
  - Laptops and Workstations using Apple M2 and Qualcomm Snapdragon
    X1 chips.
 
  - Several Samsung phones using Qualcomm Snapdragon chips
 
  - Set-top boxes based on Allwinner H313
 
  - Five BMC boards using 32-bit ASpeed SoCs
 
  - Three network routers using IXP4xx (ARMv5!) and Broadcom bcm4708
    (ARMv7) SoCs
 
 Two machines get phased out because they were available only in small
 quantities but never made it into products: one STi407 based reference
 board, and a Snapdragon 845 based Chromebook.
 
 Aside from the newly added machines, a lot of work went into
 improving hardware support on the existing machines and cleaning
 up contents for validation.
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Merge tag 'soc-dt-6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

Pull SoC dt updates from Arnd Bergmann:
 "There are five sets of new SoCs that get added in existing families,
  all of them being either upgrades or cut-down versions of the older
  chips:

   - Apple M2 Pro, M2 Max and M2 Ultra, used in the 2022/2023 generation
     of high-end workstations and laptops from Apple. Linux has been
     working on these for a while but stil requires patches.

   - Axis Artpec8 is an Armv8 chip based on Samsung Exynos design,
     unlike the earlier Armv7 Artpec6 from the same company that was
     part of a separate family of chips.

   - NXP i.MX91 is a cut-down version of i.MX93, using only a single
     Cortex-A55 core.

   - Qualcomm Lemans Auto is a variant of the Lemans SoC that was
     originally merged under the sa8775p name, the differences being
     mostly the firmware configuration of the platform.

   - Four new Renesas SoCs RZ/T2H (r9a09g077m44), RZ/N2H (r9a09g087m44),
     RZ/T2H (r9a09g077), and RZ/N2H (r9a09g087) are all industrial
     bedded SoCs based on Cortex-A55 cores

  In total, there are 65 new machines, including:

   - Industrial embedded system and single-board computers based on NXP,
     Allwinner, TI, Rockchips, Marvell, Xilinx Spacemit, Starfive chips.

   - Reference boards for the newly added Renesas, Qualcomm, NXP and
     Axis ARMv8 chips as well as Microchip's MPFS RISC-V SoC

   - Laptops and Workstations using Apple M2 and Qualcomm Snapdragon X1
     chips.

   - Several Samsung phones using Qualcomm Snapdragon chips

   - Set-top boxes based on Allwinner H313

   - Five BMC boards using 32-bit ASpeed SoCs

   - Three network routers using IXP4xx (ARMv5!) and Broadcom bcm4708
     (ARMv7) SoCs

  Two machines get phased out because they were available only in small
  quantities but never made it into products: one STi407 based reference
  board, and a Snapdragon 845 based Chromebook.

  Aside from the newly added machines, a lot of work went into improving
  hardware support on the existing machines and cleaning up contents for
  validation"

* tag 'soc-dt-6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (931 commits)
  arm64: dts: apm-shadowcat: Drop "apm,xgene2-pcie" compatible
  arm64: dts: apm-shadowcat: Move slimpro nodes out of "simple-bus" node
  ARM: dts: microchip: sam9x7: Add qspi controller
  arm64: dts: qcom: Add MST pixel streams for displayport
  arm64: dts: qcom: sm6350: correct DP compatibility strings
  arm64: dts: qcom: monaco-evk: Enable Adreno 623 GPU
  arm64: dts: qcom: qcs8300-ride: Enable Adreno 623 GPU
  arm64: dts: qcom: qcs8300: Add gpu and gmu nodes
  arm64: dts: allwinner: h313: Add Amediatech X96Q
  dt-bindings: arm: sunxi: Add Amediatech X96Q
  arm64: dts: apple: t8015: Add SPMI node
  arm64: dts: apple: t8012: Add SPMI node
  arm64: dts: apple: Add J180d (Mac Pro, M2 Ultra, 2023) device tree
  arm64: dts: rockchip: Add devicetree for the ROC-RK3588-RT
  dt-bindings: arm: rockchip: Add Firefly ROC-RK3588-RT
  arm64: dts: rockchip: update pinctrl names for Radxa E52C
  arm64: dts: rockchip: remove vcc_3v3_pmu regulator for Radxa E52C
  arm64: dts: apple: Add J474s, J475c and J475d device trees
  arm64: dts: apple: Add J414 and J416 Macbook Pro device trees
  arm64: dts: apple: Add initial t6020/t6021/t6022 DTs
  ...
2025-10-01 17:19:38 -07:00
Nobuhiro Iwamatsu
ea9da67e2a ARM: dts: socfpga: sodia: Fix mdio bus probe and PHY address
On SoCFPGA/Sodia board, mdio bus cannot be probed, so the PHY cannot be
found and the network device does not work.

```
stmmaceth ff702000.ethernet eth0: __stmmac_open: Cannot attach to PHY (error: -19)
```

To probe the mdio bus, add "snps,dwmac-mdio" as compatible string of the
mdio bus. Also the PHY address connected to this board is 4. Therefore,
change to 4.

Cc: stable@vger.kernel.org # 6.3+
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2025-09-07 07:26:29 -05:00
Linus Walleij
85ac6b8069 ARM: dts: Add ixp4xx Actiontec MI424WR device trees
The Actiontex MI424WR is a pretty widespread home router, made
in many different revisions.

Revisions A, C and D are based on IXP42x. We add a device tree
for the A/C variant and one for the D variant as these differ in
the location of the WAN PHY on the MDIO bus, and the ethernet
interfaces for the WAN PHY and the DSA switch are switched around.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/20250822-ixp4xx-mi424wr-dts-v2-3-cc804884474d@linaro.org
2025-08-29 11:18:15 +02:00
Linus Walleij
c9cc6b6a7d ARM: dts: Fix up wrv54g device tree
Fix up the KS8995 switch and PHYs the way that is most likely:

- Phy 1-4 is certainly the PHYs of the KS8995 (mask 0x1e in
  the outoftree code masks PHYs 1,2,3,4).
- Phy 5 is the MII-P5 separate WAN phy of the KS8995 directly
  connected to EthC.
- The EthB MII is probably connected as CPU interface to the
  KS8995.

Properly integrate the KS8995 switch using the new bindings.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Link: https://patch.msgid.link/20250625-ks8995-dsa-bindings-v2-2-ce71dce9be0b@linaro.org
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2025-06-27 15:14:53 -07:00
Arnd Bergmann
0d57ac1f92 SoCFPGA DTS updates for v6.15
- Updates to dt-bindings
         - Document Agilex5 NAND daughter board
         - Convert Stratix10 FPGA Manager to json-schema
         - Convert Stratix10 Service Layer to json-schema
         - Add document for Terasic's DE10-nano board
 - Add support for Agilex5 NAND daughter board
 - Add basic support for Terasic's DE10-nano board
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Merge tag 'socfpga_dts_updates_for_v6.15' of https://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux into soc/dt

SoCFPGA DTS updates for v6.15
- Updates to dt-bindings
        - Document Agilex5 NAND daughter board
        - Convert Stratix10 FPGA Manager to json-schema
        - Convert Stratix10 Service Layer to json-schema
        - Add document for Terasic's DE10-nano board
- Add support for Agilex5 NAND daughter board
- Add basic support for Terasic's DE10-nano board

* tag 'socfpga_dts_updates_for_v6.15' of https://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux:
  arm64: dts: socfpga: agilex: Add dma channel id for spi
  arm64: dts: socfpga: agilex5: add led and memory nodes
  arm64: dts: intel: socfpga_agilex: add frequencies to internal oscillators
  ARM: dts: socfpga: Add basic support for Terrasic's de10-nano
  dt-bindings: altera: Add compatible for Terasic's DE10-nano
  arm64: dts: socfpga: agilex5: add qspi flash node
  dt-bindings: firmware: stratix10: Convert to json-schema
  dt-bindings: fpga: stratix10: Convert to json-schema
  arm64: dts: socfpga: agilex5: fix gpio0 address
  arm64: dts: socfpga: agilex5: add NAND daughter board
  dt-bindings: intel: document Agilex5 NAND daughter board

Link: https://lore.kernel.org/r/20250326121152.1739873-1-dinguyen@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-05-09 22:34:37 +02:00
Uwe Kleine-König
144616a808 ARM: dts: socfpga: Add basic support for Terrasic's de10-nano
This dts is enough to make the board boot to Linux with the rootfs on
a micro SD card.

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@baylibre.com>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2025-03-26 06:47:04 -05:00
Linus Walleij
3dceb794c0 ARM: dts: ixp4xx: Add Netgear WG302 v1 GPIOs
This adds GPIO LED indicators, the reset GPIO RESET
button on the Netgear WG302 v1 to the device tree.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/20250210-ixp4xx-dts-v1-3-6b752d745e04@linaro.org
2025-02-12 23:56:31 +01:00
Linus Walleij
824974af79 ARM: dts: ixp4xx: Fix up PCI on WG302
Looking at the board file for WG302 v2 was not a good idea
because the GPIO IRQ for slot 2 differs, and v1 uses GPIO
10 instead of GPIO 9. Fix it up.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/20250210-ixp4xx-dts-v1-2-6b752d745e04@linaro.org
2025-02-12 23:56:31 +01:00
Linus Walleij
9c1b4ba8c6 ARM: dts: Properly assign NPE to ethA
The way to assign NPE (network processing engines) shifted
during device tree design and an erroneous entry was left
behind in a disabled node. Fix it up.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/20250210-ixp4xx-dts-v1-1-6b752d745e04@linaro.org
2025-02-12 23:56:31 +01:00
Arnd Bergmann
e736f2ad32 SoCFPGA DTS updates for v6.14
- Remove unused and undocumented property "snps,max-mtu"
 - Add gpio and spi node for Agilex5
 - Add VGIC maintenance interrupt for Agilex
 - Use correct reset name of "stmmaceth-ocp" instead of "ahb"
 - Drop unused #address-cells/#size-cells in the cyclone5-mcvevk
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Merge tag 'socfpga_dts_updates_v6.14' of https://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux into soc/dt

SoCFPGA DTS updates for v6.14
- Remove unused and undocumented property "snps,max-mtu"
- Add gpio and spi node for Agilex5
- Add VGIC maintenance interrupt for Agilex
- Use correct reset name of "stmmaceth-ocp" instead of "ahb"
- Drop unused #address-cells/#size-cells in the cyclone5-mcvevk

* tag 'socfpga_dts_updates_v6.14' of https://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux:
  arm64: dts: altera: Remove unused and undocumented "snps,max-mtu" property
  arm64: dts: socfpga: agilex5: Add gpio0 node and spi dma handshake id
  arm64: dts: socfpga: agilex: Add VGIC maintenance interrupt
  arm: dts: socfpga: use reset-name "stmmaceth-ocp" instead of "ahb"
  ARM: dts: socfpga_cyclone5_mcvevk: Drop unused #address-cells/#size-cells

Link: https://lore.kernel.org/r/20250103023012.1268627-1-dinguyen@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-01-16 14:39:11 +01:00
Conor Dooley
ba9dfa76eb ARM: dts: socfpga: remove non-existent DAC from CycloneV devkit
There is no Rohm DAC on the CycloneV devkit according to the online
documentation for it that I could find, and it definitely does not have
a dh2228fv as this device does not actually exist! Remove the DAC node
from the devicetree as it is not acceptable to pretend to have a device
on a board in order to bind the spidev driver in Linux.

Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20240717-partake-antivirus-3347e415fb7d@spud
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-12-29 11:02:50 +01:00
Mamta Shukla
62a40a0d56 arm: dts: socfpga: use reset-name "stmmaceth-ocp" instead of "ahb"
The ahb reset is deasserted in probe before first register access, while the
stmmacheth-ocp reset needs to be asserted every time before changing the phy
mode in Arria10[1].

Changed in Upstream to "ahb"(331085a423  arm64: dts: socfpga: change the
reset-name of "stmmaceth-ocp" to "ahb" ).This change was intended for arm64
socfpga and it is not applicable to Arria10.

Further with STMMAC-SELFTEST Driver enabled, ethtool test also FAILS.
$ ethtool -t eth0
[  322.946709] socfpga-dwmac ff800000.ethernet eth0: entered promiscuous mode
[  323.374558] socfpga-dwmac ff800000.ethernet eth0: left promiscuous mode
The test result is FAIL
The test extra info:
 1. MAC Loopback                 0
 2. PHY Loopback                 -110
 3. MMC Counters                 -110
 4. EEE                          -95
 5. Hash Filter MC               0
 6. Perfect Filter UC            -110
 7. MC Filter                    -110
 8. UC Filter                    0
 9. Flow Control                 -110
10. RSS                          -95
11. VLAN Filtering               -95
12. VLAN Filtering (perf)        -95
13. Double VLAN Filter           -95
14. Double VLAN Filter (perf)    -95
15. Flexible RX Parser           -95
16. SA Insertion (desc)          -95
17. SA Replacement (desc)        -95
18. SA Insertion (reg)           -95
19. SA Replacement (reg)         -95
20. VLAN TX Insertion            -95
21. SVLAN TX Insertion           -95
22. L3 DA Filtering              -95
23. L3 SA Filtering              -95
24. L4 DA TCP Filtering          -95
25. L4 SA TCP Filtering          -95
26. L4 DA UDP Filtering          -95
27. L4 SA UDP Filtering          -95
28. ARP Offload                  -95
29. Jumbo Frame                  -110
30. Multichannel Jumbo           -95
31. Split Header                 -95
32. TBS (ETF Scheduler)          -95

[  324.881327] socfpga-dwmac ff800000.ethernet eth0: Link is Down
[  327.995360] socfpga-dwmac ff800000.ethernet eth0: Link is Up - 1Gbps/Full - flow control rx/tx

Link:[1] https://www.intel.com/content/www/us/en/docs/programmable/683711/21-2/functional-description-of-the-emac.html
Fixes: 331085a423 ("arm64: dts: socfpga: change the reset-name of "stmmaceth-ocp" to "ahb")
Signed-off-by: Mamta Shukla <mamta.shukla@leica-geosystems.com>
Tested-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Reviewed-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2024-12-16 18:18:35 -06:00
Uwe Kleine-König
d5f9e83ca6 ARM: dts: socfpga_cyclone5_mcvevk: Drop unused #address-cells/#size-cells
The properties #address-cells and #size-cells are only useful if there
is a ranges property or child nodes with "reg" properties.

This fixes a W=1 warning:

	arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mcvevk.dts:51.22-72.4: Warning (avoid_unnecessary_addr_size): /soc/i2c@ffc04000/stmpe811@41: unnecessary #address-cells/#size-cells without "ranges", "dma-ranges" or child "reg" property

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@baylibre.com>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2024-12-16 18:18:35 -06:00
Rob Herring (Arm)
44dae95e61 ARM: dts: socfpga: Fix at24 EEPROM node names
at24.yaml defines the node name for at24 EEPROMs as 'eeprom'.

Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2024-10-01 21:35:49 -05:00
Rob Herring
ef1e32cb63
ARM: dts: Fix undocumented LM75 compatible nodes
"lm75" without any vendor is undocumented. It works with the Linux
kernel since the I2C subsystem will do matches of the compatible string
without a vendor prefix to the i2c_device_id and/or driver name.

Mostly replace "lm75" with "national,lm75" as that's the original part
vendor and the compatible which matches what "lm75" matched with. In a
couple of cases the node name or compatible gives a clue to the actual
part and vendor and a more specific compatible can be used. In these
cases, it does change the variant the kernel picks.

"nct75" is an OnSemi part which is compatible with TI TMP75C based on
a comparison of the OnSemi NCT75 datasheet and configuration the Linux
driver uses. Adding an OnSemi compatible would be an ABI change.

"nxp,lm75" is most likely an NXP part. Alexander Stein says the i.MX53
boards are a NXP LM75A as well. NXP makes a LM75A and LM75B. Both are
11-bit resolution and 100ms sample time. The "national,lm75a" is
9-bit, so "national,lm75b" is the closest match for both NXP variants.

While we're here, fix the node names to use the generic name
"temperature-sensor".

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Kevin Hilman <khilman@baylibre.com> # am335x-nano.dts
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Reviewed-by: Alexander Stein <alexander.stein@ew.tq-group.com> # imx53-mba53.dts, imx53-tqma53.dtsi
Link: https://lore.kernel.org/r/20240816164717.1585629-1-robh@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2024-09-05 14:37:43 +00:00
Linus Walleij
8b5d415c4f
ARM: dts: ixp4xx: nslu2: beeper uses PWM
The beeper in the NSLU2 is just a GPIO connected to a
speaker, so we need to use PWM on the GPIO to get any kind
of sound out.

Tested with some random beeps by enabling INPUT_EVDEV and
running beep.c with e.g. beep 400 for a 400 Hz tone.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/20240627-ixp4xx-dts-v1-1-cdbbe1150873@linaro.org
Link: https://lore.kernel.org/r/20240703-ixp4xx-dts-v1-1-e5149da36f6e@linaro.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2024-07-08 16:31:25 +02:00
Rob Herring
f02b0f0dc2
arm: dts: Fix dtc interrupt_map warnings
The dtc interrupt_map warning is off because its dependency,
interrupt_provider, is off by default. Fix all the warnings so it can be
enabled.

Signed-off-by: Rob Herring <robh@kernel.org>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20240213-arm-dt-cleanups-v1-4-f2dee1292525@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2024-02-20 21:47:41 +01:00
Linus Walleij
18a1ee9d71 ARM: dts: usr8200: Fix phy registers
The MV88E6060 switch has internal PHY registers at MDIO
addresses 0x00..0x04. Tie each port to the corresponding
PHY.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20231020-ixp4xx-usr8200-dtsfix-v1-1-3a8591dea259@linaro.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2024-01-11 16:21:02 +01:00
Krzysztof Kozlowski
575c726ce8 ARM: dts: socfpga: align NAND controller name with bindings
Bindings expect NAND controller node name to match certain patterns:

  socfpga_arria10_socdk_nand.dtb: nand@ffb90000: $nodename:0: 'nand@ffb90000' does not match '^nand-controller(@.*)?'

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2024-01-03 18:10:39 -06:00
Krzysztof Kozlowski
a5db395a1c ARM: dts: socfpga: drop unsupported cdns,page-size and cdns,block-size
cdns,page-size and cdns,block-size are neither documented nor used by
Linux, so remove them to fix dtbs_check warnings like:

  socfpga_arria5_socdk.dtb: flash@0: Unevaluated properties are not allowed ('cdns,block-size', 'cdns,page-size' were unexpected)

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2024-01-03 18:10:39 -06:00
Linus Walleij
d3c849020b ARM: dts: ixp4xx: Use right restart keycode
The "reset" key on a few IXP4xx routers were sending KEY_ESC
but what we want to send is KEY_RESTART which will make
OpenWrt and similar userspace do a controlled reboot.

Link: https://lore.kernel.org/r/20230908-ixp4xx-dts-v1-2-98d36264ed6d@linaro.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-10-09 22:29:42 +02:00
Linus Walleij
2ffdee77f0 ARM: dts: ixp4xx-nslu2: Enable write on flash
To upgrade the firmware and similar, the flash needs write
access.

Link: https://lore.kernel.org/r/20230908-ixp4xx-dts-v1-1-98d36264ed6d@linaro.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-10-09 22:29:36 +02:00
Linus Walleij
f71d371ae5 ARM: dts: ixp4xx: Add USRobotics USR8200 device tree
This is a USRobotics NAS/Firewall/router that has been supported
by OpenWrt in the past. It had dedicated users so let's get it
properly supported.

Some debugging and fixing was provided by Howard Harte.

Link: https://lore.kernel.org/r/20231007-ixp4xx-usr8200-v1-1-aded3d6ff6f1@linaro.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-10-09 22:26:50 +02:00
Linus Walleij
5b1d4d99d1 ARM: dts: Use only the Linksys compatible for now
The Gemtek users can just use the Linksys device tree,
triplet compatible is overdoing it.

Link: https://lore.kernel.org/r/20231007-ixp4xx-usr8200-v3-3-ec46edd1ff0e@linaro.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-10-09 22:25:40 +02:00
Dinh Nguyen
331085a423 arm64: dts: socfpga: change the reset-name of "stmmaceth-ocp" to "ahb"
The "stmmaceth-ocp" reset line on the SoCFPGA stmmac ethernet driver is
the same as the "ahb" reset on a standard stmmac ethernet.

commit ("843f603762a5 dt-bindings: net: snps,dwmac: Add 'ahb'
reset/reset-name") documented the second reset signal as 'ahb' instead
of 'stmmaceth-ocp'. Change the reset-names of the SoCFPGA DWMAC driver to
'ahb'. In order not to break ABI, we will keep support in thedwmac-socfpga
driver to still make use of "stmmaceth-ocp".

This also fixes the dtbs_check warning:
ethernet@ff802000: reset-names:1: 'ahb' was expected

Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
---
v2: update commit message to further describe the reason for the change
2023-07-17 16:16:36 -05:00
Rob Herring
724ba67515 ARM: dts: Move .dts files to vendor sub-directories
The arm dts directory has grown to 1559 boards which makes it a bit
unwieldy to maintain and use. Past attempts stalled out due to plans to
move .dts files out of the kernel tree. Doing that is no longer planned
(any time soon at least), so let's go ahead and group .dts files by
vendors. This move aligns arm with arm64 .dts file structure.

There's no change to dtbs_install as the flat structure is maintained on
install.

The naming of vendor directories is roughly in this order of preference:
- Matching original and current SoC vendor prefix/name (e.g. ti, qcom)
- Current vendor prefix/name if still actively sold (SoCs which have
  been aquired) (e.g. nxp/imx)
- Existing platform name for older platforms not sold/maintained by any
  company (e.g. gemini, nspire)

The whole move was scripted with the exception of MAINTAINERS and a few
makefile fixups.

Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Acked-by: Michal Simek <michal.simek@amd.com> #Xilinx
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Neil Armstrong <neil.armstrong@linaro.org>
Acked-by: Paul Barker <paul.barker@sancloud.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Acked-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Acked-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Wei Xu <xuwei5@hisilicon.com> #hisilicon
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Nick Hawkins <nick.hawkins@hpe.com>
Acked-by: Baruch Siach <baruch@tkos.co.il>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Acked-by: Peter Rosin <peda@axentia.se>
Acked-by: Jesper Nilsson <jesper.nilsson@axis.com>
Acked-by: Sudeep Holla <sudeep.holla@arm.com>
Acked-by: Florian Fainelli <f.fainelli@gmail.com> #broadcom
Acked-by: Manivannan Sadhasivam <mani@kernel.org>
Reviewed-by: Jisheng Zhang <jszhang@kernel.org>
Acked-by: Patrice Chotard <patrice.chotard@foss.st.com>
Acked-by: Romain Perier <romain.perier@gmail.com>
Acked-by: Alexandre TORGUE <alexandre.torgue@st.com>
Acked-by: Shawn Guo <shawnguo@kernel.org>
Acked-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Acked-by: Enric Balletbo i Serra <eballetbo@gmail.com>
Signed-off-by: Rob Herring <robh@kernel.org>
2023-06-21 11:39:50 -06:00