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1068 Commits
| Author | SHA1 | Message | Date | |
|---|---|---|---|---|
Linus Torvalds
|
502d45774a |
Mostly the usual clk driver updates and new SoC additions plus non-critical
data fixes for things that weren't used yet. One thing that's new here in the core is SSC spread spectrum support (SSC) in the clk provider API. The idea is that DT authors will configure SSC for certain clks and they'll be configured at clk provider registration time or when a consumer device is probed, similar to how we handle assigned clk rates or parents. On the clk driver side we have Qualcomm adding almost half the diff because they add support for 4 different SoCs and then a long tail of other SoCs like Mediatek, Renesas, Rockchip, SpaceMiT, etc. add more SoC support this time around. Luckily it's mostly clk data for these new SoCs because the actual clk_ops are already there. Beyond the new drivers we get all the little fixups for more compilation coverage or usage of more modern APIs. That all looks normal. Finally, I kinda buried the lead, I'm bringing on Brian and Jerome to help out with maintaining the clk subsystem. The current working model is already semi-distributed in that silicon vendors typically take care of their drivers and send me pull requests but I'm becoming a bottleneck for new drivers and core framework review because this has become a 100% volunteer effort on my part. Mike is stepping down after all these years (thanks Mike!) and that jump started the conversation around finding co-maintainers. Brian and Jerome have graciously offered to help me with the work load, meaning in the future they'll be sending pull requests and committing directly to the clk.git tree. They've both been around on the list for a while, I've met them both in person, and they've been making changes to the core clk framework along with helping review patches so I'm pretty confident this will work well. Core: - devm_clk_bulk_get_enable() consumer API - devm_clk_hw_register_composite_pdata() provider API - Spread Spectrum Clock (SSC) support via DT bindings and provider APIs - Divider clk rounding improved (and tested) New Drivers: - Cix Sky1 audio subsystem (AUDSS) - UltraRISC DP1000 - MediaTek MT8173 MFG_TOP - Si549 - Aspeed AST2700 PECI - Airoha EN7523 PCIe - Rockchip RV1106 - Mobileye EyeQ7H - Qualcomm Maili GCC, TCSR, RPMh, and video clks - Qualcomm Shikra GCC, RPM, GPU, display, and audio clks - Qualcomm Nord display and graphics clks - Qualcomm Glymur camera and EVA clks - Qualcomm Hawi video clks - Amlogic A9 AO and peripheral clks - Renesas R-Car X5H (R8A78000) CPG -----BEGIN PGP SIGNATURE----- iQJIBAABCAAyFiEE9L57QeeUxqYDyoaDrQKIl8bklSUFAmqPGK4UHHN3Ym95ZEBj aHJvbWl1bS5vcmcACgkQrQKIl8bklSXB+g/+O8McZyE7kqNPiz8nQNQq9YwzO9uB /5LkNUUvvxhzJ9YEcXx8HCkmUcAks+kMCHzrZ/gxAN6BQGv9qrTChZZD2ZmD8e50 nj3IxyvN51PwRk5ley1PEsUILrnOqRpY6g83arnFppTP2aU/NxFFGjc5u+5qlIT4 f0xj2sJ0H96Ykw+brSJgEj9MXJHMEKerEqBmaDd0boHavDV3YkT/HxRrjy3WH/sE FBAdq6sOAEX3qnNwsF9debrfg1nKJGH2U8ecb1JThlAufn8yHvC+mxr3P4USxdov xGhDkvKbS+9nkbxeL1LOhnoReOWqNBGQg9qmadQKTrPEu/BAOb8nG62xpucIgLSl 6X3AACRzEE8u8Thaboz+cvQluQfOo667xz5X+bpTsQjfQuq4Yh0F4pO6pLmLd+LT NdOzbQctglbpwHbXIxXQftg+Fnk1bgERILW64DU9mUqXzSJJG9uzv+Ne5R0TTXJp TMRTp/o8o4Fclr1WB73wES523xpf7VltPfUw5XL9UN2xCCY5TI2bpHQwgfmkz/6J nHmxNBBK19qlNFzDovN1gfgwn9XVDLmT7YVSw0El24kINHs7rYXuGc++OX+LmUb3 r19QxJXU8ESV89ZGJYhnaSOKrCj1d4W49AkVqovvJXXYxxlFTab1ox8xKnhUlxGH SGDC+kZah2zUl7A= =iYa8 -----END PGP SIGNATURE----- Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull clk updates from Stephen Boyd: "Mostly the usual clk driver updates and new SoC additions plus non-critical data fixes for things that weren't used yet. One thing that's new here in the core is SSC spread spectrum support (SSC) in the clk provider API. The idea is that DT authors will configure SSC for certain clks and they'll be configured at clk provider registration time or when a consumer device is probed, similar to how we handle assigned clk rates or parents. On the clk driver side we have Qualcomm adding almost half the diff because they add support for 4 different SoCs and then a long tail of other SoCs like Mediatek, Renesas, Rockchip, SpaceMiT, etc. add more SoC support this time around. Luckily it's mostly clk data for these new SoCs because the actual clk_ops are already there. Beyond the new drivers we get all the little fixups for more compilation coverage or usage of more modern APIs. That all looks normal. Finally, I kinda buried the lede, I'm bringing on Brian and Jerome to help out with maintaining the clk subsystem. The current working model is already semi-distributed in that silicon vendors typically take care of their drivers and send me pull requests but I'm becoming a bottleneck for new drivers and core framework review because this has become a 100% volunteer effort on my part. Mike is stepping down after all these years (thanks Mike!) and that jump started the conversation around finding co-maintainers. Brian and Jerome have graciously offered to help me with the work load, meaning in the future they'll be sending pull requests and committing directly to the clk.git tree. They've both been around on the list for a while, I've met them both in person, and they've been making changes to the core clk framework along with helping review patches so I'm pretty confident this will work well. Core: - devm_clk_bulk_get_enable() consumer API - devm_clk_hw_register_composite_pdata() provider API - Spread Spectrum Clock (SSC) support via DT bindings and provider APIs - Divider clk rounding improved (and tested) New Drivers: - Cix Sky1 audio subsystem (AUDSS) - UltraRISC DP1000 - MediaTek MT8173 MFG_TOP - Si549 - Aspeed AST2700 PECI - Airoha EN7523 PCIe - Rockchip RV1106 - Mobileye EyeQ7H - Qualcomm Maili GCC, TCSR, RPMh, and video clks - Qualcomm Shikra GCC, RPM, GPU, display, and audio clks - Qualcomm Nord display and graphics clks - Qualcomm Glymur camera and EVA clks - Qualcomm Hawi video clks - Amlogic A9 AO and peripheral clks - Renesas R-Car X5H (R8A78000) CPG" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (269 commits) clk: microchip: mpfs: fix regmap_update_bits() mask/val order clk: visconti: Make sure clk_init_data is fully initialized clk: ti: Make sure clk_init_data is fully initialized MAINTAINERS: Add Brian Masney and Jerome Brunet as co-maintainers for clk subsystem Drop Michael Turquette's clk maintainer entry clk: ti: composite: resolve parent clocks by DT index, not by name clk: ti: mux: resolve parent clocks by DT index, not by name clk: devres: fix cleanup in devm_clk_get_optional_enabled_with_rate() dt-bindings: clock: ti,keystone-gate: Convert to DT schema dt-bindings: clock: ti: Convert APLL clock to DT schema clk: zynq: pll: Fix kernel-doc after determine_rate() conversion dt-bindings: clock: ti,clockdomain: Convert to DT schema dt-bindings: clock: Correct white-space style clk: samsung: Don't include <linux/mod_devicetable.h> clk: at91: Read "reg" with helper clk: renesas: Add R-Car X5H CPG driver clk: rockchip: rk3576: fix source muxes for SPI0..SPI4 clk: rockchip: Add clock controller for the RV1106 dt-bindings: clock: rockchip: Add RV1106 CRU support dt-bindings: clock: Document Renesas R-Car X5H Clock Pulse Generator ... |
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Stephen Boyd
|
dd8eb789f1
|
Merge branches 'clk-pile' and 'clk-microchip' into clk-next
* clk-pile: (111 commits) clk: microchip: mpfs: fix regmap_update_bits() mask/val order clk: visconti: Make sure clk_init_data is fully initialized clk: ti: Make sure clk_init_data is fully initialized MAINTAINERS: Add Brian Masney and Jerome Brunet as co-maintainers for clk subsystem Drop Michael Turquette's clk maintainer entry clk: ti: composite: resolve parent clocks by DT index, not by name clk: ti: mux: resolve parent clocks by DT index, not by name clk: devres: fix cleanup in devm_clk_get_optional_enabled_with_rate() dt-bindings: clock: ti,keystone-gate: Convert to DT schema dt-bindings: clock: ti: Convert APLL clock to DT schema clk: zynq: pll: Fix kernel-doc after determine_rate() conversion dt-bindings: clock: ti,clockdomain: Convert to DT schema dt-bindings: clock: Correct white-space style clk: tegra: set up proper EMC clock implementation for Tegra114 clk: clocking-wizard: remove 20kHz restriction clk: clocking-wizard: optimize clock search clk: clocking-wizard: fix clock difference detection clk: mediatek: mt8135: Fix inverted gate control for devapc_ck clk: clocking-wizard: Program PLL CP/RES and lock parameters on reconfig clk: tegra: support 48MHz clock for pll_p_out1 ... * clk-microchip: clk: at91: Read "reg" with helper |
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Linus Torvalds
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c6cf4441a3 |
Devicetree updates for v7.3:
- Add a DT maintainer profile document - Various dt-check-style improvements - Add a devres managed reserved memory region init function - Print node name on any skipped reserved memory regions - Correctly handle optional argument in of_parse_phandle_with_args_map() - Convert ti,keystone-reset, ti,da850-vpif, TI L4 interconnect, TI SmartReflex, microchip,pic32mzda-dmt, microchip,pic32mzda-wdt, TI DA8XX MSTPRI bus, and Xen VM bindings to DT schema format - Add bindings for StarFive JHB100 plic, Allwinner A733 NMI controller, MediaTek MT8173 GPU, QCom Shikra, Eliza, and Maili cpu-bwmon, and QCom Shikra SCM firmware - A couple of syntax fixes found using PoC Rust implementation of dtschema tools - Clean-ups for typos, brackets, incorrect "::" usages, and white-space style -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEktVUI4SxYhzZyEuo+vtdtY28YcMFAmqA0pYACgkQ+vtdtY28 YcOGLRAAsSVfV1r7n9SmPQ246dRQeVkNo3ZAEFuqqeBzJjMNyVyYn4iCcwkYDhaY rRlRpanmhbooUJfRRpxpgIv8XwWOiha8eq9mojnbGfgq00/8BEnD16A7bwNDaxsf /IUVKYQs8x7AK3nGLXvJ2BXQZzAZCnwylnsW6Pbkhns3xuc3lED4BGRRRsPH4T77 lMh2cA8JjeaY9sC/6aosTg1342nj+QpC2qJOfd2ONsWCKKD3zYAWWVFpj17J4o3d XDpLIjR1X6aOKoWOMDqmjnC/vwQ3Zzmz84zfArb4bl0O9A/ENQ1XYuNJ5tohxWd0 LfWMOD6dUIaquuoRUSvWrnafgSqumjTYzLZeK5KLDT2xqAnBO3sfizjFq9c4AHO8 TkU74DZiIGH2VCGCQtm7v5gZGbGKJ0g2TndCbQhEa/OyvaNfZpItGJWCHY3kg5xd Wn60sk1L/HnwItwGH47xxeksc1TiuhqH3zfr4ztj9fenUnuLtmkjdhu8wZGjpYFq 2Jf2KIUJov4WLN6cyP51vf5L1+OoaSfZ/6nuaO+9bAa/j+GQiZpRQI95yEOcXBd/ QbAL1tA8w9IRpN/bZ5l+Hw9ZO9Q1hpLTV92xqOPvVDXvDR7xi/7R4dvRm86m9IcT FTtNLLkz76V0DTqgHWfNtwxulYa69NrZjtD+VooVw1BWMo8ExmQ= =54fa -----END PGP SIGNATURE----- Merge tag 'devicetree-for-7.3' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux Pull devicetree updates from Rob Herring: - Add a DT maintainer profile document - Various dt-check-style improvements - Add a devres managed reserved memory region init function - Print node name on any skipped reserved memory regions - Correctly handle optional argument in of_parse_phandle_with_args_map() - Convert ti,keystone-reset, ti,da850-vpif, TI L4 interconnect, TI SmartReflex, microchip,pic32mzda-dmt, microchip,pic32mzda-wdt, TI DA8XX MSTPRI bus, and Xen VM bindings to DT schema format - Add bindings for StarFive JHB100 plic, Allwinner A733 NMI controller, MediaTek MT8173 GPU, QCom Shikra, Eliza, and Maili cpu-bwmon, and QCom Shikra SCM firmware - A couple of syntax fixes found using PoC Rust implementation of dtschema tools - Clean-ups for typos, brackets, incorrect "::" usages, and white-space style * tag 'devicetree-for-7.3' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: (40 commits) dt-bindings: interconnect: qcom-bwmon: Add Maili cpu-bwmon compatible dtc: dt-check-style: Simplify setting depth of DtsLine dtc: dt-check-style: Add missing /dts-v1/ to few test cases dt-bindings: power: reset: ti,keystone-reset: Convert to DT schema media: dt-bindings: ti,da850-vpif: Convert to dt-schema dt-bindings: devfreq: samsung,exynos-ppmu: Use standard regex syntax dt-bindings: interrupt-controller: mediatek,mt6577-sysirq: Drop invalid JSON pointer dt-bindings: arm: omap: Convert L4 interconnect to DT schema dt-bindings: power: Convert TI SmartReflex to DT schema of: reserved_mem: Introduce devres-managed initialization function dt-bindings: interrupt-controller: Add StarFive JHB100 plic dt-bindings: irq: sun7i-nmi: Document the Allwinner A733 NMI controller dt-bindings: Correct white-space style dt-bindings: fix typos and brackets docs: dt: submitting-patches: Mention expectation about dt-check-style docs: dt: maintainer: Add Devicetree and OF maintainer profile document docs: dt: writing-schema: Extend expectations about example part of binding dt-bindings: gpu: powervr-rogue: Add MediaTek MT8173 GPU of: base: Handle optional argument in of_parse_phandle_with_args_map() dt-bindings: update Sudeep Holla's email address ... |
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Linus Torvalds
|
368cf60c36 |
soc: drivers for 7.3
The SoC driver changes once more consist of many small fixes and
cleanups, that are to a large part the result of automated testing. On
platform specific drivers, this includes SoC specific code for xilinx,
freescale/nxp, qualcomm, TI, aspeed, omap, tegra, samsung, rockchip,
renesas, ixp4xx. In firmware drivers, we see a similar picture for
SCMI and qcomtee.
Aside from these, we see actual new hardware support in a few
areas:
- The Apple platform gets a new driver for low power states
- Updates to Qualcomm platform drivers add several new
hardware specific features and additional SoCs.
- Amlogic SoC support for A1 and T7 is added
- The Mediatek MMSYS driver is refactored as a cleanup.
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Merge tag 'soc-drivers-7.3' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull SoC driver updates from Arnd Bergmann:
"The SoC driver changes once more consist of many small fixes and
cleanups, that are to a large part the result of automated testing.
On platform specific drivers, this includes SoC specific code for
xilinx, freescale/nxp, qualcomm, TI, aspeed, omap, tegra, samsung,
rockchip, renesas, ixp4xx. In firmware drivers, we see a similar
picture for SCMI and qcomtee.
Aside from these, we see actual new hardware support in a few areas:
- The Apple platform gets a new driver for low power states
- Updates to Qualcomm platform drivers add several new hardware
specific features and additional SoCs.
- Amlogic SoC support for A1 and T7 is added
- The Mediatek MMSYS driver is refactored as a cleanup"
* tag 'soc-drivers-7.3' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (157 commits)
soc: qcom: make QCOM_PDR_MSG selectable
soc: qcom: ubwc: Fix missing include
soc: qcom: ubwc: Fix link error when QCOM_SMEM=n
media: iris: Guard the QCOM_UBWC_CONFIG select with QCOM_SMEM
drm/msm: Guard the QCOM_UBWC_CONFIG select with QCOM_SMEM
dt-bindings: arm: qcom,ids: Add SoC ID for Snapdragon SDM 850
firmware: xilinx: Clear firmware notifiers across kexec transitions
firmware: xilinx: Release all peripheral devices from firmware
firmware: xilinx: Add support to clear EL3 PM state
firmware: xilinx: Propagate actual error from feature check
firmware: xilinx: Use TF-A feature check for TF-A-specific APIs
bus: fsl-mc: drop unused assignment of acpi_device_id::driver_data
soc: fsl: qe: check platform_driver_register() in qe_ic_of_init()
phy: lynx-10g: use RCW override procedure for dynamic protocol change
soc: fsl: guts: implement the RCW override procedure
dt-bindings: fsl: layerscape-dcfg: define DCFG_DCSR region
soc: fsl: guts: make fsl_soc_data available after fsl_guts_init()
soc: fsl: guts: make it easier to determine on which SoC we are running
soc: fsl: guts: add a central fsl_guts_read() function
soc: fsl: guts: add a global structure to hold state
...
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Arnd Bergmann
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545ecc3577 |
RISC-V Devicetrees for v7.3
Sophgo: The changes of this PR are all for CV18xx serials. There are three major changes. The first is to allow DMA multiplexer setting channel number for DMA controller; the second is to add initial RISC-V support for "Duo S" board, which uses SG2000, a dual-arch SoC (RISC-V and ARM64); the third is to add support for "Duo 256M" board, another dev-board based on SG2002 SoC. Signed-off-by: Chen Wang <chen.wang@linux.dev> -----BEGIN PGP SIGNATURE----- iHUEABYKAB0WIQTYPcWJ6By3aFu8IuKHG95Quc97dgUCanKEvQAKCRCHG95Quc97 dn44AP9HHp2ut8rY0UnmS/s+rCAbWX/2YkhGWdWPPk1o4VkSdQEArt9F9RpXg/Mp RfmT/LEx81g7zR7wqpGlpy1a5F+TBw4= =SAg0 -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmp57JAACgkQmmx57+YA GNla7xAAqMRFdMgCOH74zaNtohonnSgbmJi4dL6RakzJHCjZO+VWMnxavg/A8qTb DrSugeW0SV1pe/NbOKaJbqZ6xa/gJJitivPNJIgn8uM3WauetzE55isGPb+smR1r soqTG/3AYocT88fy7FgLL3GmvY9yd1dAOHA/CFdTpmBdrqfV5fSSmed08wM0lVQe O1EgjHe7eNk+v3DYo80buRxwljiW0gpbhFFsz84hbdFoL/Cf/GAXWP1xhZjCTKo1 9/Zex3J7SsdNAaZjDzMyF0S0eolyAPJW0SzToDkMniE/tSYc2lkjW7R1I55iuQvi BJ+kKK1k2/TrSbmvjuvqCEnwfOh9BzXPf4UWuLrUrEVTpdEBtpe0otFGRBqzg0lO RkgUPdHWR8uhL57Oos8HM4WH2VN4s0jqP0FN1sUp46fnnQFCEi/nO4vRTnOt+ppy HxNjJyQRrP97OH7s7zpUTyCVVJBZPL3EF3NuNCzioooXK3LHI4MSApTtDIt9bPBi yS5U1SaUaNm4RwCaFH9QZSQHXdoEXKe0DPX/P9cROr62T6eSyDhZnIIcucveMw+6 tJie38mJChficq8mCo3/S1P3gMELy5lmBw68XCg/UMBcdV76Mq4AgFq6o5Ow+oXp KS/sO+RkxZPD7ImnGLKrSuurJnIsMpOR/69lLFBkZ0LBtdZY9W4= =CrHg -----END PGP SIGNATURE----- Merge tag 'riscv-sophgo-dt-for-v7.3' of https://github.com/sophgo/linux into soc/dt RISC-V Devicetrees for v7.3 Sophgo: The changes of this PR are all for CV18xx serials. There are three major changes. The first is to allow DMA multiplexer setting channel number for DMA controller; the second is to add initial RISC-V support for "Duo S" board, which uses SG2000, a dual-arch SoC (RISC-V and ARM64); the third is to add support for "Duo 256M" board, another dev-board based on SG2002 SoC. Signed-off-by: Chen Wang <chen.wang@linux.dev> * tag 'riscv-sophgo-dt-for-v7.3' of https://github.com/sophgo/linux: riscv: dts: sophgo: Add Milk-V Duo 256M board support riscv: dts: sophgo: cv180x: Add PWR_GPIO controller dt-bindings: soc: sophgo: add Milk-V Duo 256M board riscv64: dts: sophgo: add initial Milk-V Duo S board support riscv64: dts: sophgo: add SG2000 dtsi riscv: dts: sophgo: cv180x: Allow the DMA multiplexer to set channel number for DMA controller Signed-off-by: Arnd Bergmann <arnd@arndb.de> |
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Arnd Bergmann
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30502a6a72 |
FSL SOC Changes for 7.3
Freescale QUICC Engine: - Use generic I/O helpers in interrupt controller for IO Ports - Move CONFIG_QE_GPIO out of powerpc - Fix DT scan for GPIO nodes - Convert IO ports interrupt controller to generic IRQ chip - Add support of IRQs in GPIO controller - Implement get_direction() in GPIO controller - Check platform_driver_register() in interrupt controller for IO Ports Data Path I/O: - Replace maintainer - Remove redundant dev_err() - Fix kernel-doc typos Freescale Management Complex: - Use strscpy() to copy strings into arrays - Remove redundant dev_err() - Drop unused assignment of acpi_device_id::driver_data Other changes: - Add kernel and device tree binding support for RCW override, completing the SerDes PHY driver functionality - Fix kernel-doc warnings and typos in DPAA header -----BEGIN PGP SIGNATURE----- iHUEABYKAB0WIQTH/wu6mIr0ZW+Vui/dkHAmvKvPUwUCanjJsQAKCRDdkHAmvKvP UwszAQDD8kadgq4T9kUl7LO9TzCfPbG39oyjY5b1xrtEmqPa2QEA55gxY7ker9KC GXDq12bKiI79q1C5acQOvvGtRzn50g4= =gVuJ -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmp5jCwACgkQmmx57+YA GNnQ1RAAoXeSmgQv7IV9lh9gxm/L5HaIHy8VZhOH++dWgNT7o4imnhg1v1Lf9wT9 cvIA17WlkcTDvF7yPpsli8BKpb3ohWlmiliuvkJBtFXMOawToOPA1JaMo3bwWdtV UDqHJGvaQ3fY0nfJZHUn3F6m43X0fpl1X7jqMwRu0n59G9grSN0a1JzH5fcvhzLc R3MZX8Xf0MkB7NnilSm6p9+NR7awFFOt+2F1MIaVJrTBCQsLQ7TZJ2PXznMGUqlZ E/eubTe4l3H3Tvf9Ymeoqn+eD9DaV4/thqtWkZieRuQ7sRKgpLLjLVIMmEy4C50B fVQBhRj3puj67qwxGbgfuQ0rO80e7Enx4rx4FP2wOEyz1srKMr5gaTAQfan8shW1 CZEAbx8OniBfFuLdOHueOjwyONYA2KWfvFcfhEaR1QXU5EFteUwOXKKQsA7A7j3i 9RhPkXukIoU/BG59ZspR9s5cegh4C54ATsrxkgnW2tCMSHPN27Zfn+UnTDQ0MGYj PIlrftuqcFWUjgjn7vdASwVEsyoPr1/c79GwmW6/8Wna3rZsJEKwEX47FDNxan96 /cF244Ljrg6e3SRVhuyCNqGgbCi/v6TMe3L5niKoDBLnpQh+WU9HRFTWUPJ/bOBz 8CxrN1kZa2oZU8IhZSMI1O9T8Y77yPElt8wEIetpxJ+DKK5fPpw= =76G2 -----END PGP SIGNATURE----- Merge tag 'soc_fsl-7.3-1' of https://git.kernel.org/pub/scm/linux/kernel/git/chleroy/linux into soc/drivers FSL SOC Changes for 7.3 Freescale QUICC Engine: - Use generic I/O helpers in interrupt controller for IO Ports - Move CONFIG_QE_GPIO out of powerpc - Fix DT scan for GPIO nodes - Convert IO ports interrupt controller to generic IRQ chip - Add support of IRQs in GPIO controller - Implement get_direction() in GPIO controller - Check platform_driver_register() in interrupt controller for IO Ports Data Path I/O: - Replace maintainer - Remove redundant dev_err() - Fix kernel-doc typos Freescale Management Complex: - Use strscpy() to copy strings into arrays - Remove redundant dev_err() - Drop unused assignment of acpi_device_id::driver_data Other changes: - Add kernel and device tree binding support for RCW override, completing the SerDes PHY driver functionality - Fix kernel-doc warnings and typos in DPAA header * tag 'soc_fsl-7.3-1' of https://git.kernel.org/pub/scm/linux/kernel/git/chleroy/linux: (31 commits) bus: fsl-mc: drop unused assignment of acpi_device_id::driver_data soc: fsl: qe: check platform_driver_register() in qe_ic_of_init() phy: lynx-10g: use RCW override procedure for dynamic protocol change soc: fsl: guts: implement the RCW override procedure dt-bindings: fsl: layerscape-dcfg: define DCFG_DCSR region soc: fsl: guts: make fsl_soc_data available after fsl_guts_init() soc: fsl: guts: make it easier to determine on which SoC we are running soc: fsl: guts: add a central fsl_guts_read() function soc: fsl: guts: add a global structure to hold state soc: fsl: guts: use a macro to encode the DCFG CCSR space soc: fsl: guts: perform fsl_guts_init() error teardown in reverse order of setup soc: fsl: dpio: fix kernel-doc typos soc: fsl: fix kernel-doc warnings and typos bus: fsl-mc: Remove redundant dev_err() soc: fsl: qe: Add support of IRQs in QE GPIO soc: fsl: qe: Rename irq variable to parent_irq soc: fsl: qe: Convert to generic IRQ chip soc: fsl: qe: Handle spurious interrupts soc: fsl: qe: Iterate over all pending interrupts in cascade handler soc: fsl: qe: Use generic_handle_domain_irq() ... Signed-off-by: Arnd Bergmann <arnd@arndb.de> |
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Arnd Bergmann
|
ec833fd504 |
Apple Soc driver updates for 7.3
- New driver and dt-bindings for Apple PMGR misc controls, which tweaks various global power related states and saves about 1W of power on M1 Pro/Max/Ultra during s2idle. - A small fix for device links in SART Signed-off-by: Sven Peter <sven@kernel.org> -----BEGIN PGP SIGNATURE----- iHUEABYKAB0WIQS3vz815OHsEaWy0u9EEX0kKnUe6QUCanYDQgAKCRBEEX0kKnUe 6ZuoAP98l5DFnC+mM8Hb58BKTNi0Aj4x+ZS6wUQQyEWGM/x9wAEAg4qGNtuaecIi fZDfSWHUSZ4/mpf7q9OwAtbpbvn3Jw0= =dNHf -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmp5hmEACgkQmmx57+YA GNnDiw//bh8x/MOhIM9wObUEZLdO9vLMCI3jnnxeZ7T5FQDKBAnkK3IV0yPo+IJg T2ypxkDkKYvlaN2nOXHIgH96N/K0YQwZMzea9M/ohIU6ftDdKm1YuOjfzAQaRjna uFsY90TUncG/956YY+iamGom+sUFwlGx64zniYL5WXEfQ80wHGhwNCtz1lmrX/ng 9wSBAzPMy8mZ9GUEbq5z6R2Dz7zs/9vRosOkhPAO2EnFKWEsviiVz7RT0w6pIZ6s VPtCTsC8re2Uu+UkqM/jg8xoH06Wb39HCHWLL655U34P6Bob0CCeYFmOK/Y9+9fC ndVlEGx30sRmNqcGjwDGEkn4tysnyu3A7ahZCRHPUFJgkEn1LOjFBX/+mPwFDjIV 6DExTuDbdroOI4F4CEJa+knNF5jOiX4IgnUFq1AjF5au4ZT4kEHboQmK67NVD2iJ A7aZqn0OR3da0+Bxa+BLGJd+ZB1mGoRQbf64I7mYRJsCO5iEGM5wuFPKmOZOfy7f 9J2l0lj7Yiw+WD2AnVrwApYVEpZBWvCNjCHpA1ctcgwqafY4psEkoJLt7pIcVaPa zTEh/kRb6LtK4F6m13s9QaWMgoWsoa9TYUou2Aeof2X4Uyg8qNMPMalRnIDB16gf eF/x9PBxRJ8JMDABzuR8TBcac+5ZZfjOuWMWMrvnAs57AqdO5C4= =KWIH -----END PGP SIGNATURE----- Merge tag 'apple-soc-drivers-7.3' of https://git.kernel.org/pub/scm/linux/kernel/git/sven/linux into soc/drivers Apple Soc driver updates for 7.3 - New driver and dt-bindings for Apple PMGR misc controls, which tweaks various global power related states and saves about 1W of power on M1 Pro/Max/Ultra during s2idle. - A small fix for device links in SART Signed-off-by: Sven Peter <sven@kernel.org> * tag 'apple-soc-drivers-7.3' of https://git.kernel.org/pub/scm/linux/kernel/git/sven/linux: soc: apple: Add driver for Apple PMGR misc controls dt-bindings: soc: apple: Add Apple PMGR misc controls soc: apple: sart: require device link for consumers Signed-off-by: Arnd Bergmann <arnd@arndb.de> |
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Arnd Bergmann
|
93d524fb91 |
More Qualcomm driver updates for v7.3
Add SMEM parsing for DDR configuration data and use its highest bank address bit to select the appropriate UBWC configuration. Enable generic PAS trusted-zone APIs for the Iris and Venus media drivers. Fix SCM probe retry state, reserved-memory cleanup, and an early IRQ-handler NULL dereference. Enable QSEECOM EFI variable access on the Asus Zenbook A16. Correct GENI firmware-size validation using the hardware CFG RAM depth and correct the PMIC GLINK Thunderbolt extradata layout. Document the Nord AOSS side channel and the IMEM minidump SRAM property. Clean up Qualcomm statistics macros and the WCNSS binding schema. -----BEGIN PGP SIGNATURE----- iQJCBAABCgAsFiEEBd4DzF816k8JZtUlCx85Pw2ZrcUFAmp1/J8OHGJqb3JuQGty eW8uc2UACgkQCx85Pw2ZrcXcZQ/9G3XLVoPBw7j1dyAfdDs1x16kZBoHxexXbPLQ RgNZHrcz2voh4pXOF21nf5Pv9eC+i4rZU0PzIBJBzHiW/0C+QMegOzx70upIgoBM V2Xsw/eqhfcPMl0xz/6LCYijGe1UXcdl1qD+blbe4qql+BFsZdG5skmqpEA2M6ZH DiD9II5hW/XNAZOFRkV64nV+oaX3nlU9HyusPIebL5YV8ZHjBis/QQpbObLHNUQy kL7UACS86U2PoR+womdoBcESArrEEpJzdezWwxjAS8nsOFoPUjzRaYxdlODm4rad xw+fB/loedU8yLfZpcE0GdEE6qwrwt4tda3X3ZeSfOuYqq+XiRA33CeRwCDb+XNK DlOpA3bRNTY8d3LZ+Worg329kRPB86fmvYTxsvurJ7/LTVSl1ZHotL0rdFOcL8BD sR3FIRXSPt/RUE0QY7Xq38BahsgWAjKt2TFNrtq2PJdQES2kYLXpx8+xAzFWeg// TxkM8UtA5dmt19svsAtELHyTGm8lWFBtbZSyHDbdGhDH6Wvf0PHNcsqY5lYIvwn+ 5+bpT00Os2KdlgaBvWzUxM+FoWJ1QH9hYjEJZRFdcWmtbnNRABBLcyyGgtAOffot mVjRrrRkgSBn+94eZTmqC25RPwZbkd1hog9ym5JUa2RLYfgsKDHW6rb1p/+Qp601 diAdn9s= =hi1p -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmp5hSsACgkQmmx57+YA GNk9Lw//d58iG3MEb2ttm1MTuUv1S5f3kaleALzaGJh7mXk7MrtdYd+nVEKsXJ4m tmBQW2TmrjUdj36YkIhkyuiX0iE2Y6Gje+pm1v7axbqWGJ3Kr48Ytrc/QrlCS6Ji nHz4aZx7Lm6HYiGkl9QVajkP3w/FDnlk+awLc0kN/0BqzEkyPKrJYTePz7FHnfhy kRmpzMBZY05MG3MxxJU57bJHWntmKL4rCSpTUdVMP28lb8lIRLbrK7IEIoCR+Css bciH++o8pBFrJv3ryexMlUmR5Ua38BjuoDXeK17PwqoB2My8CJUJAf8+dKVWGJ9h efpSGJKfUjpDTUJKqKESx11jb900DPpFg773JwtJCRTP+7TZU1iv/6KxyfNgz6Qx LGNUEehZ6nYRUo91v5FX4jBaafEHqpl/PLUQIPqvaCcYTQ1pw+TZKBhA/EZJucuv RrE9fLt1ivn7+YaJSrEavzsPzMiXHs+Y61zbb1OEIGAg07uu9GUTjhaI+DfUIDNf VT5v8Y4TopL8NEHsSekaJ4Zu4gGe/gOreZWlxDBtbtMWB7T4KmgRPJhAmrp40bQq B6LcmsDw80YCa46MRbF9PnvM7YEOdZox4Riw8V5IcdHd2IjwfMGPD75TY56mMlIC u0LBNKuaOtG+Y9m7TeJ/W8kElAib71dh4wZb5xmqrZcVLmRgtxo= =TIvW -----END PGP SIGNATURE----- Merge tag 'qcom-drivers-for-7.3-2' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/drivers More Qualcomm driver updates for v7.3 Add SMEM parsing for DDR configuration data and use its highest bank address bit to select the appropriate UBWC configuration. Enable generic PAS trusted-zone APIs for the Iris and Venus media drivers. Fix SCM probe retry state, reserved-memory cleanup, and an early IRQ-handler NULL dereference. Enable QSEECOM EFI variable access on the Asus Zenbook A16. Correct GENI firmware-size validation using the hardware CFG RAM depth and correct the PMIC GLINK Thunderbolt extradata layout. Document the Nord AOSS side channel and the IMEM minidump SRAM property. Clean up Qualcomm statistics macros and the WCNSS binding schema. * tag 'qcom-drivers-for-7.3-2' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: media: qcom: Switch to generic PAS TZ APIs dt-bindings: soc: qcom,aoss-qmp: Document Nord AOSS side channel dt-bindings: sram: qcom,imem: Add minidump-sram pattern property soc: qcom: qcom_stats: Replace CLIENT_VOTES_OFFSET macro with sizeof() soc: qcom: qcom_stats: Remove unused macro definitions soc: qcom: ubwc: Get HBB from SMEM soc: qcom: smem: Expose DDR data from SMEM soc: qcom: smem: Use 'unsigned int' instead of 'unsigned' firmware: qcom: scm: Fix tzmem state on probe retry firmware: qcom: scm: Fix reserved memory cleanup on probe failure firmware: qcom: scm: Fix NULL dereference in IRQ handler before __scm is published firmware: qcom: scm: Allow QSEECOM on Asus Zenbook A16 (UX3607OA) soc: qcom: geni-se: Use HW PROG_RAM_DEPTH to validate firmware size soc: qcom: pmic_glink_altmode: Define the TBT extradata properly dt-bindings: soc: qcom,wcnss: Drop redundant $ref of firmware-name property Signed-off-by: Arnd Bergmann <arnd@arndb.de> |
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Alexandre Belloni
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b8b3f6e974 |
arm64: dts: NXP device tree updates for v7.3
New boards and SOM support: - Variscite DART-MX8M-MINI, DART-MX8M-PLUS, VAR-SOM-MX8 QuadMax (with Sonata and Symphony carrier boards) - TQMa8MPxS (i.MX8MP) with LVDS overlays, TQMa9596LA on MBa95xxCA; TQMa91xx on MBa93xxCA - imx8mm-verdin: Toradex DSI displays (7"/10.1"), HDMI adapter, NAU8822 BTL audio, Cortex-M4F remoteproc and UART overlay i.MX8: - PCIe: add power supply properties to Root Port nodes. - imx8mp-evk add typec and usb3_phy1 tuning; imx8mq-evk add typec; - imx8mp-evk add flexcan2 overlay and CAN2/MICFIL board mux; imx8mp-frdm fix HDMI DDC pinctrl - imx8mp-var-som-symphony: add second Ethernet, CAN, PWM1, ECSPI2, capacitive touchscreen, HDMI, PCIe, USB, TPM, external RTC, input keys, header UARTs - imx8mq-evk: add DCSS node, uart3/bluetooth node - imx8qm: add SCU power key, lsio mu8/mu8b, spdif1, lpuart4 nodes; fix LPCG clock indices for ASRC0; add Variscite Symphony board support - imx8ulp: add I3C2, eDMA channel properties, LPUART6 (BT) and LPUART7, gpio-keys power button; correct SRAM node address/size; update rpmsg resource table address; rename 9x9-evk model string - imx8mp: enable MU2 for DSP communication (imx8mp-ab2) i.MX9: - PCIe: add Root Port nodes with correct outbound address space for imx94/imx943/imx95; add dma/intr/aer/pme interrupts for imx95 PCIe; remove 'supports-clkreq' from imx943-evk PCIe1 - imx95: switch USB3 controller to flattened model; add CM7/CM33S nodes for imx943/imx952/imx95-19x19-evk; add imx94 DMA channels (xspi); enable NETC block control and in-band SFP status (imx95-var-dart); add wm8904 DMICDAT1; add lpuart5 alias (imx95-toradex-smarc) - imx93: add LVDS Display Bridge support with DY1212W-4856 panel overlay for imx93-11x11-evk; add LVDS overlays for imx93-tqma9352 boards; update TMU compatible string; fix memory node for imx93-kontron - imx91: add WM8524 and PDM microphone sound cards, CAN overlay, audio board muxes (imx91-9x9-qsb); move ELE reserved memory into 512MB range; USB phy adjustments (imx91-tqma9131) Layerscape / S32G: - ls1028a/ls1046a/ls1088a/ls208xa/lx2160a/lx2162a: describe Lynx 10G SerDes blocks; refactor lx2160a PCIe and SerDes into separate dtsi files; transition to device-specific SerDes compatible strings - s32g: add GPR syscon region; describe GPIO and EIRQ in SIUL2 pinctrl Cleanup and warning fixes: - correct imx8/s32g3 indentation - imx8mp: add missing #sound-dai-cells to xcvr -----BEGIN PGP SIGNATURE----- iQHFBAABCgAvFiEEJS45w2QNr0ezLVaoNF3oRQ23YkwFAmprfTgRHGZyYW5rLmxp QG54cC5jb20ACgkQNF3oRQ23Ykyh7Av/bGjTZ/3yQiG8wIU27lJlvfErpZt7p+iL 4qcFX9rXx+XvWqn7tm45nWTFsgte4CcnbpL6iLL7u/QQNpks6sfVYUcJAESzFlSO CpW+iRu/XisAqmFIxi+Xvf63vfy8s0SfYFFRcnlBS9WzfJECzpOalCN1uKvAm+0o 8dAwTL4EWNIwPeDgX1ngdwhL4vzDYLCBjt4ct/pIWXVWamzyUebfoN2DvxEXm5+C PvP+uU3P7TYtmYNESmPHKMkMgqmUJH570Jb2f8xZdm8adp1CaT7xrqngCLAN3/Gv /I/r6b7PRL+WL7lSLnyRvrwoHwH1kCDH6/3a/jEFkRWnSSLoz6GiORPlvJHzu1Mf 43/3Tv4ffKVyVC1vD5mqS6hb3UyWQ4bkL17NJAZGTF5tRK9qK3lufUw8ZEgSlXFY V1HPf3bajl75ZQ07Ra38rdjYfqBFypr/lrnBng0lXlVIMtEvgF0qQe1pdjTgr4qt qf/BNnAScEJpHO4ETNvLZsyadmkf8K6w =0Nmj -----END PGP SIGNATURE----- Merge tag 'imx-dt64-7.3' of https://git.kernel.org/pub/scm/linux/kernel/git/frank.li/linux into soc/dt arm64: dts: NXP device tree updates for v7.3 New boards and SOM support: - Variscite DART-MX8M-MINI, DART-MX8M-PLUS, VAR-SOM-MX8 QuadMax (with Sonata and Symphony carrier boards) - TQMa8MPxS (i.MX8MP) with LVDS overlays, TQMa9596LA on MBa95xxCA; TQMa91xx on MBa93xxCA - imx8mm-verdin: Toradex DSI displays (7"/10.1"), HDMI adapter, NAU8822 BTL audio, Cortex-M4F remoteproc and UART overlay i.MX8: - PCIe: add power supply properties to Root Port nodes. - imx8mp-evk add typec and usb3_phy1 tuning; imx8mq-evk add typec; - imx8mp-evk add flexcan2 overlay and CAN2/MICFIL board mux; imx8mp-frdm fix HDMI DDC pinctrl - imx8mp-var-som-symphony: add second Ethernet, CAN, PWM1, ECSPI2, capacitive touchscreen, HDMI, PCIe, USB, TPM, external RTC, input keys, header UARTs - imx8mq-evk: add DCSS node, uart3/bluetooth node - imx8qm: add SCU power key, lsio mu8/mu8b, spdif1, lpuart4 nodes; fix LPCG clock indices for ASRC0; add Variscite Symphony board support - imx8ulp: add I3C2, eDMA channel properties, LPUART6 (BT) and LPUART7, gpio-keys power button; correct SRAM node address/size; update rpmsg resource table address; rename 9x9-evk model string - imx8mp: enable MU2 for DSP communication (imx8mp-ab2) i.MX9: - PCIe: add Root Port nodes with correct outbound address space for imx94/imx943/imx95; add dma/intr/aer/pme interrupts for imx95 PCIe; remove 'supports-clkreq' from imx943-evk PCIe1 - imx95: switch USB3 controller to flattened model; add CM7/CM33S nodes for imx943/imx952/imx95-19x19-evk; add imx94 DMA channels (xspi); enable NETC block control and in-band SFP status (imx95-var-dart); add wm8904 DMICDAT1; add lpuart5 alias (imx95-toradex-smarc) - imx93: add LVDS Display Bridge support with DY1212W-4856 panel overlay for imx93-11x11-evk; add LVDS overlays for imx93-tqma9352 boards; update TMU compatible string; fix memory node for imx93-kontron - imx91: add WM8524 and PDM microphone sound cards, CAN overlay, audio board muxes (imx91-9x9-qsb); move ELE reserved memory into 512MB range; USB phy adjustments (imx91-tqma9131) Layerscape / S32G: - ls1028a/ls1046a/ls1088a/ls208xa/lx2160a/lx2162a: describe Lynx 10G SerDes blocks; refactor lx2160a PCIe and SerDes into separate dtsi files; transition to device-specific SerDes compatible strings - s32g: add GPR syscon region; describe GPIO and EIRQ in SIUL2 pinctrl Cleanup and warning fixes: - correct imx8/s32g3 indentation - imx8mp: add missing #sound-dai-cells to xcvr * tag 'imx-dt64-7.3' of https://git.kernel.org/pub/scm/linux/kernel/git/frank.li/linux: (131 commits) arm64: dts: imx95: Add dma, intr, aer and pme interrupts for PCIe arm64: dts: imx94-xspi: add the DMA channels arm64: dts: freescale: imx8mm-verdin: Add Cortex-M4F UART_4 overlay arm64: dts: freescale: imx8mm-verdin: Add Cortex-M4F remoteproc arm64: dts: freescale: imx8mm-verdin: Add Toradex Capacitive Touch Display 7" DSI arm64: dts: freescale: imx8mm-verdin: Add Toradex Capacitive Touch Display 10.1" DSI arm64: dts: freescale: imx8mm-verdin: Add Toradex DSI to LVDS adapter with 10.1" display arm64: dts: freescale: imx8mm-verdin: Add DSI to HDMI adapter overlay arm64: dts: freescale: imx8mm-verdin: Add NAU8822 Bridge Tied Load arm64: dts: imx95-var-dart-sonata: enable in-band status for SFP arm64: dts: imx8ulp-evk: Update rpmsg resource table address arm64: dts: imx943-evk: Add CM7 and CM33S nodes arm64: dts: imx952-evk: Add CM7 node and related memory nodes arm64: dts: imx95-19x19-evk: Add CM7 node and related memory nodes arm64: dts: imx8qm-var-som-symphony: enable expansion header UART arm64: dts: imx8ulp-9x9-evk: Rename model string to reflect die size arm64: dts: imx8ulp-evk: Change the values of some PCRs of ENET arm64: dts: imx8ulp-evk: Enable LPUART7 arm64: dts: imx8ulp-evk: Enable LPUART6 for Bluetooth arm64: dts: imx8ulp-evk: Add gpio-keys node for power button ... Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> |
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Vladimir Oltean
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d1b710f463 |
dt-bindings: fsl: layerscape-dcfg: define DCFG_DCSR region
In Layerscape (Arm) and QorIQ (PowerPC) devices, hardware peripherals
are accessed by the CPU through a portion of the SoC address space
called CCSR ("Configuration, Control, and Status Registers"). All
hardware IP blocks have their registers mapped here, and the Device
Configuration block makes no exception.
However, there exists a secondary range of the address space named DCSR
("Debug Control and Status Registers") which, like CCSR, also holds
registers of hardware IP blocks, except the DCSR contents is hidden in
all public reference manuals.
The intention of the CCSR/DCSR split, to the best of my knowledge, was
to place the functionality that is too low level for normal use, and
which is necessary only for debug, in a completely separate address
space which can be hidden.
A use case has appeared where networking SerDes lanes need to be
reconfigured at runtime for a different protocol (example: 10GBase-R to
SGMII), and the architecture of the SoCs does not normally permit that.
The Reset Configuration Word (RCW) is a data structure read by the SoC
preboot loader (PBL) which contains stuff like pinmuxing and SerDes
protocol mapping for each lane.
The RCW that the PBL has loaded is visible in the DCFG block's normal
status registers (from CCSR), as read only. Turns out, the RCW is also
mapped in the DCFG's shadow register map (in DCSR), in a write-only
form. Writing to the RCW registers from the DCFG's DCSR space to change
what the PBL has loaded is called "RCW override".
It has been validated that the RCW override procedure is necessary to
reconfigure the networking data path when a SerDes lane performs a major
protocol change. It changes some internal muxes which connect the PCS to
either the 10G MAC or to the 1G MAC.
Defining the DCSR area of the DCFG as a secondary 'reg' array element
allows operating systems to perform RCW overrides. Since it is
introduced late in the binding's lifetime, it is optional. It can be
identified by name, but also by index (first 'reg' is CCSR).
Note that while all SoCs should have a DCFG register block in DCSR, we
only need to expose it for the SoCs where the RCW override procedure is
known to be needed and has been validated.
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20260721231603.67865-8-vladimir.oltean@nxp.com
Signed-off-by: Christophe Leroy (CS GROUP) <chleroy@kernel.org>
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Arnd Bergmann
|
6a05421154 |
Qualcomm driver updates for v7.3
Add Maili platform bindings for SCM, IMEM, AOSS, and PMIC GLINK. Add Shikra IMEM, RPM SMD, LLCC, and UBWC support, including handling for firmware-configured LLCC ECC interrupts. Add the generic Peripheral Authentication Service with SCM and OP-TEE backends, and migrate the MSM DRM and IPA drivers to it. Add SCM SMC-call tracepoints and configurable minidump delivery through always-on SRAM. Correct SCM download-mode pointer ordering and improve download-mode probe diagnostics. Rework the UBWC configuration database and add Milos and Shikra configuration. Add protection-domain mappings for SA8775P and QCS8300, support newer ICE versions, Hawi subsystem statistics, and SDM850 identification. Simplify Qualcomm SoC Kconfig selection and architecture dependencies. Use managed resources in EBI2 and RPMh RSC probe paths to correct cleanup on failures. -----BEGIN PGP SIGNATURE----- iQJCBAABCgAsFiEEBd4DzF816k8JZtUlCx85Pw2ZrcUFAmprfkkOHGJqb3JuQGty eW8uc2UACgkQCx85Pw2ZrcUUVQ/+NufSVHC2E2W/ZTTVGAWCoB9rvNhPaPCoYrFY WsefQzhdCk54rzzb1DsVyj/Lh/nKVApdH495TWgWrUpRuq6w0xjHkYKklQNp7Hqt Lr2GNx90mvQDgvj1RNa++oI8dhpeEv/d7as0xrwQibi85mw/F/jGpHdw7VnfcRF5 XcTIIMtA+M5KWxmTBnwH+pgB5aaEDUED82mifcdOeNgI7l6A20jBdT0MJ8SZBMff wTMbuSOOEJlNjtcGtFm4EDdpVsoL1s4vAt0PGyVPpGvT2WVE1aGffPS4dMv4kNDU xFQsh6ST+J25W9r4zib5HB6FivgKcEvkMmZb4ca/bcJGxAEb163Yyay8Z+sz4kNV qEHjbm7zSfUiKELsFzzaulnLhEghZ6R/CQua+XdXq5J3QgKocqJ3m/a2Mm5rRXHv XUE+aEy/cJdxxhqan8BZ8Ihn1SkMRCDNWTVopi4H12RtIfXBII/9LEWW8fp66GlW 55TYLjTrdA5V56/NHmm1fsHDP7KojHUTipg9WL07OL/LggJExOvBpBZIoCQPUOR7 bB6jlf8bu00Ecur091+HkFD1ePcT0DTO+1tHdpG2mv27WXVVsFAZmIDp3G64cEn3 vZOVNDEZBjyE/MMqKwd+W0ERERoQnW+YYdtigN5tWmk/+M+/11D/10x6FPr1Q+38 OdidhsU= =+KlS -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmpyRQsACgkQmmx57+YA GNkjJQ//RfK/MpMrLOk4IPiA/+Ek93eXgVqfcXwUTAhg23HddOkOgZugVLi//xv0 flRkb/XbOc6aYOTIdmR6thfFOMkUbRxQl5EqSypNEWsrjsiVKbxmqH801BPPgFRw KzbmqNNe1O0koJ+p7b6g9kwXzEyF9iyBqjZqfWfbayqcznI1DC8x2Hs8ieBQvsKj 7igqDpLE2XhRuBhIRxOmKb17nvYaAS0/Jxa97Mhic7CEyNmC0EWUWXwJzWDJSBSv 253kTU6JVXcm7BI33lIvkAZbUwMo8wtz6hApJPj+JCELXNho9CTondOMhQ+lLZmx kZ3yJQRGQS41+nb6BVfVJkqfkErnxRM18sYbMzpEk79mnoN6OtomMypNQozq5U8/ qhA6sgygjL/jI62RCUTmiFhTXgkBXRw/yDiAUihaYWmCExUc/TCXw2Yb1FNk9m5m k9l4F9ynH1DoFRCtzOzqtO72ZqBnbuELnYZ/AA/mw3bFyHAKeLfmQpREqWfDcJCO g3me14uHHdWaMcoAICOBv9Obx1blxXU3vx6Fvm7ZJU4yygWvM/8BrroViHRGtUOb a8vggrcangB6JxMMX3AygpYu0kIBILRXUvsQccavcNkf5p1p0nQhKEgdHpD4n72r f70dhESEmIOLAxUI+ByQIh6deUJCPbOa/RE4F8QRaoTz8CcZKFc= =5310 -----END PGP SIGNATURE----- Merge tag 'qcom-drivers-for-7.3' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/drivers Qualcomm driver updates for v7.3 Add Maili platform bindings for SCM, IMEM, AOSS, and PMIC GLINK. Add Shikra IMEM, RPM SMD, LLCC, and UBWC support, including handling for firmware-configured LLCC ECC interrupts. Add the generic Peripheral Authentication Service with SCM and OP-TEE backends, and migrate the MSM DRM and IPA drivers to it. Add SCM SMC-call tracepoints and configurable minidump delivery through always-on SRAM. Correct SCM download-mode pointer ordering and improve download-mode probe diagnostics. Rework the UBWC configuration database and add Milos and Shikra configuration. Add protection-domain mappings for SA8775P and QCS8300, support newer ICE versions, Hawi subsystem statistics, and SDM850 identification. Simplify Qualcomm SoC Kconfig selection and architecture dependencies. Use managed resources in EBI2 and RPMh RSC probe paths to correct cleanup on failures. * tag 'qcom-drivers-for-7.3' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (44 commits) soc: qcom: llcc: Skip ECC interrupt setup on Shikra, pre-configured by DSF dt-bindings: sram: Document qcom,shikra-imem compatible net: ipa: Switch to generic PAS TZ APIs firmware: qcom: scm: Add minidump SRAM support firmware: qcom: scm: use dev_err_probe() for dload address failure firmware: qcom: scm: Fix missing smp_load_acquire() dt-bindings: firmware: qcom,scm: Add minidump SRAM property drm/msm: Switch to generic PAS TZ APIs bus: qcom-ebi2: use managed resources for clocks and children soc: qcom: rpmh-rsc: manage PM notifiers with devres firmware: qcom: scm: Allow QSEECOM on Honor Magicbook Art 14 firmware: qcom: scm: instrument SMC call path with tracepoints firmware: qcom: scm: add trace events for the SMC call interface soc: qcom: Avoid SCM and SPM for cpuidle drivers soc: qcom: Make important drivers default soc: qcom: Restrict drivers per ARM/ARM64 soc: qcom: Hide all drivers behind selectable menu MAINTAINERS: Add maintainer entry for Qualcomm PAS TZ service firmware: qcom: Add a PAS TEE service firmware: qcom_scm: Migrate to generic PAS service ... Signed-off-by: Arnd Bergmann <arnd@arndb.de> |
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|
Arnd Bergmann
|
484ddb357c |
Amlogic drivers for v7.3:
- Clock measure debugfs fixup - Clock measure support for Amlogic A1 & T7 -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEPVPGJshWBf4d9CyLd9zb2sjISdEFAmppuGgACgkQd9zb2sjI SdHMxxAAuWIZcX7X4r5NEuX0FIv9segRbi9RvWln3mi23d6tP2WI6b1Um54iYloa NtFY9lFtWDDEIwqh+5cSuqV2GtkPHccf8DuFQPScJrcqG/YuBEKiGam2/gPqkUn9 cYeWaaHzPhgRp14oJ4FRq+aazKb1HncSUBiCXl7H4iv1tWYfdFqtEh/06e0OiNGc p/MCs61/6RRjP2ofrxn/+dlrk/aX3GMeIBHqIxObCaTbsa6rA4z/lZqfr+V+UApk C7gIEcr1D2TBrCx6Y/MiiOwNyurHFVKbSb62XAjxOLRqoAHnI1GECweO6J0wcz/n Z/evQMmzgxcOsoQO9DweRJ8WAZiKsjBt7FkM6uyDBsb7XjIfqHIvqAQMnXfQnZmJ QdMoadmuJ4N2WHu/w65BrICEJj0gHuN3Cc51oRMwp8Z6D53yBXqwGuZ0ruLoBB3G niTzguF91H8/ExxFrNjT8X3Xsn61Yduz+cA1/zAjnWIDjwS80a/kJHneqwFB8y2k CxfUcLaEejgiTcZOiRRRI/zHqS+hMpbvJw3OVZsrDkAXoabjDzT6c+i/7Yp91IUj a3xf0Ri3IAZRkMEGDvZw4jYeZ5brMCMgTpGGPNXjHkCiQw8AKLI3bEN2oOdFUQid dvHFCoHL96DqCjQQgdWT2iyXSKdkq9CI667NKRaJjxjIKdONxmI= =fKAj -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmpyQg0ACgkQmmx57+YA GNmaGg//Wtu6r9JQek5bWH5ZYXBcJi2mZXH0lHm6/mylqOpVaLZ3Ivguey20gNhg AqMeh3QlhrfaG4yxzR246j4WnVAi080CVU9rt8Z8oK0ox3U18mmGcL+u4vzr0blZ 751htm7fZ4LXaJjp5ahBfbFuUpQyi9hFihPfjY1ZBUtkc7KgigjrRPYi/41I2Sx6 r7yW9A3XpAlA/qhhOt6eAC8iidhimp6U4j+HQxa9ynFJk1E0hI+mI4MktbnpXl2x Z2kR6axrgJpgIMIIz6ywLyvZxUNDnQLPGhyRf3BK+m7A9BmY+Ej/FLmKPnII/yIp XBngV9ES6Kd3MDuTlGhh7O/IfZETatDjVw8XQfReGK2dK8K/XTswRU4DVFqdQbRB nEjKdOHCpi/AYpKGbREHfCd3b+EGwHfLkH93lmy1aWDF6wPzfZkR1+UNsBETPUjL qt5D1PcL9tNbZriXl3HFixFQlsyKP5My1h+0jmFSbCJQI7mSnM3B1NDajSSYN0ny MBaibHcsAApH/ZEQE/e8r+E9wNabHOLlen3owHtwuRlSvA5tMeGy2dzu3q8KZPC+ lUhsI3Sa8l2cMTvLzoJVtuH2A8oQfJL+bEYeSrEV4U1pIny7a1jkkbaQWhEEWsNL ws0Wfs/u4sdSCJinZgy3aLHhOyQ+v5Mfp4aHWSeskWtPhahAaBY= =wjNR -----END PGP SIGNATURE----- Merge tag 'amlogic-drivers-for-v7.3' of https://git.kernel.org/pub/scm/linux/kernel/git/amlogic/linux into soc/drivers Amlogic drivers for v7.3: - Clock measure debugfs fixup - Clock measure support for Amlogic A1 & T7 * tag 'amlogic-drivers-for-v7.3' of https://git.kernel.org/pub/scm/linux/kernel/git/amlogic/linux: soc: amlogic: meson-clk-measure: remove debugfs tree soc: amlogic: clk-measure: Add A1 and T7 support dt-bindings: soc: amlogic: clk-measure: Add A1 and T7 compatible Signed-off-by: Arnd Bergmann <arnd@arndb.de> |
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Chen-Yu Yeh
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06c2369097
|
dt-bindings: soc: sophgo: add Milk-V Duo 256M board
Add compatible string for the Milk-V Duo 256M board. Signed-off-by: Chen-Yu Yeh <chenyou910331@gmail.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://patch.msgid.link/20260725175346.139173-2-chenyou910331@gmail.com Signed-off-by: Inochi Amaoto <inochiama@gmail.com> Signed-off-by: Chen Wang <chen.wang@linux.dev> |
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Christophe Leroy
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b6a375b38c |
dt-bindings: soc: fsl: qe: Convert QE GPIO to DT schema
Convert QE GPIO devicetree binding to DT schema. The old binding uses fsl,<chip>-qe-pario-bank because multiple MCP83XX SoC has support for these GPIO banks. The best practice is to list out every <chip> instead. Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu> Signed-off-by: Paul Louvel <paul.louvel@bootlin.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Reviewed-by: Christophe Leroy (CS GROUP) <chleroy@kernel.org> Link: https://lore.kernel.org/r/20260708-qe-pic-gpios-v2-3-1972044cfbd1@bootlin.com Signed-off-by: Christophe Leroy (CS GROUP) <chleroy@kernel.org> |
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Shawn Guo
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a60558ae65 |
dt-bindings: soc: qcom,aoss-qmp: Document Nord AOSS side channel
Document Always-on Subsystem side channel on Qualcomm Nord SoC. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260729023508.879752-2-shengchao.guo@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org> |
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Krzysztof Kozlowski
|
3fd6a04e5b |
dt-bindings: soc: qcom,wcnss: Drop redundant $ref of firmware-name property
The DT schema core defines the type ($ref) of 'firmware-name' property as string-array, so individual schemas do not need to. They also should not redefine it to a single string, but instead just set number of expected firmware names. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20260712162212.184592-2-krzysztof.kozlowski@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org> |
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Arnd Bergmann
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ce9af94e6d |
Samsung SoC drivers for v7.3
1. Fix very old leak of OF node in PMU driver. 2. Few cleanups and new bindings for ExynosAutov920 HSI0 syscon. -----BEGIN PGP SIGNATURE----- iQJEBAABCgAuFiEE3dJiKD0RGyM7briowTdm5oaLg9cFAmpnqlgQHGtyemtAa2Vy bmVsLm9yZwAKCRDBN2bmhouD1+MtD/9M66W36D7KaI9tnHLxVO+2h+VZV73Q9+jI Siy6LaytoSX9Zz3jYYeLT8AFCm2ykbydGfIWOBw8lWKrc5tSlQhE/zFrl8fcigr6 7xvHbHPoUa/cv8yxDn0v0JPQtnbKyRz6+vNuYPSTGFsLCqavMEPlq3PGNz43j5rG 6TgbpE2HC1K0fhuYMkootj/O4QLVN0RbUbAjYmdbxY35/z5pPq/5lAvOZU9GdI9d l+rICXNJy9ZMPw9u5HR8IEDiV9dH+Znwk7jkGxIzyDpSxi4FW9jrfui124aqFDCU qc97cBzYZ1mf7FK1zkfT3KRZ/TaAxl49kxbOB4WzOxDDtZ866ciSN2OGtvMmFlzd 5jnHj7b7hnm5L1U59GPDZD940qNFydK/2cgS1x4bc0aPsT324NxV/m0TuzIro91Z xwbllGGfHmEC5Rl1WthrrXZPBTkM23KJAdvA9d4M/yPv6tEMJsAkqwKcoiV+wPeQ hhtuyH2bCw+UZZ7rxN0gAuT8hdj1bexuminZilixCBAZkNymV9njiueipNEL9Hb0 2bfTKE84plPjjQ8ijgoAZ/Sefv/6at51gEwYjWZnX66huzkp3w8pXj2MhkG7lgmv DC5hWpOU/kFNCamePeQUeJ9hwbdPCy13NDkjmuh0s6Ouzy9DpuIxCmE4U8cID5MQ x+Rh4YbWPQ== =xeyD -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmpqFiQACgkQmmx57+YA GNlYKw/+KxY6PubRpNhKHivaGqFBFgD+GlPaJNRMkFgXYIiUz6CDwnFK0v9XozOr UfwrfIDGBvdq0XrNJmiRPW68A4PhGV9MP7Tq3iwEFr/hjRCgjylGNe92znzTIHat oJtB96EdAPd+Dgr5vuZ923yA9t3zGf1Ns5YqlLos7xGWDBzXuAKmQVbf7j7exLg5 FwjabWAwHsf3le13WYsEY4TleqHMYuspLnsIVSQXJwiX4Ex67ndKcwQdIECY7eYs y7790ofY67mBa2y+JRiybCMCk6KbgBxtbDb1jL/GJ8zde4mpoX7hdJ8u6hMIdOMJ 5lpHL0m31nuKyzIsBAAKcdKJviNL09d8yy+RzU1/DT84kVxz6eFsxfj+NR6inHKE ZsBZS7oJRoRpMxCLxvnE44PVFCnCuv517CqvDfvEyCMx2pKmUl3C2O1CgE5mIK2n FqgbuTy4rQLw7pKR3HF+qEyhyHYiuARWftVuXPWf8NHCPNSb37x50HjC4FYJPcOq rP9fKAlqxHd4CQ0WlUx1J0mmp5USmYj9xbc2aUS/g1bJ1GaWfSuT/a7wZuI57769 HIc2Mqv9G+3LaEd2UNCods7QXW3zZTK80qm8WyEm4PddSX/9K6R/gzCzl0CwMfCe /qFewzZTL9SJ4F3MRiefc897g7+JMtrg5+xNbZyIInUGJQsR3sA= =rMXV -----END PGP SIGNATURE----- Merge tag 'samsung-drivers-7.3' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into soc/drivers Samsung SoC drivers for v7.3 1. Fix very old leak of OF node in PMU driver. 2. Few cleanups and new bindings for ExynosAutov920 HSI0 syscon. * tag 'samsung-drivers-7.3' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux: dt-bindings: samsung: exynos-pmu: Narrow allowed reboot modes dt-bindings: samsung: exynos-pmu: Restrict children with unevaluatedProperties dt-bindings: soc: samsung: exynos-sysreg: Add hsi0 for ExynosAutov920 soc: samsung: exynos-pmu: fix of_node refcount leak in exynos_get_pmu_regmap() Signed-off-by: Arnd Bergmann <arnd@arndb.de> |
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Joakim Zhang
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48ceae43be |
dt-bindings: soc: cix: add sky1 audss cru controller
The Cix Sky1 Audio Subsystem (AUDSS) Clock and Reset Unit (CRU) groups clock muxing, gating and block-level software reset control in a single register block. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Joakim Zhang <joakim.zhang@cixtech.com> Signed-off-by: Brian Masney <bmasney@redhat.com> |
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Benoît Monin
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c74d7d8021 |
dt-bindings: soc: mobileye: Add EyeQ7H OLB
The Other Logic Blocks (OLB) found in Mobileye SoCs contain hardware sub-functions grouped in a logical device. The EyeQ7H features 14 such OLB. The main differences with the previous generation of SoC are that some blocks have two clock sources instead of one and that the clock source can be the one of the clock output of another OLB instead of the main oscillator. For the blocks with a single parent clock, the name of that clock is "ref", similar to what is done for the OLB of the previous SoC. The blocks with two parent clocks use either "ref" for the main oscillator, "ref_100p0" for a 100MHz reference clock or "ref_106p6" for 106.6MHz reference clock. Some OLB also contain a reset controller with one or more reset domain, like the blocks found in the EyeQ6H. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Benoît Monin <benoit.monin@bootlin.com> |
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Sasha Finkelstein
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a49c2acde6 |
dt-bindings: soc: apple: Add Apple PMGR misc controls
Certain Apple SoCs include additional PMGR power states that are controlled via a different "misc" control block. On existing SoCs, this includes the fabric and memory controller state. Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Sasha Finkelstein <k@chaosmail.tech> Reviewed-by: Joshua Peisach <jpeisach@ubuntu.com> Link: https://patch.msgid.link/20260705-pmgr-misc-v3-1-51b75fed6f73@chaosmail.tech Signed-off-by: Sven Peter <sven@kernel.org> |
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AngeloGioacchino Del Regno
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11c3fc9e3d
|
dt-bindings: soc: mediatek: mutex: Improve title and description
Improve both the title and the description of this hardware to disambiguate its functionality from a hardware mutex and/or from a hwspinlock. Though in datasheets this is called "DISP_MUTEX", the meaning is is "Mute-X" (where "X" means "any hardware trigger signal") really as this is what this piece of hardware does: muting or unmuting of signals in each sub-IP of the display or other multimedia related controllers. Based on that, also clarify the description text, as to make sure that the information is actually accurate. While at it, also avoid forcing literal blocks in the description as there is nothing in there needing that (no ascii graph or other stuff that needs a literal block anyway), and add myself in the list of maintainers. Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> |
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Fenglin Wu
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49bd2cc8c3 |
dt-bindings: soc: qcom: qcom,pmic-glink: Add Maili compatible string
Maili is a mobile platform that is compatible with Hawi and Kaanapali platform with respect to pmic-glink support. Add Maili compatible string with Kaanapali as a fallback. Signed-off-by: Fenglin Wu <fenglin.wu@oss.qualcomm.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260610-maili-pmic-glink-v1-1-a6ba02d6deba@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org> |
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Krzysztof Kozlowski
|
e131ca83da |
dt-bindings: samsung: exynos-pmu: Narrow allowed reboot modes
syscon-reboot-mode schema allows arbitrary "mode-.* properties but only a subset actually makes sense and is valid. Provide negative look-ahead pattern to disallow any modes not supported by the device, which tightens the binding. Most of Android-based Exynos devices share the bootloader or its parts, thus reboot modes are most likely the same, however only a few upstream DTS define them, so add restrictions only for these. Google GS101 has on the other hand quite different bootloader with many known reboot modes. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Reviewed-by: Peter Griffin <peter.griffin@linaro.org> Acked-by: Rob Herring (Arm) <robh@kernel.org> Link: https://patch.msgid.link/20260701105731.196618-4-krzysztof.kozlowski@oss.qualcomm.com Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> |
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Krzysztof Kozlowski
|
3527091de0 |
dt-bindings: samsung: exynos-pmu: Restrict children with unevaluatedProperties
Each schema for a child node should end with either additionalProperties or unevaluatedProperties, so add missing one making the schema tighter. Defining 'type: object' is on the other hand not necessary when other schema is referenced. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Reviewed-by: Peter Griffin <peter.griffin@linaro.org> Acked-by: Rob Herring (Arm) <robh@kernel.org> Link: https://patch.msgid.link/20260701105731.196618-3-krzysztof.kozlowski@oss.qualcomm.com Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> |
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Chunkai Deng
|
30783d878a |
dt-bindings: soc: qcom,aoss-qmp: Document the Maili AOSS side channel
Document the Always-on Subsystem side channel on Qualcomm Maili SoC. Signed-off-by: Chunkai Deng <chunkai.deng@oss.qualcomm.com> Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260604-maili-soc-binding-v2-3-21b5e9bd1aa5@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org> |
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Krzysztof Kozlowski
|
39eace59ac |
dt-bindings: rockchip: grf: Narrow allowed reboot modes
syscon-reboot-mode schema allows arbitrary "mode-.* properties but only a subset actually makes sense and is valid. Provide negative look-ahead pattern to disallow any modes not supported by the device, which tightens the binding. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Link: https://patch.msgid.link/20260701105849.197086-4-krzysztof.kozlowski@oss.qualcomm.com Signed-off-by: Heiko Stuebner <heiko@sntech.de> |
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Jian Hu
|
457462828d |
dt-bindings: soc: amlogic: clk-measure: Add A1 and T7 compatible
Add the Amlogic A1 and T7 compatible for the clk-measurer IP. Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Jian Hu <jian.hu@amlogic.com> Link: https://patch.msgid.link/20260421-clkmsr_a1_t7-v3-1-efc00b0f9e6b@amlogic.com Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> |
||
|
Krzysztof Kozlowski
|
5de561db57 |
dt-bindings: Drop incorrect usage of double '::'
There is no use of double colon '::' in YAML. OTOH, the literal style block, e.g. using '|' treats all characters as content [1] therefore single use of ':' in descriptions is perfectly fine, whenever '|' is used. Cleanup existing code, so the confusing style won't be re-used in new contributions. Link: https://yaml.org/spec/1.2.2/#literal-style [1] Acked-by: Conor Dooley <conor.dooley@microchip.com> Acked-by: Alim Akhtar <alim.akhtar@samsung.com> Acked-by: Sebastian Reichel <sebastian.reichel@collabora.com> Acked-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Acked-by: Mark Brown <broonie@kernel.org> Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> # renesas Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Acked-by: Andi Shyti <andi.shyti@kernel.org> Link: https://patch.msgid.link/20260623054842.21831-4-krzysztof.kozlowski@oss.qualcomm.com Signed-off-by: Rob Herring (Arm) <robh@kernel.org> |
||
|
Liu Ying
|
0ff57bce94 |
dt-bindings: soc: imx: fsl,imx93-media-blk-ctrl: Allow LVDS Display Bridge child node
i.MX93 SoC mediamix blk-ctrl contains one LDB_CTRL register and one LVDS register which control video output through a LVDS interface. Allow the LVDS Display Bridge(LDB) child node and add the child node to example. i.MX93 LDB child node(bridge@20) is an addressable node, while i.MX93 Parallel Display Format Configuration(PDFC) child node(dpi-bridge) is a non-addressable node. Mixing the addressable and non-addressable child nodes is allowed according to discussion [1]. Link: https://lore.kernel.org/all/n6akxiayi3g6gxcqhreb4iaohmeokoalnqup6h5r2fwdt4zijt@u2wyps55ayqm/ [1] Signed-off-by: Liu Ying <victor.liu@nxp.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Frank Li <Frank.Li@nxp.com> |
||
|
Sanghoon Bae
|
d3ebfcb661 |
dt-bindings: soc: samsung: exynos-sysreg: Add hsi0 for ExynosAutov920
Add hsi0 compatible on samsung,exynos-sysreg To support ExynosAutov920 PCIe settings: - PCIe PHY power control - PLL settings for PCIe - PCIe device direction (RC/EP) Signed-off-by: Sanghoon Bae <sh86.bae@samsung.com> Reviewed-by: Peter Griffin <peter.griffin@linaro.org> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://patch.msgid.link/20260610050326.2903402-2-sh86.bae@samsung.com Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> |
||
|
Komal Bajaj
|
beb6c1bac2 |
dt-bindings: soc: qcom: smd-rpm: Add Shikra rpm-smd compatible
Add compatible for the Qualcomm Shikra rpm-smd device. Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com> Signed-off-by: Sneh Mankad <sneh.mankad@oss.qualcomm.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20260508-shikra_mailbox_and_rpm_changes-v3-1-698f8e5fb339@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org> |
||
|
Linus Torvalds
|
09fb6892f3 |
Devicetree updates for v7.2:
DT core:
- Add support for handling multiple cells in "iommu-map" entries.
- Support only 1 entry in /reserved-memory "reg" entries. Support for
more than 1 entry has been broken.
- Fix a UAF on alloc_reserved_mem_array() failure
- Make "ibm,phandle" handling logic specific to PPC
- Use memcpy() instead of strcpy() for known length strings
- Ensure __of_find_n_match_cpu_property() handles malformed "reg"
entries
- Add various checks that expected strings are strings before accessing
them
- Drop redundant memset() when unflattening DT
DT bindings:
- Add a DTS style checker. Currently hooked up to dt_binding_check to
check examples.
- Convert st,nomadik platform, ti,omap-dmm, and ti,irq-crossbar
bindings to DT schema
- Add Apple System Management Controller hwmon, Qualcomm Hamoa Embedded
Controller, Qualcomm IPQ6018 PWM controller, fsl,mc1323, Samsung
SOFEF01-M DDIC panel, Freescale i.MX53 Television Encoder, Samsung S2M
series PMIC extcon, and MT6365 PMIC AuxADC schemas
- Extend bindings for QCom Maili and Nord PDC, QCom Hali fastrpc,
qcom,eliza-imem, qcom,oryon-1-5 CPU, and MT6365 Keys
- Consolidate "sram" property definitions
- Fix constraints on "nvmem" properties which only contain phandles and
no arg cells
- Another pass of fixing "phandle-array" constraints
- Add Gira vendor prefix
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Merge tag 'devicetree-for-7.2' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux
Pull devicetree updates from Rob Herring:
"DT core:
- Add support for handling multiple cells in "iommu-map" entries
- Support only 1 entry in /reserved-memory "reg" entries. Support for
more than 1 entry has been broken
- Fix a UAF on alloc_reserved_mem_array() failure
- Make "ibm,phandle" handling logic specific to PPC
- Use memcpy() instead of strcpy() for known length strings
- Ensure __of_find_n_match_cpu_property() handles malformed "reg"
entries
- Add various checks that expected strings are strings before
accessing them
- Drop redundant memset() when unflattening DT
DT bindings:
- Add a DTS style checker. Currently hooked up to dt_binding_check to
check examples
- Convert st,nomadik platform, ti,omap-dmm, and ti,irq-crossbar
bindings to DT schema
- Add Apple System Management Controller hwmon, Qualcomm Hamoa
Embedded Controller, Qualcomm IPQ6018 PWM controller, fsl,mc1323,
Samsung SOFEF01-M DDIC panel, Freescale i.MX53 Television Encoder,
Samsung S2M series PMIC extcon, and MT6365 PMIC AuxADC schemas
- Extend bindings for QCom Maili and Nord PDC, QCom Hali fastrpc,
qcom,eliza-imem, qcom,oryon-1-5 CPU, and MT6365 Keys
- Consolidate "sram" property definitions
- Fix constraints on "nvmem" properties which only contain phandles
and no arg cells
- Another pass of fixing "phandle-array" constraints
- Add Gira vendor prefix"
* tag 'devicetree-for-7.2' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: (50 commits)
dt-bindings: interrupt-controller: qcom,pdc: Add Maili compatible string
dt-bindings: interrupt-controller: ti,irq-crossbar: Convert to DT schema
dt-bindings: vendor-prefixes: add Gira
dt-bindings: embedded-controller: Add Qualcomm reference device EC description
dt-bindings: pwm: add IPQ6018 binding
dt-bindings: hwmon: Add Apple System Management Controller hwmon schema
docs: dt: writing-schema: Clarify what is required in a schema
of: Respect #{iommu,msi}-cells in maps
of: Factor arguments passed to of_map_id() into a struct
of: Add convenience wrappers for of_map_id()
of: reserved_mem: zero total_reserved_mem_cnt if no valid /reserved-memory entry
of: reserved_mem: handle NULL name in of_reserved_mem_lookup()
dt-bindings: cache: l2c2x0: Add missing power-domains
dt-bindings: interrupt-controller: renesas,r9a09g077-icu: Fix reg size in example
dt-bindings: nvmem: consumer: Make 'nvmem' an array of one-item entries
drivers/of/overlay: Use memcpy() to copy known length strings
dt-bindings: add self-test fixtures for style checker
dt-bindings: wire style checker into dt_binding_check
scripts/jobserver-exec: propagate child exit status
dt-bindings: add DTS style checker
...
|
||
|
Linus Torvalds
|
70cb95c736 |
soc: drivers for 7.2
There are a few added drivers, but mostly the normal maintenance to drivers
for firmware, memory controller and other soc specific hadware:
- The NXP QuickEngine gets modern MSI support, which allows some cleanups to
the GICv3 irqchip chip driver
- A new SoC specific driver for the Renesas R-Car MFIS unit is added,
encapsulating support for the on-chip mailbox and hwspinlock
implementations that are not easily separated into individual
drivers
- The Qualcomm SoC drivers add support for additional SoC implementations,
and flexiblity around power managedment for the serial-engine driver
as well as probing the LLCC driver using custom hardware descriptions
inside of the device itself.
- Added support for the Samsung thermal management unit
- A cleanup to the Tegra 'PMC' driver interfaces to remove legacy
APIs and allow multiple PMC instances everywhere.
- Updates to the TI SCI and KNAS drivers to improve suspend/resume
support.
- Minor driver changes for mediatek, xilinx, allwinner, aspeed, tegra,
broadcom, amd, microchip and starfive specific drivers
- Memory controller updates for Tegra and Renesas for additional SoC
types and other improvements.
- Firmware driver updates for Arm FF-A, SMCCC and SCMI interfaces,
to update driver probing, object lifetimes and address minor bugs.
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Merge tag 'soc-drivers-7.2' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull SoC driver updates from Arnd Bergmann:
"There are a few added drivers, but mostly the normal maintenance to
drivers for firmware, memory controller and other soc specific
hardware:
- The NXP QuickEngine gets modern MSI support, which allows some
cleanups to the GICv3 irqchip chip driver
- A new SoC specific driver for the Renesas R-Car MFIS unit is added,
encapsulating support for the on-chip mailbox and hwspinlock
implementations that are not easily separated into individual
drivers
- The Qualcomm SoC drivers add support for additional SoC
implementations, and flexibility around power management for the
serial-engine driver as well as probing the LLCC driver using
custom hardware descriptions inside of the device itself.
- Added support for the Samsung thermal management unit
- A cleanup to the Tegra 'PMC' driver interfaces to remove legacy
APIs and allow multiple PMC instances everywhere.
- Updates to the TI SCI and KNAS drivers to improve suspend/resume
support.
- Minor driver changes for mediatek, xilinx, allwinner, aspeed,
tegra, broadcom, amd, microchip and starfive specific drivers
- Memory controller updates for Tegra and Renesas for additional SoC
types and other improvements.
- Firmware driver updates for Arm FF-A, SMCCC and SCMI interfaces, to
update driver probing, object lifetimes and address minor bugs"
* tag 'soc-drivers-7.2' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (189 commits)
Revert "firmware: zynqmp: Add dynamic CSU register discovery and sysfs interface"
Revert "Documentation: ABI: add sysfs interface for ZynqMP CSU registers"
memory: tegra234: drop dead NULL check in tegra234_mc_icc_aggregate()
memory: tegra264: drop redundant tegra264_mc_icc_aggregate()
memory: tegra186-emc: stop borrowing MC aggregate hook for EMC
soc: aspeed: cleanup dead default for ASPEED_SOCINFO
firmware: tegra: bpmp: Add support for multi-socket platforms
firmware: tegra: bpmp: Propagate debugfs errors
soc/tegra: pmc: Add Tegra238 support
soc/tegra: pmc: Restrict power-off handler to Nexus 7
soc/tegra: pmc: Populate powergate debugfs only when needed
soc/tegra: pmc: Move legacy code behind CONFIG_ARM guard
soc/tegra: pmc: Remove unused legacy functions
soc/tegra: pmc: Create PMC context dynamically
firmware: samsung: acpm: remove compile-testing stubs
firmware: samsung: acpm: Add devm_acpm_get_by_phandle helper
firmware: samsung: acpm: Add TMU protocol support
firmware: samsung: acpm: Make acpm_ops const and access via pointer
firmware: samsung: acpm: Drop redundant _ops suffix in acpm_ops members
firmware: samsung: acpm: Annotate rx_data->cmd with __counted_by_ptr
...
|
||
|
Arnd Bergmann
|
3659b13199 |
Microchip RISC-V soc drivers for v7.2
A single dt-binding compatible addition for the irqmux on pic64gx. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> -----BEGIN PGP SIGNATURE----- iHUEABYKAB0WIQRh246EGq/8RLhDjO14tDGHoIJi0gUCaiakQAAKCRB4tDGHoIJi 0spXAQDsU+p0Dr7OhDDn5pP8I4/q2ucr+lqpAUY6i9hq14VuoQD/RqhGh16LFFou EssSKsXGD2uxxrFiv4V7dOp7Rg+lSAs= =4WhE -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIyBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmooKucACgkQmmx57+YA GNmWGA/4irxaH4mTli1QFDNPfDsQlY/Fr5AzOUtl7bNQN7F3xQmhZTUKo4gJW0K8 AnDS8iffdvTLPxlASQslSBQhd3FreWMCOD/iBUXaGkgg1dshg0h1rUyb4vvrqucH tjBZvZeFOd27SySJhDe8fsj8uNERIP3kaz00VIi/IR3IzPucJKFoH5kGUEYUu64x geXIA8tiS7s0y6rvWpuLt9n00uw5I0nbRIdTGTkyZPMQrwBwORjiu2JX/yXJPxkS fp/S3oaqOgXJk9hehqiJRf26vvQLWKVPbfWNoX1WZ5odltv9Pl68YNxgK6Q3rv2q AY4zQ2nbXLC8Re8/4ngRic3rFvodMGX7AjP9rxsA9YBKE39Q4Vdq50Gibmf4WBst spJIWX1tBt8UCx5pUIXUnNwhH/0QxqbUQrTMMX5FxWIZ6kdHz0t8ikNFXZxvsmLZ Jat6t87O+OIPwxg0K+muwKjWpBYolUunPZevp0SBjVrs5ULuKFCdHvjUHZol1tb+ d4MjMveHMxjqeKkyX9chtKf7nzujZIwU1kLcV7s288SBsz3gCTVcnyhJq0j68bVb Pphr1JN1JwuJyJCyQnOGI/XBENE9Tg+dRIhNErjLE2nn73VHb13VpNuKATOw4T2M CVzq6kQsyxKZK/Xm9bNtq8QOubjeC7aGbc6+3y8PCIoLDtj1Ow== =ZrlJ -----END PGP SIGNATURE----- Merge tag 'riscv-soc-drivers-for-v7.2' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into soc/drivers Microchip RISC-V soc drivers for v7.2 A single dt-binding compatible addition for the irqmux on pic64gx. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> * tag 'riscv-soc-drivers-for-v7.2' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux: dt-bindings: soc: microchip: document irqmux on pic64gx Signed-off-by: Arnd Bergmann <arnd@arndb.de> |
||
|
Krzysztof Kozlowski
|
9cf333de20 |
RISC-V Devicetrees for v7.2
Sophgo: For CV18xx serials: - Add bindings for Milk-V "Duo S" board. For SG2042: - The CPU unit address incorrectly used decimal numbers, especially for those nodes which value >= 10. Now corrected to use hexadecimal. - The MSI controller actually only supports 16 interrupts; corrected to match the actual situation. - PCIe RCs are cache-coherent with the CPU. Marked it out for RC nodes. For SG2044: - The same as SG2042, use hex for CPU unit address. In additional, update Chen Wang's email address for Sopgho SoC maintainer. Signed-off-by: Chen Wang <unicorn_wang@outlook.com> -----BEGIN PGP SIGNATURE----- iHUEABYKAB0WIQTYPcWJ6By3aFu8IuKHG95Quc97dgUCah/FnAAKCRCHG95Quc97 dhWzAQDU0rJDliEvffHvt4MBpMe5MuK5vgwxEun3YPCjCTzkpQEA6HT6IgHjlibB SLUn4X8cbJpupgI3czvkxogPNWeZYgE= =kAeE -----END PGP SIGNATURE----- Merge tag 'riscv-sophgo-dt-for-v7.2' of https://github.com/sophgo/linux into soc/dt RISC-V Devicetrees for v7.2 Sophgo: For CV18xx serials: - Add bindings for Milk-V "Duo S" board. For SG2042: - The CPU unit address incorrectly used decimal numbers, especially for those nodes which value >= 10. Now corrected to use hexadecimal. - The MSI controller actually only supports 16 interrupts; corrected to match the actual situation. - PCIe RCs are cache-coherent with the CPU. Marked it out for RC nodes. For SG2044: - The same as SG2042, use hex for CPU unit address. In additional, update Chen Wang's email address for Sopgho SoC maintainer. Signed-off-by: Chen Wang <unicorn_wang@outlook.com> * tag 'riscv-sophgo-dt-for-v7.2' of https://github.com/sophgo/linux: riscv: dts: sophgo: reduce SG2042 MSI count to 16 riscv: dts: sophgo: sg2042: use hex for CPU unit address riscv: dts: sophgo: sg2044: use hex for CPU unit address riscv: dts: sophgo: Add dma-coherent to SG2042 PCIe controllers dt-bindings: soc: sophgo: add sg2000 plic and clint documentation dt-bindings: soc: sophgo: add Milk-V Duo S board compatibles MAINTAINERS: update Chen Wang's email address Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> |
||
|
Krzysztof Kozlowski
|
a451dd4b43 |
Renesas driver updates for v7.2 (take two)
- Identify the R-Car M3Le SoC, - Add Multifunctional Interface (MFIS) support for R-Car V4H and V4M. -----BEGIN PGP SIGNATURE----- iHUEABYKAB0WIQQ9qaHoIs/1I4cXmEiKwlD9ZEnxcAUCah1FOwAKCRCKwlD9ZEnx cAwKAQCHcFEsNEOFt1Tx6EnK1sACrdjqMlb0hR/rNuwIGz2sZQD/X2tqhSP4cpYA QPfA/+mo0RcJStl34No1weBgWJOB2QM= =zOyF -----END PGP SIGNATURE----- Merge tag 'renesas-drivers-for-v7.2-tag2' of https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/drivers Renesas driver updates for v7.2 (take two) - Identify the R-Car M3Le SoC, - Add Multifunctional Interface (MFIS) support for R-Car V4H and V4M. * tag 'renesas-drivers-for-v7.2-tag2' of https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel: soc: renesas: rcar-mfis: Add R-Car V4H/V4M support dt-bindings: soc: renesas: mfis: Add R-Car V4H/V4M support soc: renesas: Identify R-Car R8A779MD M3Le SoC Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> |
||
|
Bhargav Joshi
|
ffda432eb1 |
dt-bindings: soc: ti,omap-dmm: Convert to DT schema
Convert the TI OMAP Dynamic Memory Manager (DMM) dt binding from text format to DT schema. During conversion following changes were made: - Move file from /bindings/arm/omap to /bindings/soc/ti/ - Make the 'ti,hwmods' property optional and mark it deprecated as it is no longer used, it is kept to support legacy dtbs. - Add the missing required property 'interrupts' to example node. Signed-off-by: Bhargav Joshi <j.bhargav.u@gmail.com> Link: https://patch.msgid.link/20260605-ti-omap-dmm-v2-1-1b460742ec83@gmail.com Signed-off-by: Rob Herring (Arm) <robh@kernel.org> |
||
|
Joshua Milas
|
efe66eed43 |
dt-bindings: soc: sophgo: add Milk-V Duo S board compatibles
Document the compatible strings for the Milk-V Duo S board [1] which uses the SOPHGO SG2000 SoC. Link: https://milkv.io/duo-s [1] Signed-off-by: Joshua Milas <josh.milas@gmail.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://patch.msgid.link/20260530173347.33533-2-josh.milas@gmail.com Signed-off-by: Inochi Amaoto <inochiama@gmail.com> Signed-off-by: Chen Wang <unicorn_wang@outlook.com> |
||
|
Geert Uytterhoeven
|
556304bddb |
Renesas R-Car X5H MFIS DT Binding Definitions
DT bindings and binding definitions for the Renesas R-Car X5H (R8A78000) Multifunctional Interface (MFIS), shared by driver and DT source files. -----BEGIN PGP SIGNATURE----- iHUEABYKAB0WIQQ9qaHoIs/1I4cXmEiKwlD9ZEnxcAUCafhrNgAKCRCKwlD9ZEnx cEYxAQD75qANLTBGvyEIvcSjM099aebREw0CoFgrbhSZ8S/cMwD9H3DjKC1nEcdt Ai6vhFqT6Ps8BILUCPB84VDHj++zOw0= =iPDZ -----END PGP SIGNATURE----- Merge tag 'renesas-r8a78000-dt-binding-defs-tag1' into renesas-dts-for-v7.2 Renesas R-Car X5H MFIS DT Binding Definitions DT bindings and binding definitions for the Renesas R-Car X5H (R8A78000) Multifunctional Interface (MFIS), shared by driver and DT source files. |
||
|
Marek Vasut
|
2cba284c0c |
dt-bindings: soc: renesas: Document R-Car R8A779MD Geist
Document the compatible value for the Renesas R-Car M3Le (R8A779MD) SoC and the Renesas Geist development board. The Renesas M3Le SoC is a register-compatible variant of the R8A77965 (M3-N) with reduced set of peripherals. The Geist board is derived from Renesas Salvator-X/XS boards, with adjustment for the R8A779MD SoC. Acked-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Link: https://patch.msgid.link/20260504144534.43745-5-marek.vasut+renesas@mailbox.org Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> |
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Arnd Bergmann
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b6a6fae6c5 |
Qualcomm driver updates for v7.2
Enable QSEECOM and with that access to UEFI variables on the Surface Pro 12in laptop. Refactor the Geni Serial-Engine helper code to allow the serial engine drivers (such as I2C) to operate on targets where power and performance is controlled through an SCMI server instead of individual resources in Linux. Extend the LLCC driver to support reading its data from a System Cache Table (SCT) in memory instead of being hard coded per platform in the driver. Also add support for the Eliza platform. Add support for the Hawi platform to pd-mapper. Switch the SMEM driver to track partitions using xarray to handle the ever growing number of hosts better. Extend the socinfo driver with knowledge about the Nord, SM7750, IPQ9650, and Shikra SoCs, as well as PMAU0102, PMC1020H, PMIV0102, and PMIV0104 PMICs. Define UBWC 3.1 and add a couple of convenient helpers in the UBWC library for MDSS and Adreno. Fix a memory leak in the WCNSS firmware download mechanism. -----BEGIN PGP SIGNATURE----- iQJCBAABCgAsFiEEBd4DzF816k8JZtUlCx85Pw2ZrcUFAmoVuSUOHGJqb3JuQGty eW8uc2UACgkQCx85Pw2ZrcUJoBAAxf+8fFvYZif2gk1wzA01IINQgB5/2gYu9oSW Ex4YrHF2wV3BlzRjDnoQ9yC9mYyQeAwqy0pHPIEhJrh5pTc7sJLH5P+iXwe0JU2e GD6WtxRlSswIhDcmoJokSWNkyQxGu540Mh140/Bd0Pb0tMelh76wmzcpY31tzDOa APmtPCXWOdMGYAJSA5DMUMlKEENBNuD7yg0sYtoNz4+XVv4nsjMviEspyNN/fWHg UvL7IJPFwiKynsYrohTgFS5spXOR79aR1xPVsujoUVhzV/W0NFXiDgGLZa41QBAJ lfqmxQiNCZ6I3n2R4X1OULXy9vLZalLiXQzMOJhvPbjXjW1R6jy40f5+W9SZnNSH Q33nbkpJWG81gN5GeqwdPi1+gDDIMyw4A3+RaqRPJBYkYzG1NU2YD5ZNFpMrfRta BT0Nzs8wdmMQgHDGXhjuzMC1hrm9b8QOT12GUnm2hcL7DIJsJC2mtLmlrvnQSm8y 3iPDrEhok2GzSXOKs1EkRfennjLG2MM54Bv7WosNJjrQi2FWkwU2OeNavDxkHo4G JTWwOPFoRysHqmqLr9aIvQGV9lQ2W+57CqnjrbVeMNclJNUm0usZX/i3zX9jCG7R SGwdslqlE/PqJWjUN8S/+LECI54axJXlp3KE6+m+nkEsOQcYIxwU/PfZiG1vyJu1 0Y22gro= =mOpO -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmoaDQQACgkQmmx57+YA GNm/KxAAumqFwdnLIK37ui8u3FG1he/Pal9RwXR0dJkLTAYmCK5vd/e/GEjTL0BG W2Zv+Gt1kvm0BZ10b7AaQNKx5jnE7AsglOTHXXW8pVmZW7w1Fz8CP96SiZz2iKb0 Fqpuq8utUg7fxYzYZuPGMWNQVSf0dliZrygp8iTHop/2iaJzL/dOQHBtXSXvuJVW FhCYtaDIBXpLzbFpe8z+QMM5bYmgiIF8zqdmOSe92LYVVWv1WNzflu8+fGDCxv9z EhsLdkM62xCR2a5YE0Tx0/44hw6sGh7ffnfkkIrEJvIBtkjxoERc0TRGXcvTeUnp bX4H1d/kanzvUu+0KrP+fxiCQL1DmiUi8SOEFx0YUSrBSp0HtIdgVyLxM6Q0UYdc JP95xqb/SfvVGRf3FFrP8NlIwM7n8NGpV8PqUnQ0K+NVUnsQWPJPZ+lkyCjX6G3b pXR/eSe4OBu3xjUAB2x7r0YQbEjlB1FeVQEA5lRdlW5QSzty/kLgUm/z+4rLQSq1 Zmw9rL28SnlOsoESF0/EAgNUTFfG+cA1wERwa9BdQbb3CzWxKU6QsAInL6ZEp1xI eTtGI+ia9yUv4pzMOiuv00seQQ2A45Qww6xkgsM2n0wbP1Bza9Rrkc1w9exK36ho JZkQ773gwyEYyRfHoobYyFRYtMve4JOWCjGjL5F3Gtw3YddABXU= =ryJr -----END PGP SIGNATURE----- Merge tag 'qcom-drivers-for-7.2' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/drivers Qualcomm driver updates for v7.2 Enable QSEECOM and with that access to UEFI variables on the Surface Pro 12in laptop. Refactor the Geni Serial-Engine helper code to allow the serial engine drivers (such as I2C) to operate on targets where power and performance is controlled through an SCMI server instead of individual resources in Linux. Extend the LLCC driver to support reading its data from a System Cache Table (SCT) in memory instead of being hard coded per platform in the driver. Also add support for the Eliza platform. Add support for the Hawi platform to pd-mapper. Switch the SMEM driver to track partitions using xarray to handle the ever growing number of hosts better. Extend the socinfo driver with knowledge about the Nord, SM7750, IPQ9650, and Shikra SoCs, as well as PMAU0102, PMC1020H, PMIV0102, and PMIV0104 PMICs. Define UBWC 3.1 and add a couple of convenient helpers in the UBWC library for MDSS and Adreno. Fix a memory leak in the WCNSS firmware download mechanism. * tag 'qcom-drivers-for-7.2' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (40 commits) soc: qcom: geni-se: Introduce helper APIs for performance control soc: qcom: geni-se: Introduce helper API for attaching power domains soc: qcom: geni-se: Add resources activation/deactivation helpers soc: qcom: geni-se: Handle core clk in geni_se_clks_off() and geni_se_clks_on() soc: qcom: geni-se: Introduce helper API for resource initialization soc: qcom: geni-se: Add geni_icc_set_bw_ab() function soc: qcom: geni-se: Refactor geni_icc_get() and make qup-memory ICC path optional soc: qcom: llcc-qcom: Fix NULL vs IS_ERR() bug in qcom_llcc_get_fw_config() soc: qcom: llcc-qcom: Add support for Eliza dt-bindings: cache: qcom,llcc: Document Eliza LLCC block soc: qcom: ubwc: add helper controlling AMSBC enablement soc: qcom: ubwc: define helper for MDSS and Adreno drivers soc: qcom: ubwc: define UBWC 3.1 soc: qcom: socinfo: Add SoC ID for Nord SA8797P dt-bindings: arm: qcom,ids: Add SoC ID for Nord SA8797P soc: qcom: socinfo: Add SoC ID for SM7750 dt-bindings: arm: qcom,ids: Add SoC ID for SM7750 soc: qcom: socinfo: Add PMIC PMAU0102 soc: qcom: socinfo: Add PMIV0102 & PMIV0104 PMICs firmware: qcom: scm: Allow QSEECOM on Surface Pro 12in ... Signed-off-by: Arnd Bergmann <arnd@arndb.de> |
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Wolfram Sang
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2e9b940f07 |
dt-bindings: soc: renesas: mfis: Add R-Car V4H/V4M support
The above SoCs have only 12 mailboxes and do not have an extra register space for mailboxes. Everything is contained in the common register set. In addition to adding these SoCs, the other entries get updated to enforce 2 register spaces and their specific number of interrupts. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://patch.msgid.link/20260519075620.4128-2-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> |
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Conor Dooley
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17d9064987 |
dt-bindings: soc: microchip: document irqmux on pic64gx
Being practically identical to PolarFire SoC, pic64gx has a irqmux that's entirely compatible with that on mpfs. Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> |
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Mukesh Ojha
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c5f5156ed4 |
dt-bindings: soc: qcom,aoss-qmp: Document the Hawi AOSS side channel
Document the Always-on Subsystem side channel on Qualcomm Hawi SoC. Signed-off-by: Mukesh Ojha <mukesh.ojha@oss.qualcomm.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260427181609.3648384-1-mukesh.ojha@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org> |
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Fenglin Wu
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676f67060a |
dt-bindings: soc: qcom: qcom,pmic-glink: Add Hawi compatible string
Hawi is a mobile platform that is compatible with Kaanapali platform with respect to pmic-glink support. Add the Hawi compatible string with Kaanapali as a fallback. Signed-off-by: Fenglin Wu <fenglin.wu@oss.qualcomm.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260419-hawi-pmic-glink-v1-1-a26908c468fc@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org> |
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Deepti Jaggi
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35466ef5db |
dt-bindings: qcom: geni-se-qup: Add compatible for SA8797P SoC
Document GENI Serial Engine QUP Wrapper Controller on Nord SA8797P SoC which is compatible with SA8255P one. Signed-off-by: Deepti Jaggi <deepti.jaggi@oss.qualcomm.com> Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260427005901.230237-1-shengchao.guo@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org> |
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Abel Vesa
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7754a6b6a1 |
dt-bindings: soc: qcom,aoss-qmp: Document the Eliza Always-On Subsystem side channel
Document the Always-On Subsystem (AOSS) side channel found on the Qualcomm Eliza SoC. It is used for communication with other clients, like remoteprocs. Acked-by: Rob Herring (Arm) <robh@kernel.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260504-eliza-bindings-aoss-v2-1-c3628ca79a25@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org> |
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Abel Vesa
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a390203b7e |
dt-bindings: soc: qcom: qcom,pmic-glink: Document Eliza compatible
Document the compatible for the PMIC GLINK interface found on the Qualcomm Eliza SoC. It is fully compatible with the one found on SM8550, so use that as fallback. Acked-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260504-eliza-bindings-pmic-glink-v2-1-d6b5397b7899@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org> |
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Wolfram Sang
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0f63ba15dd |
dt-bindings: soc: renesas: Document MFIS IP core
Document the Renesas Multifunctional Interface (MFIS) as found on the Renesas R-Car X5H (r8a78000) SoC. MFIS includes features like Mailbox/HW Spinlock/Product Register/Error Injection/Error Detection and the likes. Family-compatible values are not introduced here because MFIS is usually very different per SoC. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260402112709.13002-2-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> |
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Linus Torvalds
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d730905bc3 |
Support for Mobileye EyeQ6Lplus
Cleanups and fixes -----BEGIN PGP SIGNATURE----- iQJOBAABCAA4FiEEbt46xwy6kEcDOXoUeZbBVTGwZHAFAmniNBwaHHRzYm9nZW5k QGFscGhhLmZyYW5rZW4uZGUACgkQeZbBVTGwZHB2QA//U53JZYmmOxKxwbYwLvK9 Z8MuVgkvA/v7WktwL2PoMO0AlhQsteM5VtupddHhuhUiIr7gPy6Z7pEE9sDqM3gj p1d6vrg5XiWlh1fURdSqvzufKsm/etpElbvc2JjkcqD0sMGJUwlkP3ncZk/DCus6 zhcvya7jVxyvzbCBgJSM8QHvOoj/g3EV4hsx8Ymru8XSdLVEegodZtvUHVx4Q29U fmHCf1u/v+rJVbe2T3nuqsqzQhmaWkC+WyeVJIDUNecjclPoGNOeg8duICNfOu9q dtkzOua7v6rRsUA9GDbMcR44PWzL4LqGTOffzwF7uvYakOAp6nQWsymAUIfkQbE6 +I8heGaYPEQLjSHgCPI2WdJ4urbPdgsd5W2pC8s6WaHPdRlSMapH16I0DxmmNZlV CzW7o2ore5b8H4Mu5mboMjFzMY+A/0zC5S7twOpX+mvgPz+MTf1g0vD3hCSL+N7c LSW7rSZyd2smcgaHJBDpHceRHNZbVqloeO007DiJtrx+IWTBhvhFt2q/aqGG51xM 2P/lRZrA8vAMaTR1hZKLmxUPZpSekezoWC8GbWNeIg5NUUTOJoTAtQvT5vU40GZA 22o3s1a6rgz5KngV9rMWYERSV2yflvloYVo0ASVqgy1ijzzlsin/fbO976GdGD2I 7vrch6tajmTSBYeG0SuKiFY= =jKsJ -----END PGP SIGNATURE----- Merge tag 'mips_7.1' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux Pull MIPS updates from Thomas Bogendoerfer: - Support for Mobileye EyeQ6Lplus - Cleanups and fixes * tag 'mips_7.1' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux: (30 commits) MIPS/mtd: Handle READY GPIO in generic NAND platform data MIPS/input: Move RB532 button to GPIO descriptors MIPS: validate DT bootargs before appending them MIPS: Alchemy: Remove unused forward declaration MAINTAINERS: Mobileye: Add EyeQ6Lplus files MIPS: config: add eyeq6lplus_defconfig MIPS: Add Mobileye EyeQ6Lplus evaluation board dts MIPS: Add Mobileye EyeQ6Lplus SoC dtsi clk: eyeq: Add Mobileye EyeQ6Lplus OLB clk: eyeq: Adjust PLL accuracy computation clk: eyeq: Skip post-divisor when computing PLL frequency pinctrl: eyeq5: Add Mobileye EyeQ6Lplus OLB pinctrl: eyeq5: Use match data reset: eyeq: Add Mobileye EyeQ6Lplus OLB MIPS: Add Mobileye EyeQ6Lplus support dt-bindings: soc: mobileye: Add EyeQ6Lplus OLB dt-bindings: mips: Add Mobileye EyeQ6Lplus SoC MIPS: dts: loongson64g-package: Switch to Loongson UART driver mips: pci-mt7620: rework initialization procedure mips: pci-mt7620: add more register init values ... |