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1019 Commits
| Author | SHA1 | Message | Date | |
|---|---|---|---|---|
Linus Torvalds
|
d730905bc3 |
Support for Mobileye EyeQ6Lplus
Cleanups and fixes -----BEGIN PGP SIGNATURE----- iQJOBAABCAA4FiEEbt46xwy6kEcDOXoUeZbBVTGwZHAFAmniNBwaHHRzYm9nZW5k QGFscGhhLmZyYW5rZW4uZGUACgkQeZbBVTGwZHB2QA//U53JZYmmOxKxwbYwLvK9 Z8MuVgkvA/v7WktwL2PoMO0AlhQsteM5VtupddHhuhUiIr7gPy6Z7pEE9sDqM3gj p1d6vrg5XiWlh1fURdSqvzufKsm/etpElbvc2JjkcqD0sMGJUwlkP3ncZk/DCus6 zhcvya7jVxyvzbCBgJSM8QHvOoj/g3EV4hsx8Ymru8XSdLVEegodZtvUHVx4Q29U fmHCf1u/v+rJVbe2T3nuqsqzQhmaWkC+WyeVJIDUNecjclPoGNOeg8duICNfOu9q dtkzOua7v6rRsUA9GDbMcR44PWzL4LqGTOffzwF7uvYakOAp6nQWsymAUIfkQbE6 +I8heGaYPEQLjSHgCPI2WdJ4urbPdgsd5W2pC8s6WaHPdRlSMapH16I0DxmmNZlV CzW7o2ore5b8H4Mu5mboMjFzMY+A/0zC5S7twOpX+mvgPz+MTf1g0vD3hCSL+N7c LSW7rSZyd2smcgaHJBDpHceRHNZbVqloeO007DiJtrx+IWTBhvhFt2q/aqGG51xM 2P/lRZrA8vAMaTR1hZKLmxUPZpSekezoWC8GbWNeIg5NUUTOJoTAtQvT5vU40GZA 22o3s1a6rgz5KngV9rMWYERSV2yflvloYVo0ASVqgy1ijzzlsin/fbO976GdGD2I 7vrch6tajmTSBYeG0SuKiFY= =jKsJ -----END PGP SIGNATURE----- Merge tag 'mips_7.1' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux Pull MIPS updates from Thomas Bogendoerfer: - Support for Mobileye EyeQ6Lplus - Cleanups and fixes * tag 'mips_7.1' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux: (30 commits) MIPS/mtd: Handle READY GPIO in generic NAND platform data MIPS/input: Move RB532 button to GPIO descriptors MIPS: validate DT bootargs before appending them MIPS: Alchemy: Remove unused forward declaration MAINTAINERS: Mobileye: Add EyeQ6Lplus files MIPS: config: add eyeq6lplus_defconfig MIPS: Add Mobileye EyeQ6Lplus evaluation board dts MIPS: Add Mobileye EyeQ6Lplus SoC dtsi clk: eyeq: Add Mobileye EyeQ6Lplus OLB clk: eyeq: Adjust PLL accuracy computation clk: eyeq: Skip post-divisor when computing PLL frequency pinctrl: eyeq5: Add Mobileye EyeQ6Lplus OLB pinctrl: eyeq5: Use match data reset: eyeq: Add Mobileye EyeQ6Lplus OLB MIPS: Add Mobileye EyeQ6Lplus support dt-bindings: soc: mobileye: Add EyeQ6Lplus OLB dt-bindings: mips: Add Mobileye EyeQ6Lplus SoC MIPS: dts: loongson64g-package: Switch to Loongson UART driver mips: pci-mt7620: rework initialization procedure mips: pci-mt7620: add more register init values ... |
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Linus Torvalds
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31b43c079f |
soc: drivers for 7.1
The driver updates again are all over the place with many minor fixes
going into platform specific code. The most notable changes are:
- Support for Microchip pic64gx system controllers
- Work on cleaning up devicetree bindings for SoC drivers, and
converting them into the new format
- Lots of smaller changes for Qualcomm SoC drivers, including support
for a number of newly supported chips
- reset controller API cleanups and a new driver for Cix Sky1
- Reworks of the Tegra PMC and CBB drivers, along with a change
to how individual Tegra SoCs get selected in Kconfig and
BPMP firmware driver updates including a refresh of the ABI
header to match the version used by firmware
- STM32 updates to the firewall bus driver and support for
the debug bus through OP-TEE
- SCMI firmware driver improvements for reliability, in particular
for dealing with broken firmware interrupts
- Memory driver updates for Tegra, and a patch to remove the
unused Baikal T1 driver
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Merge tag 'soc-drivers-7.1' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull SoC driver updates from Arnd Bergmann:
"The driver updates again are all over the place with many minor fixes
going into platform specific code. The most notable changes are:
- Support for Microchip pic64gx system controllers
- Work on cleaning up devicetree bindings for SoC drivers, and
converting them into the new format
- Lots of smaller changes for Qualcomm SoC drivers, including support
for a number of newly supported chips
- reset controller API cleanups and a new driver for Cix Sky1
- Reworks of the Tegra PMC and CBB drivers, along with a change to
how individual Tegra SoCs get selected in Kconfig and BPMP firmware
driver updates including a refresh of the ABI header to match the
version used by firmware
- STM32 updates to the firewall bus driver and support for the debug
bus through OP-TEE
- SCMI firmware driver improvements for reliability, in particular
for dealing with broken firmware interrupts
- Memory driver updates for Tegra, and a patch to remove the unused
Baikal T1 driver"
* tag 'soc-drivers-7.1' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (193 commits)
firmware: arm_ffa: Use the correct buffer size during RXTX_MAP
firmware: qcom: scm: Allow QSEECOM on Lenovo IdeaCentre Mini X
clk: spear: fix resource leak in clk_register_vco_pll()
reset: rzv2h-usb2phy: Add support for VBUS mux controller registration
reset: rzv2h-usb2phy: Convert to regmap API
dt-bindings: reset: renesas,rzv2h-usb2phy: Document RZ/G3E USB2PHY reset
dt-bindings: reset: renesas,rzv2h-usb2phy: Add '#mux-state-cells' property
soc: microchip: add mpfs gpio interrupt mux driver
dt-bindings: soc: microchip: document PolarFire SoC's gpio interrupt mux
gpio: mpfs: Add interrupt support
soc: qcom: ubwc: add helpers to get programmable values
soc: qcom: ubwc: add helper to get min_acc length
firmware: qcom: scm: Register gunyah watchdog device
soc: qcom: socinfo: Add SoC ID for SA8650P
dt-bindings: arm: qcom,ids: Add SoC ID for SA8650P
firmware: qcom: scm: Allow QSEECOM on Mahua CRD
soc: qcom: wcnss: simplify allocation of req
soc: qcom: pd-mapper: Add support for Eliza
soc: qcom: aoss: compare against normalized cooling state
soc: qcom: llcc: fix v1 SB syndrome register offset
...
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Benoît Monin
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4434c3896f |
dt-bindings: soc: mobileye: Add EyeQ6Lplus OLB
The "Other Logic Block" found in the EyeQ6Lplus from Mobileye provides various functions for the controllers present in the SoC. The OLB produces 22 clocks derived from its input, which is connected to the main oscillator of the SoC. It provides reset signals via two reset domains. It also controls 32 pins to be either a GPIO or an alternate function. Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Benoît Monin <benoit.monin@bootlin.com> Reviewed-by: Linus Walleij <linusw@kernel.org> Acked-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de> |
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Krzysztof Kozlowski
|
ecaf3a92fb |
RISC-V soc drivers for v7.1
Microchip: Add coverage for the pic64gx in the system controller and syscons. Add a interrupt mux driver (akin to the one that Renesas recently added) that fixes a problem where the platform never properly modelled gpio interrupts. There's a gpio driver change here that Bartosz has acked that adds the interrupt support to the GPIO driver itself. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> -----BEGIN PGP SIGNATURE----- iHUEABYKAB0WIQRh246EGq/8RLhDjO14tDGHoIJi0gUCadOMGgAKCRB4tDGHoIJi 0gXaAP9j6X7ZAL+EOJqiUjQUVslWZUv+hZrKOCv1InnSHDkC5gEAovr3nk6yHjt0 a+4XnUj8AGPbT4bcFEdzeArmH//QtgA= =+V3B -----END PGP SIGNATURE----- Merge tag 'riscv-soc-drivers-for-v7.1' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/conor/linux into soc/drivers RISC-V soc drivers for v7.1 Microchip: Add coverage for the pic64gx in the system controller and syscons. Add a interrupt mux driver (akin to the one that Renesas recently added) that fixes a problem where the platform never properly modelled gpio interrupts. There's a gpio driver change here that Bartosz has acked that adds the interrupt support to the GPIO driver itself. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> * tag 'riscv-soc-drivers-for-v7.1' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/conor/linux: soc: microchip: add mpfs gpio interrupt mux driver dt-bindings: soc: microchip: document PolarFire SoC's gpio interrupt mux gpio: mpfs: Add interrupt support soc: microchip: mpfs-sys-controller: add support for pic64gx dt-bindings: soc: microchip: mpfs-sys-controller: Add pic64gx compatibility dt-bindings: soc: microchip: add compatible for the mss-top-sysreg on pic64gx Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> |
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Théo Lebrun
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7d1b6b7092 |
dt-bindings: soc: mobileye: OLB is an Ethernet PHY provider on EyeQ5
OLB on EyeQ5 ("mobileye,eyeq5-olb" compatible) is now declared as a
generic PHY provider. Under the hood, it provides Ethernet RGMII/SGMII
PHY support for both MAC instances.
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
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Arnd Bergmann
|
a66cc657ef |
Qualcomm driver updates for v7.1
Add ECS LIVA QC710, Glymur CRD, Mahua CRD, Purwa IoT EVK, and Asus Vivobook to the QSEECOM allow-list, to enable UEFI variable access through uefisecapp. Register the Gunyah watchdog device if the SCM driver finds itself running under Gunyah. Clean up some locking using guards. Handle possible cases where AOSS cooling state is given a non-boolean state. Replace LLCC per-slice activation bitmap with reference counting. Also add SDM670 support. Improve probe deferral handling in the OCMEM driver. Add Milos, QCS615, Eliza, Glymur, and Mahua support to the pd-mapper. Add support for SoCCP-based pmic-glink, as found in Glymur and Kaanapali. Add common QMI service ids to the main qmi headerfile, to avoid spreading these constants in various drivers. Add support for version 2 of SMP2P and implement the irqchip state reading support. Add CQ7790, SA8650P, SM7450, SM7450P, and IPQ5210 SoC and the PM7550BA PMIC identifiers to the socinfo driver. Add Eliza and Mahua support to the UBWC driver, introduce helpers for drivers to read out min_acc length and other programmable values, and disable bank swizzling for Glymur. Simplify the logic related to allocation of NV download request in the WCNSS control driver. -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEBd4DzF816k8JZtUlCx85Pw2ZrcUFAmnMQNQACgkQCx85Pw2Z rcWpmA//QDo8m9t4GgAdqJLSyH40Hcw0Uotv4DhzquUe1hYXTQb4NwNoJ+JZVPvO 70BDuJTOQcnQCKeagW1Zq5ycJtA11khRL9ZWwzJB3fq3UTHI+n0EfHDmshAxz37Y h8x71dWKcI3NnEHWBFglRyYbv/eKFxcc2CFP0HrAB3UOxPClqsOVB5iNNM/JA3Jp eppYK6473VAF89q+q7+F3kEhz2p4sgyI9G2Sm/vFqXV3CLY0WV98FjQAHi1nXuNV pCz4oPkccBAcu7FQffMIydbtoIBPZDoI7pueJ4GlgewkkunuiJew/Rq0GEKnyzsN SqzfnBnbfsbQPOtZTBNY6tDgnSMQV2fMtgyBqkmgnSCs6A1AU6XVPFq4wWDpr6t/ +y9QpA/Jfb1txeHp7xY/9bOAl2/vorZDLp9O8CR828z6Ptg/CGO8Gws/X0g4QWvZ 6+UjRHTB5BnJENjzJGoxhrO59gyASUExoM02b6pQmz4ayw9q1PHGMVdSAPCygrDH r9+yMcTO8kfUAYtliJrygDTDlhwxMDfd2z82BOZGpSbAbR8zfFKKJmIaSQGNHCjl u3G9Kb5L7QlAVBGVcRYaArp1MQWD6oP+IU1W9YMra5cySwt/nXtSsQZRdhoP5Qp6 YO8YMdldkf37DNar/+wrN012yaYSWj/k9x/f0phAn106oq1o8+0= =1zur -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmnO3XkACgkQmmx57+YA GNlXDRAAkXYODhxU+T1AyT5OgDBzKgfVBte2vne+NOuirAX6+4U6v+0lCVx+fs4z kTfeveRoXtWlSSF3Vyv+rw1fZvpUOwZ9Y+u405fgveAxtDUkjzJGsnlrfMGIWD4a Q99WFz9L+kTcaf03uNLhrg9UAx0SpkfQQm2riY+ueHVY/0dOTsNzjv71A9sJrmvq oSEH3xquCOgd8diR3evE+2KhD4yQkzMmVeBuujDhWwIJmY8aSpZFIJIXYL5sRo+V l1bd5EwPH2Ku0bXaKh5mLDS/MvdKk7EPKru7ST0+IVfBXBnZf6KefAqljCvVuR66 RRNDN2kcWU+aoih2vuVI+y3w1XGMX9AbFlviaGZWCY1mL2FTFvWfrQ4vLTz2bRlB 8gFPmxMtVZQxu5hBOxAprnYrValRddYamh8cPQcpu9BGIG/ZIqx8cSOXZsQTiARk 9DPRBQsQmaGXXl1YxbcYibQn1TL3ozmqQn0dhZ2Ojkxv0cyD3ymvdv68QKXPf7dm j2LU6BgNiK5IGZ2VUk5mk3hp5Kc+6qpmMqg7l/HIf1zUULCCFWu6l/IobuaX7ynj b5EU0feXMCJ9B17G1lgdFsZ0oI3RhkROjCi2huklNh1fA/xThwTsZsZQ9NmEKQHw TDCcavPXh64fSVtv4qePd9HV+KcHeBeA18m+6njdqByT36qMeC0= =nCjL -----END PGP SIGNATURE----- Merge tag 'qcom-drivers-for-7.1' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/drivers Qualcomm driver updates for v7.1 Add ECS LIVA QC710, Glymur CRD, Mahua CRD, Purwa IoT EVK, and Asus Vivobook to the QSEECOM allow-list, to enable UEFI variable access through uefisecapp. Register the Gunyah watchdog device if the SCM driver finds itself running under Gunyah. Clean up some locking using guards. Handle possible cases where AOSS cooling state is given a non-boolean state. Replace LLCC per-slice activation bitmap with reference counting. Also add SDM670 support. Improve probe deferral handling in the OCMEM driver. Add Milos, QCS615, Eliza, Glymur, and Mahua support to the pd-mapper. Add support for SoCCP-based pmic-glink, as found in Glymur and Kaanapali. Add common QMI service ids to the main qmi headerfile, to avoid spreading these constants in various drivers. Add support for version 2 of SMP2P and implement the irqchip state reading support. Add CQ7790, SA8650P, SM7450, SM7450P, and IPQ5210 SoC and the PM7550BA PMIC identifiers to the socinfo driver. Add Eliza and Mahua support to the UBWC driver, introduce helpers for drivers to read out min_acc length and other programmable values, and disable bank swizzling for Glymur. Simplify the logic related to allocation of NV download request in the WCNSS control driver. * tag 'qcom-drivers-for-7.1' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (51 commits) soc: qcom: ubwc: add helpers to get programmable values soc: qcom: ubwc: add helper to get min_acc length firmware: qcom: scm: Register gunyah watchdog device soc: qcom: socinfo: Add SoC ID for SA8650P dt-bindings: arm: qcom,ids: Add SoC ID for SA8650P firmware: qcom: scm: Allow QSEECOM on Mahua CRD soc: qcom: wcnss: simplify allocation of req soc: qcom: pd-mapper: Add support for Eliza soc: qcom: aoss: compare against normalized cooling state soc: qcom: llcc: fix v1 SB syndrome register offset dt-bindings: firmware: qcom,scm: Document ipq9650 SCM soc: qcom: ubwc: Add support for Mahua soc: qcom: pd-mapper: Add support for Glymur and Mahua soc: qcom: ubwc: Add configuration Eliza SoC soc: qcom: ubwc: Remove redundant x1e80100_data dt-bindings: firmware: qcom,scm: document Eliza SCM Firmware Interface soc: qcom: ocmem: return -EPROBE_DEFER is ocmem is not available soc: qcom: ocmem: register reasons for probe deferrals soc: qcom: ocmem: make the core clock optional soc: qcom: ubwc: disable bank swizzling for Glymur platform ... Signed-off-by: Arnd Bergmann <arnd@arndb.de> |
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Arnd Bergmann
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fbf57f25f0 |
Reset controller updates for v7.1
* Rework the reset core to support firmware nodes, add more fine grained locking, and use guard() helpers. * Change the reset-gpio driver to use firmware nodes. * Add support for the Cix Sky1 SoC reset controller. * Add support for the RZ/G3E SoC to the reset-rzv2h-usb2phy driver and convert it to regmap. Prepare registering a VBUS mux controller. * Replace use of the deprecated register_restart_handler() function in the ath79, intel-gw, lpc18xx, ma35d1, npcm, and sunplus reset drivers. * Combine two allocations into one in the sti/reset-syscfg driver. * Fix the reset-rzg2l-usbphy-ctrl MODULE_AUTHOR email. * Fix the reset_control_rearm() kerneldoc comment. The last commit is a merge of reset-fixes-for-v7.0-2 into reset/next, to solve a merge conflict between commits |
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Arnd Bergmann
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62513d2213 |
i.MX dt-bindings update for 7.1:
- New board support: Verdin iMX95, MBa93xxLA-MINI, TQMa95xxLA, S32N79 SoC/RDB, i.MX8MP audio board (version 2), SolidRun i.MX8M, TQMa8x, GOcontroll Moduline IV/Mini, FRDM-IMX91S, Variscite DART-MX91, i.MX93 Wireless EVK, Variscite DART-MX95. - fsl,irqsteer add nxp,s32n79-irqsteer support. - fsl,imx93-media-blk-ctrl add dbi-bridge. -----BEGIN PGP SIGNATURE----- iQHFBAABCgAvFiEEJS45w2QNr0ezLVaoNF3oRQ23YkwFAmnFXEURHGZyYW5rLmxp QG54cC5jb20ACgkQNF3oRQ23Ykwingv/b0JC877LuSiwreC39fP67SBWGPvaos1b q70gQ+nx9EY34ITpMmuwBVCCFUYtqgDQdpwLHzw6WOF5YcGfr7h7gjQZ4+Rt+5J3 KLP6SBlQubNSArzBC2umXUlvxoyqkOqLEwA0LukxIjkPU1D6hdYg3rHm0P3jSNpY GG8omjXXL8VBQZXR/faVSy9RIaNSI0iTvoTavFmmyXgF5aFEOquIaPBdO8Io8JGU x9EHrG3vecR3XSit9c6y6sb2T7bFfp8m1x2+y9Jwmmzl/05gwRBnifVe1KAIRnrb XKBbt8TrvZJa0K/t6/r0JIj/H4wWNw0J0CejwaUbiW4BszVgfhXi8n+T7Ld53xf9 BktA2oCFHqqpsJ+A4RZ/BmnD6bb+nd/1SZxDVnO+eXM1/XC+cDtXQsZ9RopwVmRU bf/6X7bnbITinT6MlO5QHoAgqqh6cS+roRw63mV5g1AcKTMZkj54qheNFxOCRb29 LugZSq6NInLuOn2ftx45SZjP+OPhC/ur =tZ7p -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmnO3CcACgkQmmx57+YA GNkIkBAAkYWfBOZ5wlSWOPxY0Bx79JCBVB9dC45C+Lcw2Sl8oHHH89wRSSR0BQr+ 83X4W+mNum5RWHQgDEyWkvllFZHZ0RFgstk31P7wCaYsSEq7VIHpb76NEGQDfGOB XSvIK7QgQoS38rE9JPXnJZNPjnYmn624Eev99Ykpx1o0uPBppMBDws36OX3m/WaI ObOuS7IQTIZ0wE+1dx3pwHZLt7qiYzX3rpoLZBI2wXc1Sr+RIGcbTXx6gFErk42U 9ID6ovSDrxTOxAVZtFBCuHWKklB5H9fVPbcCJvCOdDEw4q4itxc4EJXWMvvRqsK7 Sddc+zoL+g/zzgCICgWZLuK54wWDR8r39a3gGXNZgh/3FH7SkbA7+ujGImz2GGQM todKDj19HcRdcRDGYq3O6KjgbZ1vL4FvUgMv/Z3yakoMQ4BMI2X3ZsJFVm4YtEHz M3P2VKQiwSR+x0ZLml4PXQepwEkbWErUEzspeSOM98e8a23SkHdt91wbWWaii/RL cMS0BlQAauisEWpNhFNIwuTsQJPc9EnGqfQQMW3MJOImjjGjALWwvWsVDHEJRyja AqJBKYnHhFzGzAAj6xY667UfL9bjICdqg1GUBSqkt47RJZiwZ9a5kYKT4fWqQYuk MfJgEBpQH6NqjnRzwVgcmT5clEx1LYJJRn1aly28EfJb3RccYCw= =xuzA -----END PGP SIGNATURE----- Merge tag 'imx-bindings-7.1' of git://git.kernel.org/pub/scm/linux/kernel/git/frank.li/linux into soc/drivers i.MX dt-bindings update for 7.1: - New board support: Verdin iMX95, MBa93xxLA-MINI, TQMa95xxLA, S32N79 SoC/RDB, i.MX8MP audio board (version 2), SolidRun i.MX8M, TQMa8x, GOcontroll Moduline IV/Mini, FRDM-IMX91S, Variscite DART-MX91, i.MX93 Wireless EVK, Variscite DART-MX95. - fsl,irqsteer add nxp,s32n79-irqsteer support. - fsl,imx93-media-blk-ctrl add dbi-bridge. * tag 'imx-bindings-7.1' of git://git.kernel.org/pub/scm/linux/kernel/git/frank.li/linux: dt-bindings: arm: fsl: add Verdin iMX95 dt-bindings: arm: fsl: add MBa93xxLA-MINI dt-bindings: arm: add bindings for TQMa95xxLA dt-bindings: arm: lpc: add missed lpc43xx board dt-bindings: arm: fsl: Add NXP S32N79 SoC and RDB board dt-bindings: interrupt-controller: fsl,irqsteer: add S32N79 support dt-bindings: arm: fsl: Add compatible for i.MX8MP audio board (version 2) dt-bindings: arm: fsl: Add various solidrun i.MX8M boards dt-bindings: arm: fsl: add bindings for TQMa8x dt-bindings: fsl: imx7ulp-smc1: Add #clock-cells property dt-bindings: arm: fsl: Add GOcontroll Moduline IV/Mini dt-bindings: arm: fsl: Add FRDM-IMX91S board dt-bindings: arm: fsl: add Variscite DART-MX91 Boards dt-bindings: arm: fsl: Add i.MX93 Wireless EVK board dt-bindings: arm: fsl: add Variscite DART-MX95 Boards dt-bindings: soc: imx93-media-blk-ctrl: Add PDFC subnode to schema and example Signed-off-by: Arnd Bergmann <arnd@arndb.de> |
||
|
Conor Dooley
|
5f3575cc73 |
dt-bindings: soc: microchip: document PolarFire SoC's gpio interrupt mux
On PolarFire SoC there are more GPIO interrupts than there are interrupt lines available on the PLIC, and a runtime configurable mux is used to decide which interrupts are assigned direct connections to the PLIC & which are relegated to sharing a line. Reviewed-by: Herve Codina <herve.codina@bootlin.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Reviewed-by: Linus Walleij <linusw@kernel.org> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> |
||
|
Fabio Estevam
|
25c2721f18 |
dt-bindings: soc: rockchip: grf: Add RV1103B compatibles
Add the PMU GRF and IOC compatible strings for the RV1103B SoC. Signed-off-by: Fabio Estevam <festevam@nabladev.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://patch.msgid.link/20260313131058.708361-1-festevam@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de> |
||
|
Gary Yang
|
c76350e7ad |
dt-bindings: soc: cix: document the syscon on Sky1 SoC
There are two system control on Cix sky1 Soc. One is located in S0 domain, and the other is located in S5 domain. The system control contains resets, usb typeC and more. At this point, only the reset controller is embedded as usb typeC uses it by phandle. Signed-off-by: Gary Yang <gary.yang@cixtech.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> |
||
|
Biju Das
|
3ac4e6b92f |
dt-bindings: soc: renesas: renesas,rzg2l-sysc: Document RZ/G3L SoC
Document RZ/G3L (R9A08G046) SYSC bindings. The SYSC block found on the RZ/G3L SoC is similar to the one found on RZ/G3S. Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260203103031.247435-4-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> |
||
|
Biju Das
|
56c828dff9 |
dt-bindings: soc: renesas: Document RZ/G3L SoC variants, SMARC SoM and Carrier-II EVK
Document Renesas RZ/G3L (R9A08G046) SoC variants and the Renesas RZ/G3L SMARC Carrier-II EVK board which is based on the Renesas RZ/G3L SMARC SoM. The RZ/G3L SMARC Carrier-II EVK consists of an RZ/G3L SoM module and a SMARC Carrier-II carrier board. The SoM module sits on top of the carrier board. Reviewed-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260203103031.247435-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> |
||
|
Pierre-Henry Moussay
|
ecc09da7ba |
dt-bindings: soc: microchip: mpfs-sys-controller: Add pic64gx compatibility
pic64gx is not compatible with mpfs because due to the lack of FPGA functionality some features are disabled. Notably, anything to do with FPGA fabric contents is not supported. Signed-off-by: Pierre-Henry Moussay <pierre-henry.moussay@microchip.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> |
||
|
Conor Dooley
|
7a58baed88 |
dt-bindings: soc: microchip: add compatible for the mss-top-sysreg on pic64gx
pic64gx has an identical sysreg syscon to mpfs, add it using a fallback. Acked-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> |
||
|
Liu Ying
|
3feaa43426 |
dt-bindings: soc: imx93-media-blk-ctrl: Add PDFC subnode to schema and example
i.MX93 SoC mediamix blk-ctrl contains one DISPLAY_MUX register which configures parallel display format by using the "PARALLEL_DISP_FORMAT" field. Document the Parallel Display Format Configuration(PDFC) subnode and add the subnode to example. [m.felsch@pengutronix.de: add bus-width] Signed-off-by: Liu Ying <victor.liu@nxp.com> [m.felsch@pengutronix.de: port to v6.18-rc1] Signed-off-by: Marco Felsch <m.felsch@pengutronix.de> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Frank Li <Frank.Li@nxp.com> |
||
|
Anjelique Melendez
|
aed7440146 |
dt-bindings: soc: qcom: qcom,pmic-glink: Add Glymur and Kaanapali compatibles
Glymur (a recent compute platform) and Kaanapali (a recent mobile platform) have the charger FW running on a new subsystem SOCCP (SOC Control Processor) instead of on ADSP like in previous platforms. Because of this, pmic_glink interface on Glymur and Kaanapali platforms are not compatible with previous platforms. Hence, add new compatible strings for Glymur and Kaanapali. Signed-off-by: Anjelique Melendez <anjelique.melendez@oss.qualcomm.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260209204915.1983997-2-anjelique.melendez@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org> |
||
|
Linus Torvalds
|
46a1daac56 |
Pin control changes for the v7.0 kernel cycle:
Core changes:
- Drop the unused devm_pinctrl_unregister() function.
- Move pretended generic pin control functionality out of the
core and into the Amlogic AM4 driver. We have something better
coming (hopefully).
New hardware support:
- Spacemit K3 (RISC-V) pin control support.
- Atmel AT91 PIO4 (ARM32) SAMA7D65 pin control support.
- Exynos9610 (ARM64) pin control support.
- Qualcomm Mahua TLMM (ARM64) pin control support.
- Microchip Polarfire MSSIO (RISC-V) pin control support.
- Ocelot LAN9645XF (multiplatform) pin control support.
Improvements:
- Using a few more guards for locking.
- Various nonurgent fixes and tweaks.
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Merge tag 'pinctrl-v7.0-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pin control updates from Linus Walleij:
"Core changes:
- Drop the unused devm_pinctrl_unregister() function
- Move pretended generic pin control functionality out of the core
and into the Amlogic AM4 driver. We have something better coming
(hopefully)
New hardware support:
- Spacemit K3 (RISC-V) pin control support
- Atmel AT91 PIO4 (ARM32) SAMA7D65 pin control support
- Exynos9610 (ARM64) pin control support
- Qualcomm Mahua TLMM (ARM64) pin control support
- Microchip Polarfire MSSIO (RISC-V) pin control support
- Ocelot LAN9645XF (multiplatform) pin control support
Improvements:
- Using a few more guards for locking
- Various nonurgent fixes and tweaks"
* tag 'pinctrl-v7.0-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (73 commits)
pinctrl: generic: move function to amlogic-am4 driver
pinctrl: intel: Align Copyright note with corporate guidelines
pinctrl: mediatek: remove unused drv_offset field
pinctrl: canaan: k230: Fix NULL pointer dereference when parsing devicetree
pinctrl: single: fix refcount leak in pcs_add_gpio_func()
pinctrl: meson: amlogic-a4: Fix device node reference leak in bank helpers
pinctrl: qcom: sm8250-lpass-lpi: Fix i2s2_data_groups definition
pinctrl: core: Remove duplicate error messages
pinctrl: core: Simplify devm_pinctrl_*()
pinctrl: core: Remove unused devm_pinctrl_unregister()
dt-bindings: pinctrl: spacemit: fix drive-strength check warning
pinctrl: fix kismet issues with GENERIC_PINCTRL
pinctrl: tangier: Join tng_pinctrl_probe() into its wrapper
pinctrl: tangier: Remove duplicate error messages
pinctrl: lynxpoint: Remove duplicate error messages
pinctrl: cherryview: Remove duplicate error messages
pinctrl: baytrail: Remove duplicate error messages
pinctrl: intel: Remove duplicate error messages
pinctrl: equilibrium: Fix device node reference leak in pinbank_init()
dt-bindings: pinctrl: pinctrl-microchip-sgpio: add LAN969x
...
|
||
|
Linus Torvalds
|
13c916af3a |
Not much changed in the clk framework this time except the clk.h consumer API
moved the context saving APIs around to fix a build error in certain
configurations. There was a change to the core framework for
CLK_OPS_PARENT_ENABLE behavior during registration, but it wrecked existing
drivers that didn't expect things to be turned off during clk registration so
it got reverted.
This cycle is really a large collection of new clk drivers, primarily for
Qualcomm SoCs but also for Amlogic, SpacemiT, Google, and Aspeed. Another big
change in here is support for automatic hardware clock gating on Samsung SoCs
where the clks turn on and off when needed. Ideally more vendors move to this
method for better power savings. The highlights are in the updates section
below.
Beyond all the new drivers we have a bunch of cleanups like converting drivers
from divider_round_rate() to divider_determine_rate() and using scoped for each
OF child loops. Otherwise it's the usual data fixes and plugging reference
leaks, etc. that's all pretty ordinary but not critical enough to fix until the
next release.
New Drivers:
- Qualcomm Kaanapali global, tcsr, rpmh, display, gpu, camera, and video clk
controllers
- Qualcomm SM8750 camera clk controllers
- Qualcomm MSM8940 and SDM439 global clk controllers
- Google GS101 Display Process Unit (DPU) clk controllers
- SpacemiT K3 clk controllers
- Amlogic t7 clk controllers
- Aspeed AST2700 clk controllers
Updates:
- Convert clock dividers from round_rate() to determine_rate()
- Fix sparse warnings, kernel-doc warnings, and plug leaked OF refs
- Automatic hardware clk gating on Google GS101 SoCs
- Amlogic s4 video clks
- CAN-FD clks and resets on Renesas RZ/T2H, RZ/N2H, RZ/V2H, and RZ/V2N
- Expanded Serial Peripheral Interface (xSPI) clocks and resets on Renesas
RZ/T21H and RZ/N2H
- DMAC, interrupt controller (ICU), SPI, and thermal (TSU) clocks and resets
on Renesas RZ/V2N
- More serial (RSCI) clocks and resets on Renesas RZ/V2H and RZ/V2N
- CPU frequency scaling on T-HEAD TH1520
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Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk updates from Stephen Boyd:
"Not much changed in the clk framework this time except the clk.h
consumer API moved the context saving APIs around to fix a build error
in certain configurations.
There was a change to the core framework for CLK_OPS_PARENT_ENABLE
behavior during registration, but it wrecked existing drivers that
didn't expect things to be turned off during clk registration so it
got reverted.
This cycle is really a large collection of new clk drivers, primarily
for Qualcomm SoCs but also for Amlogic, SpacemiT, Google, and Aspeed.
Another big change in here is support for automatic hardware clock
gating on Samsung SoCs where the clks turn on and off when needed.
Ideally more vendors move to this method for better power savings. The
highlights are in the updates section below.
Beyond all the new drivers we have a bunch of cleanups like converting
drivers from divider_round_rate() to divider_determine_rate() and
using scoped for each OF child loops. Otherwise it's the usual data
fixes and plugging reference leaks, etc. that's all pretty ordinary
but not critical enough to fix until the next release.
New Drivers:
- Qualcomm Kaanapali global, tcsr, rpmh, display, gpu, camera, and
video clk controllers
- Qualcomm SM8750 camera clk controllers
- Qualcomm MSM8940 and SDM439 global clk controllers
- Google GS101 Display Process Unit (DPU) clk controllers
- SpacemiT K3 clk controllers
- Amlogic t7 clk controllers
- Aspeed AST2700 clk controllers
Updates:
- Convert clock dividers from round_rate() to determine_rate()
- Fix sparse warnings, kernel-doc warnings, and plug leaked OF refs
- Automatic hardware clk gating on Google GS101 SoCs
- Amlogic s4 video clks
- CAN-FD clks and resets on Renesas RZ/T2H, RZ/N2H, RZ/V2H, and
RZ/V2N
- Expanded Serial Peripheral Interface (xSPI) clocks and resets on
Renesas RZ/T21H and RZ/N2H
- DMAC, interrupt controller (ICU), SPI, and thermal (TSU) clocks and
resets on Renesas RZ/V2N
- More serial (RSCI) clocks and resets on Renesas RZ/V2H and RZ/V2N
- CPU frequency scaling on T-HEAD TH1520"
* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (165 commits)
clk: aspeed: Add reset for HACE/VIDEO
dt-bindings: clock: aspeed: Add VIDEO reset definition
clk: aspeed: add AST2700 clock driver
MAINTAINERS: Add entry for ASPEED clock drivers.
clk: aspeed: Move the existing ASPEED clk drivers into aspeed subdirectory.
Revert "clk: Respect CLK_OPS_PARENT_ENABLE during recalc"
clk: Disable KUNIT_UML_PCI
dt-bindings: clk: rs9: Fix DIF pattern match
clk: rs9: Convert to DEFINE_SIMPLE_DEV_PM_OPS()
clk: rs9: Reserve 8 struct clk_hw slots for for 9FGV0841
clk: qcom: sm8750: Constify 'qcom_cc_desc' in SM8750 camcc
clk: zynqmp: pll: Fix zynqmp_clk_divider_determine_rate kerneldoc
clk: zynqmp: divider: Fix zynqmp_clk_divider_determine_rate kerneldoc
clk: mediatek: Fix error handling in runtime PM setup
clk: mediatek: don't select clk-mt8192 for all ARM64 builds
clk: mediatek: Add mfg_eb as parent to mt8196 mfgpll clocks
clk: mediatek: Refactor pllfh registration to pass device
clk: mediatek: Pass device to clk_hw_register for PLLs
clk: mediatek: Refactor pll registration to pass device
clk: Respect CLK_OPS_PARENT_ENABLE during recalc
...
|
||
|
Stephen Boyd
|
b675697d80
|
Merge branches 'clk-amlogic', 'clk-thead', 'clk-mediatek' and 'clk-samsung' into clk-next
* clk-amlogic: clk: meson: gxbb: use the existing HHI_HDMI_PLL_CNTL3 macro clk: meson: g12a: Limit the HDMI PLL OD to /4 clk: meson: gxbb: Limit the HDMI PLL OD to /4 on GXL/GXM SoCs clk: amlogic: remove potentially unsafe flags from S4 video clocks clk: amlogic: add video-related clocks for S4 SoC dt-bindings: clock: add video clock indices for Amlogic S4 SoC clk: meson: t7: add t7 clock peripherals controller driver clk: meson: t7: add support for the T7 SoC PLL clock dt-bindings: clock: add Amlogic T7 peripherals clock controller dt-bindings: clock: add Amlogic T7 SCMI clock controller dt-bindings: clock: add Amlogic T7 PLL clock controller * clk-thead: clk: thead: th1520-ap: Support CPU frequency scaling clk: thead: th1520-ap: Add macro to define multiplexers with flags clk: thead: th1520-ap: Support setting PLL rates clk: thead: th1520-ap: Add C910 bus clock clk: thead: th1520-ap: Poll for PLL lock and wait for stability dt-bindings: clock: thead,th1520-clk-ap: Add ID for C910 bus clock * clk-mediatek: Revert "clk: Respect CLK_OPS_PARENT_ENABLE during recalc" clk: mediatek: Fix error handling in runtime PM setup clk: mediatek: don't select clk-mt8192 for all ARM64 builds clk: mediatek: Add mfg_eb as parent to mt8196 mfgpll clocks clk: mediatek: Refactor pllfh registration to pass device clk: mediatek: Pass device to clk_hw_register for PLLs clk: mediatek: Refactor pll registration to pass device clk: Respect CLK_OPS_PARENT_ENABLE during recalc dt-bindings: clock: mediatek,mt7622-pciesys: Remove syscon compatible clk: mediatek: Drop __initconst from gates * clk-samsung: clk: samsung: gs101: add support for Display Process Unit (DPU) clocks dt-bindings: samsung: exynos-sysreg: add gs101 dpu compatible dt-bindings: clock: google,gs101-clock: Add DPU clock management unit dt-bindings: clock: google,gs101-clock: fix alphanumeric ordering clk: samsung: fix sysreg save/restore when PM is enabled for CMU clk: samsung: avoid warning message on legacy Exynos (auto clock gating) clk: samsung: gs101: Enable auto_clock_gate mode for each gs101 CMU clk: samsung: Implement automatic clock gating mode for CMUs dt-bindings: clock: google,gs101-clock: add samsung,sysreg property as required clk: samsung: exynosautov920: add clock support dt-bindings: clock: exynosautov920: add MFD clock definitions |
||
|
Linus Torvalds
|
6589b3d76d |
soc: devicetree updates for 7.0
There are a handful of new SoCs this time, all of these are
more or less related to chips in a wider family:
- SpacemiT Key Stone K3 is an 8-core risc-v chip, and the first
widely available RVA23 implementation. Note that this is
entirely unrelated with the similarly named Texas Instruments
K3 chip family that follwed the TI Keystone2 SoC.
- The Realtek Kent family of SoCs contains three chip models
rtd1501s, rtd1861b and rtd1920s, and is related to their earlier
Set-top-box and NAS products such as rtd1619, but is built
on newer Arm Cortex-A78 cores.
- The Qualcomm Milos family includes the Snapdragon 7s Gen 3
(SM7635) mobile phone SoC built around Armv9 Kryo cores of the Arm
Cortex-A720 generation. This one is used in the Fairphone Gen 6
- Qualcomm Kaanapali is a new SoC based around eight high
performance Oryon CPU cores
- NXP i.MX8QP and i.MX952 are both feature reduced versions of
chips we already support, i.e. the i.MX8QM and i.MX952, with
fewer CPU cores and I/O interfaces.
As part of a cleanup, a number of SoC specific devicetree files got
removed because they did not have a single board using the .dtsi files
and they were never compile tested as a result: Samsung s3c6400,
ST spear320s, ST stm32mp21xc/stm32mp23xc/stm32mp25xc, Renesas
r8a779m0/r8a779m2/r8a779m4/r8a779m6/r8a779m7/r8a779m8/r8a779mb/
r9a07g044c1/r9a07g044l1/r9a07g054l1/r9a09g047e37, and TI am3703/am3715.
All of these could be restored easily if a new board gets merged.
Broadcom/Cavium/Marvell ThunderX2 gets removed along with its only
machine, as all remaining users are assumed to be using ACPI
based firmware.
A relatively small number of 43 boards get added this time, and
almost all of them for arm64. Aside from the reference boards for
the newly added SoCs, this includes:
- Three server boards use 32-bit ASpeed BMCs
- One more reference board for 32-bit Microchip LAN9668
- 64-bit Arm single-board computers based on Amlogic s905y4,
CIX sky1, NXP ls1028a/imx8mn/imx8mp/imx91/imx93/imx95,
Qualcomm qcs6490/qrb2210 and Rockchip rk3568/rk3588s
- Carrier board for SOMs using Intel agilex5, Marvell Armada 7020,
NXP iMX8QP, Mediatek mt8370/mt8390 and rockchip rk3588
- Two mobile phones using Snapdragon 845
- A gaming device and a NAS box, both based on Rockchips rk356x
On top of the newly added boards and SoCs, there is a lot of
background activity going into cleanups, in particular towards
getting a warning-free dtc build, and the usual work on adding
support for more hardware on the previously added machines.
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Merge tag 'soc-dt-7.0' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull SoC devicetree updates from Arnd Bergmann:
"There are a handful of new SoCs this time, all of these are more or
less related to chips in a wider family:
- SpacemiT Key Stone K3 is an 8-core risc-v chip, and the first
widely available RVA23 implementation. Note that this is entirely
unrelated with the similarly named Texas Instruments K3 chip family
that follwed the TI Keystone2 SoC.
- The Realtek Kent family of SoCs contains three chip models
rtd1501s, rtd1861b and rtd1920s, and is related to their earlier
Set-top-box and NAS products such as rtd1619, but is built on newer
Arm Cortex-A78 cores.
- The Qualcomm Milos family includes the Snapdragon 7s Gen 3 (SM7635)
mobile phone SoC built around Armv9 Kryo cores of the Arm
Cortex-A720 generation. This one is used in the Fairphone Gen 6
- Qualcomm Kaanapali is a new SoC based around eight high performance
Oryon CPU cores
- NXP i.MX8QP and i.MX952 are both feature reduced versions of chips
we already support, i.e. the i.MX8QM and i.MX952, with fewer CPU
cores and I/O interfaces.
As part of a cleanup, a number of SoC specific devicetree files got
removed because they did not have a single board using the .dtsi files
and they were never compile tested as a result: Samsung s3c6400, ST
spear320s, ST stm32mp21xc/stm32mp23xc/stm32mp25xc, Renesas
r8a779m0/r8a779m2/r8a779m4/r8a779m6/r8a779m7/r8a779m8/r8a779mb/
r9a07g044c1/r9a07g044l1/r9a07g054l1/r9a09g047e37, and TI
am3703/am3715. All of these could be restored easily if a new board
gets merged.
Broadcom/Cavium/Marvell ThunderX2 gets removed along with its only
machine, as all remaining users are assumed to be using ACPI based
firmware.
A relatively small number of 43 boards get added this time, and almost
all of them for arm64. Aside from the reference boards for the newly
added SoCs, this includes:
- Three server boards use 32-bit ASpeed BMCs
- One more reference board for 32-bit Microchip LAN9668
- 64-bit Arm single-board computers based on Amlogic s905y4, CIX
sky1, NXP ls1028a/imx8mn/imx8mp/imx91/imx93/imx95, Qualcomm
qcs6490/qrb2210 and Rockchip rk3568/rk3588s
- Carrier board for SOMs using Intel agilex5, Marvell Armada 7020,
NXP iMX8QP, Mediatek mt8370/mt8390 and rockchip rk3588
- Two mobile phones using Snapdragon 845
- A gaming device and a NAS box, both based on Rockchips rk356x
On top of the newly added boards and SoCs, there is a lot of
background activity going into cleanups, in particular towards getting
a warning-free dtc build, and the usual work on adding support for
more hardware on the previously added machines"
* tag 'soc-dt-7.0' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (757 commits)
dt-bindings: intel: Add Agilex eMMC support
arm64: dts: socfpga: agilex: add emmc support
arm64: dts: intel: agilex5: Add simple-bus node on top of dma controller node
ARM: dts: socfpga: fix dtbs_check warning for fpga-region
ARM: dts: socfpga: add #address-cells and #size-cells for sram node
dt-bindings: altera: document syscon as fallback for sys-mgr
arm64: dts: altera: Use lowercase hex
dt-bindings: arm: altera: combine Intel's SoCFPGA into altera.yaml
arm64: dts: socfpga: agilex5: Add IOMMUS property for ethernet nodes
arm64: dts: socfpga: agilex5: add support for modular board
dt-bindings: intel: Add Agilex5 SoCFPGA modular board
arm64: dts: socfpga: agilex5: Add dma-coherent property
arm64: dts: realtek: Add Kent SoC and EVB device trees
dt-bindings: arm: realtek: Add Kent Soc family compatibles
ARM: dts: samsung: Drop s3c6400.dtsi
ARM: dts: nuvoton: Minor whitespace cleanup
MAINTAINERS: Add Falcon DB
arm64: dts: a7k: add COM Express boards
ARM: dts: microchip: Drop usb_a9g20-dab-mmx.dtsi
arm64: dts: rockchip: Fix rk3588 PCIe range mappings
...
|
||
|
Arnd Bergmann
|
f51d34065d |
SoCFPGA DTS updates for v6.20, version 3
- dt-bindings updates: - Add intel,socfpga-agilex5-socdk-modular for the Agilex5 mod board - Add intel,socfpga-agilex-emmc for the Agilex eMMC daughter board - Move entries in intel,socfpga.yaml into altera.yaml - Add syscon as a fallback for sys-mgr - Add dma-cohrerent property for Agilex5 NAND and DMA - Add support for the Agilex5 modular board - Add IOMMUS property for ethernet nodes for Agilex5 - Use lowercase hex for dts files - Add #address-cells and #size-cells for sram - Fix dtbs_check warning for fpga-region - Move dma controller node for Agilex5 under simple-bus - Add support for the Agilex eMMC daughter board -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEoHhMeiyk5VmwVMwNGZQEC4GjKPQFAmmBaFYACgkQGZQEC4Gj KPQLjxAAovoapeOuk0Ps+O31v9NCzuRfIwvGC1YryL4+REqU6PIJxEV7rJKL9bxy HePefbDgOtuukwqcy/IF/rN8av3ETqbRif4c0Gdt6vzOJ5TRCwdbVctLJQlchG/h CCv86QiDNt5VmCXJ8aONNcuUl1RmKRgScv5teeL4bPFhOwXfPYsjR6n7AexwDfCm qFw3b8xR1Qo4kQrn8NQwa5aJ/YrC9zeMgJMN8Yd8Zqe07MzLRCPlKioPi04zG9Gz Sd4NFLzBNW3PNwZxjQjGaZ99f5MDRMMrIFDUFN6qyyKpF0u+z8jboZ0KfuE8AWSH SpRp2MD5wdCv2jfynfvaHYZJCbf2yO9KUwI0BTNbfZK2PB/Kjbh1NtfuyTzU1CyS 26RumUjItmEW0DHiHxHWEIqUQH18LPX95+aiX3HDEg4DC8AcYDqER6udzIEVvb0f z1XftA5uwy59tzgFLear/UV+u0kq8H3ndBHvsrSsCuXiekXEz3N9JddRmZrDve6Y 5PorxK0CA9SiMIknTwPgR+C1WEhdw0CBJsjz1jWijqw8ZIHB70MpU7Tk4j1qJlbL 7GpOQySIy5qcg2m9SS7yvCWtBt8xdtbj9cR8UnEEuJKzTnahxHcfYnontuUbYyJd zSQ0JKndpwb4QCmOAYswsp4WVOGfnVCPia4Eu4L94BRN16hv+to= =ux17 -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmmC954ACgkQmmx57+YA GNl1Hw/+KMtxRTV2Gy8jUIJmWl3G1OXJ2n9HDyo+fSH9c9IqyU3RcLxWqQlENaz7 MCxRIozKbjSvwNOgx7wkbmxY5oyEnZ0hqr0ylsn/wctBTCghaqID6IZd+5fdigS9 1VqFeVB+i5GvihJ1mJDEHaUAjfahc9JA30da+oAqBkAsT89MkAn6Iaaze44tIlu1 7i2EFzaMB7Gb5WXZ340x1rDM/u6cjR9iEYSXqSjmj+upy5xYuINzWDRN/1ZFtkTh 44xoOoZ+rH7wnLYzx0gWoEcH+RA7yDbicaqJ4l+u1lbUNAsz46WfXbdys/kGKE8F Us6gXbLlZ+ZDGxB3dEqsOvxfI3u2u1Ehz69b+nZxNf2Fh5NDBSjkzcu30BywMgpj NPY/XqK9DA6G7M405rYaIJQMSiDqevZnBS35/jtq3t5pYmkuKUvwG6/8XexrOq00 FXGX7JS8nEm8U3DFjwT6Z+Hg4Psm/nZxsv6KiarvJWDuhUeJRJM0qY2IF1dAYi1g LONh1Lt/WNHqDyF8bWkP6cT7zCGZ5Tlozj+3V/oyPNi6VndA6sNzIi9L/oR3oHOD vBGnEr95QaxZ/FaqNvMJo54DNBR3NEscDe3rAi+B4WaAH04EtSKMOwaY3pN9edwj H0hnbWU0bYsCfWDTbS698+lxTD/zCsBTEoWSFo0iL8mus0ArIgw= =XO7t -----END PGP SIGNATURE----- Merge tag 'socfpga_dts_updates_for_v6.20_v3' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux into soc/dt SoCFPGA DTS updates for v6.20, version 3 - dt-bindings updates: - Add intel,socfpga-agilex5-socdk-modular for the Agilex5 mod board - Add intel,socfpga-agilex-emmc for the Agilex eMMC daughter board - Move entries in intel,socfpga.yaml into altera.yaml - Add syscon as a fallback for sys-mgr - Add dma-cohrerent property for Agilex5 NAND and DMA - Add support for the Agilex5 modular board - Add IOMMUS property for ethernet nodes for Agilex5 - Use lowercase hex for dts files - Add #address-cells and #size-cells for sram - Fix dtbs_check warning for fpga-region - Move dma controller node for Agilex5 under simple-bus - Add support for the Agilex eMMC daughter board * tag 'socfpga_dts_updates_for_v6.20_v3' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux: dt-bindings: intel: Add Agilex eMMC support arm64: dts: socfpga: agilex: add emmc support arm64: dts: intel: agilex5: Add simple-bus node on top of dma controller node ARM: dts: socfpga: fix dtbs_check warning for fpga-region ARM: dts: socfpga: add #address-cells and #size-cells for sram node dt-bindings: altera: document syscon as fallback for sys-mgr arm64: dts: altera: Use lowercase hex dt-bindings: arm: altera: combine Intel's SoCFPGA into altera.yaml arm64: dts: socfpga: agilex5: Add IOMMUS property for ethernet nodes arm64: dts: socfpga: agilex5: add support for modular board dt-bindings: intel: Add Agilex5 SoCFPGA modular board arm64: dts: socfpga: agilex5: Add dma-coherent property Signed-off-by: Arnd Bergmann <arnd@arndb.de> |
||
|
Dinh Nguyen
|
42918d28cb |
dt-bindings: altera: document syscon as fallback for sys-mgr
For 32-bit Altera SoCFPGA parts, the sys-mgr uses the syscon as a fallback. This change addresses this warning from dtbs_check: sysmgr@ffd08000 (altr,sys-mgr): compatible: 'oneOf' conditional failed, one must be fixed: ['altr,sys-mgr', 'syscon'] is too long 'altr,sys-mgr-s10' was expected 'altr,sys-mgr' was expected from schema $id: http://devicetree.org/schemas/soc/altera/altr,sys-mgr.yaml Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> |
||
|
Arnd Bergmann
|
a393bda150 |
Reset controller updates for v6.20
* Add a compatible to the reset-gpio driver, suppress the sysfs bind attributes, and propagate GPIO API errors. * Add support for the i.MX8ULP SIM LPAV reset controller. * Add RZ/G3S USBPHY suspend/resume support. * Enable reset-k230 by default on ARCH_CANAAN * Add support for the SpacemiT K3 SoC reset controller. * Merge the 'spacemit-clkrst-v6.20-3' tag, shared with the clk tree, as a dependency for the SpacemiT changes. -----BEGIN PGP SIGNATURE----- iI0EABYKADUWIQRRO6F6WdpH1R0vGibVhaclGDdiwAUCaXiRShcccC56YWJlbEBw ZW5ndXRyb25peC5kZQAKCRDVhaclGDdiwDWkAP0foLlNQzqjNj7uT6ysYoHwbixE +F9iaLCqJ9SAS5ajcwEAvJdJOJJCHGLR/4ImjH4AdCC1RqENUPYTqivvjZ3ozAU= =Z0D4 -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAml7J0sACgkQmmx57+YA GNnDxhAAn5icxeT8YFUJjKnYCnNx3gOVP9sdSQRc+MOdTwSNen6LdVqaXhYJij2y yqTk138Ulr3NUG84k3p75Rajz6TbMsVY1usuqa+vJqr9ruuPmAIx1xTEI/Hb6HVM 4k2NeSk2osYSx/o0xgOC3qPA8fGAw/sdduFkU69wrWPAfoxg5uK+OQyJ8VJRnhFQ 45WnIZ+Z8AtINhJiq88cowilf762PTEi2t6PRjsI/E5JJplQXYyi2Kpx48nYHmrp Kfl0bmNIM7a7fVOAXd/fdQ7QYex/qhUZzZy1GZh7uo3VSVyjLJuN2ZHkxvmfjIjG x2SyAhfuryvCWiN7GDJcreiPNJOOkBtzjvisCvBQE9OFYSsZd2YRhb2cluK7YUZt mlSPxqqD0Z+Y4/03pXAdLmAiUYqq2ZZeLiO4u6ExwYrHu7lcJlhmSMXdcokiMVwo 1QRRaJiXc5qcr/s/xkKT91Kmy1ncwiulb0Py2WkUaGTPKjPCqvPgHQ2PDZ6za9Eo ilsn6yyuBfn3Dlcat2o59frXDp5/GggHx0gcxq6CrEWUUwchUbvHy0IMfqUNdzo4 dTT2HKwse+GPDfK9Rm8O1UiRGaWMBSW68db2X4KNGeKj3PvakDyAz7CxdCa86E3g HfFQDzTK8bzlSnXCvjH9/q99aqxwAxs171NkveE3nx+NPqxptXc= =P4vq -----END PGP SIGNATURE----- Merge tag 'reset-for-v6.20' of https://git.pengutronix.de/git/pza/linux into soc/drivers Reset controller updates for v6.20 * Add a compatible to the reset-gpio driver, suppress the sysfs bind attributes, and propagate GPIO API errors. * Add support for the i.MX8ULP SIM LPAV reset controller. * Add RZ/G3S USBPHY suspend/resume support. * Enable reset-k230 by default on ARCH_CANAAN * Add support for the SpacemiT K3 SoC reset controller. * Merge the 'spacemit-clkrst-v6.20-3' tag, shared with the clk tree, as a dependency for the SpacemiT changes. * tag 'reset-for-v6.20' of https://git.pengutronix.de/git/pza/linux: reset: spacemit: Add SpacemiT K3 reset driver reset: spacemit: Extract common K1 reset code reset: Create subdirectory for SpacemiT drivers dt-bindings: soc: spacemit: Add K3 reset support and IDs reset: canaan: k230: drop OF dependency and enable by default reset: rzg2l-usbphy-ctrl: Add suspend/resume support reset: rzg2l-usbphy-ctrl: Propagate the return value of regmap_field_update_bits() reset: gpio: check the return value of gpiod_set_value_cansleep() reset: imx8mp-audiomix: Support i.MX8ULP SIM LPAV reset: imx8mp-audiomix: Extend the driver usage reset: imx8mp-audiomix: Switch to using regmap API reset: imx8mp-audiomix: Drop unneeded macros reset: gpio: suppress bind attributes in sysfs clk: spacemit: k3: extract common header reset: spacemit: fix auxiliary device id clk: spacemit: prepare common ccu header reset: gpio: add the "compatible" property Signed-off-by: Arnd Bergmann <arnd@arndb.de> |
||
|
Arnd Bergmann
|
35a53670ea |
MediaTek soc driver updates
This adds:
- A socinfo entry for the MT8371 Genio 520 SoC
- Support for the Dynamic Voltage and Frequency Scaling
Resource Controller (DVFSRC) version 4, found in the
new MediaTek Kompanio Ultra (MT8196) SoC
- Initial support for the CMDQ mailbox found in the MT8196.
- A memory leak fix in the MediaTek SVS driver's debug ops.
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Merge tag 'mtk-soc-for-v6.20' of https://git.kernel.org/pub/scm/linux/kernel/git/mediatek/linux into soc/drivers
MediaTek soc driver updates
This adds:
- A socinfo entry for the MT8371 Genio 520 SoC
- Support for the Dynamic Voltage and Frequency Scaling
Resource Controller (DVFSRC) version 4, found in the
new MediaTek Kompanio Ultra (MT8196) SoC
- Initial support for the CMDQ mailbox found in the MT8196.
- A memory leak fix in the MediaTek SVS driver's debug ops.
* tag 'mtk-soc-for-v6.20' of https://git.kernel.org/pub/scm/linux/kernel/git/mediatek/linux:
soc: mediatek: mtk-cmdq: Add mminfra_offset adjustment for DRAM addresses
soc: mediatek: mtk-cmdq: Extend cmdq_pkt_write API for SoCs without subsys ID
soc: mediatek: mtk-cmdq: Add pa_base parsing for hardware without subsys ID support
soc: mediatek: mtk-cmdq: Add cmdq_get_mbox_priv() in cmdq_pkt_create()
mailbox: mtk-cmdq: Add driver data to support for MT8196
mailbox: mtk-cmdq: Add mminfra_offset configuration for DRAM transaction
mailbox: mtk-cmdq: Add GCE hardware virtualization configuration
mailbox: mtk-cmdq: Add cmdq private data to cmdq_pkt for generating instruction
soc: mediatek: mtk-dvfsrc: Rework bandwidth calculations
soc: mediatek: mtk-dvfsrc: Get and Enable DVFSRC clock
soc: mediatek: mtk-dvfsrc: Add support for DVFSRCv4 and MT8196
soc: mediatek: mtk-dvfsrc: Write bandwidth to EMI DDR if present
soc: mediatek: mtk-dvfsrc: Add a new callback for calc_dram_bw
soc: mediatek: mtk-dvfsrc: Add and propagate DVFSRC bandwidth type
soc: mediatek: mtk-dvfsrc: Change error check for DVFSRCv4 START cmd
dt-bindings: soc: mediatek: dvfsrc: Document clock
soc: mediatek: mtk-socinfo: Add entry for MT8371AV/AZA Genio 520
soc: mediatek: svs: Fix memory leak in svs_enable_debug_write()
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
|
||
|
Arnd Bergmann
|
896cc203af |
Samsung DTS ARM64 changes for v6.20
1. ExynosAutov920:
- Add MFD clock controller node.
2. Google GS101:
- Add True Random Number Generator (TRNG) and OTP nvmem nodes.
- Correct the PMU (Power Management Unit) compatibles by dropping
fallback to syscon. The PMU on Samsung devices serves the role of
syscon, however on GS101 it cannot be used via standard Linux syscon
interface, because register accesses require custom regmap. It was
simply never correctly working with "syscon" compatible fallback.
- Add phandles to System Registers SYSREG blocks in clock controllers,
necessary for enabling automatic clock control later.
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Merge tag 'samsung-dt64-6.20' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into soc/dt
Samsung DTS ARM64 changes for v6.20
1. ExynosAutov920:
- Add MFD clock controller node.
2. Google GS101:
- Add True Random Number Generator (TRNG) and OTP nvmem nodes.
- Correct the PMU (Power Management Unit) compatibles by dropping
fallback to syscon. The PMU on Samsung devices serves the role of
syscon, however on GS101 it cannot be used via standard Linux syscon
interface, because register accesses require custom regmap. It was
simply never correctly working with "syscon" compatible fallback.
- Add phandles to System Registers SYSREG blocks in clock controllers,
necessary for enabling automatic clock control later.
* tag 'samsung-dt64-6.20' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
arm64: dts: exynos: gs101: add OTP node
arm64: dts: exynos: gs101: add samsung,sysreg property to CMU nodes
arm64: dts: exynosautov920: add CMU_MFD clock DT nodes
arm64: dts: exynos: gs101: remove syscon compatible from pmu node
dt-bindings: soc: samsung: exynos-pmu: remove syscon for google,gs101-pmu
arm64: dts: exynos: gs101: add TRNG node
dt-bindings: rng: add google,gs101-trng compatible
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
|
||
|
Guodong Xu
|
216e0a5e98 |
dt-bindings: soc: spacemit: Add K3 reset support and IDs
Update the spacemit,k1-syscon.yaml binding to document K3 SoC reset support. K3 reset devices are registered at runtime as auxiliary devices by the K3 CCU driver. Since K3 reuses the K1 syscon binding, there is no separate YAML binding file for K3 resets. Update #reset-cells description to document where reset IDs are defined. Acked-by: Alex Elder <elder@riscstar.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Guodong Xu <guodong@riscstar.com> Reviewed-by: Yixun Lan <dlan@kernel.org> Link: https://lore.kernel.org/spacemit/20260114092742-GYC7933267@gentoo.org/ [1] Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> |
||
|
Conor Dooley
|
6b324d1994 |
dt-bindings: pinctrl: document polarfire soc mssio pin controller
On Polarfire SoC, the Bank 2 and Bank 4 IOs connected to the Multiprocessor Subsystem (MSS) are controlled by IOMUX_CRs 1 through 6, which determine what function in routed to them, and MSSIO_BANK#_IO_CFG_CRs, which determine the configuration of each pin. Document it, including several custom configuration options that stem from MSS Configurator options (the MSS Configurator is part of the FPGA tooling for this device). "ibufmd" unfortunately is not a 1:1 mapping with an MSS Configurator option, unlike clamp-diode or lockdown, and I do not know the effect of any bits in the field. I have no been able to find an explanation for these bits in documentation. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Linus Walleij <linusw@kernel.org> |
||
|
Peter Griffin
|
1d8fae6617 |
dt-bindings: samsung: exynos-sysreg: add gs101 dpu compatible
Add dedicated compatibles for gs101 dpu sysreg controllers to the documentation. Reviewed-by: André Draszik <andre.draszik@linaro.org> Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Acked-by: Rob Herring (Arm) <robh@kernel.org> Link: https://patch.msgid.link/20260113-dpu-clocks-v3-3-cb85424f2c72@linaro.org Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> |
||
|
Herve Codina (Schneider Electric)
|
f3b795d298 |
dt-bindings: soc: renesas: Document RZ/N1 GPIO Interrupt Multiplexer
On the Renesas RZ/N1 SoC, GPIOs can generate interruptions. Those interruption lines are multiplexed by the GPIO Interrupt Multiplexer in order to map 32 * 3 GPIO interrupt lines to 8 GIC interrupt lines. The GPIO interrupt multiplexer IP does nothing but select 8 GPIO IRQ lines out of the 96 available to wire them to the GIC input lines. Signed-off-by: Herve Codina (Schneider Electric) <herve.codina@bootlin.com> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260114093938.1089936-7-herve.codina@bootlin.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> |
||
|
Yixun Lan
|
efe897b557
|
dt-bindings: soc: spacemit: k3: add clock support
Add compatible strings for clock drivers to support Spacemit K3 SoC, also includes all the defined clock IDs. The SpacemiT K3 SoC clock IP is scattered over several different blocks, which are APBC, APBS, APMU, DCIU, MPMU, all of them are capable of generating clock and reset signals. APMU and MPMU have additional Power Domain management functionality. Following is a brief list that shows devices managed in each block: APBC: UART, GPIO, PWM, SPI, TIMER, I2S, IR, DR, TSEN, IPC, CAN APBS: various PPL clocks control APMU: CCI, CPU, CSI, ISP, LCD, USB, QSPI, DMA, VPU, GPU, DSI, PCIe, EMAC.. DCID: SRAM, DMA, TCM MPMU: various PLL1 derived clocks, UART, WATCHDOG, I2S Link: https://lore.kernel.org/r/20260108-k3-clk-v5-1-42a11b74ad58@gentoo.org Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Yixun Lan <dlan@gentoo.org> |
||
|
Nicolas Frattaroli
|
831ee17036
|
dt-bindings: soc: mediatek: dvfsrc: Document clock
The DVFSRC hardware has a clock on all platforms. Instead or proliferating the culture of omitting clock descriptions in the clock controller drivers or marking them critical instead of declaring these types of relationships, add this one to the binding. Any device that wishes to use this binding should figure out their incomplete or incorrect clock situation first before piling more features on top. Acked-by: Rob Herring (Arm) <robh@kernel.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> |
||
|
Rob Herring (Arm)
|
4acd805157 |
dt-bindings: soc: samsung: exynos-pmu: Drop unnecessary select schema
The "select" schema is not necessary because "syscon" compatible is already excluded from the default select logic. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Link: https://patch.msgid.link/20260105212858.3454174-1-robh@kernel.org Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> |
||
|
Peter Griffin
|
411727d918 |
dt-bindings: soc: samsung: exynos-pmu: remove syscon for google,gs101-pmu
Since commit
|
||
|
SungMin Park
|
ce39d255de |
dt-bindings: samsung: exynos-pmu: Add compatible for ARTPEC-9 SoC
Add Axis ARTPEC-9 pmu compatible to the bindings documentation. It reuses the older samsung,exynos7-pmu design. Signed-off-by: SungMin Park <smn1196@coasia.com> Signed-off-by: Ravi Patel <ravi.patel@samsung.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://patch.msgid.link/20251029130731.51305-5-ravi.patel@samsung.com Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> |
||
|
Linus Torvalds
|
a110f94267 |
Pin control changes for the v6.19 kernel cycle:
Core changes:
- Handle per-direction skew control in the generic pin config.
- Drop the pointless subsystem boilerplate banner message during
boot. Less noise in the console. It's available as debug message
if someone really want it.
New drivers:
- Samsung Exynos 8890 SoC support.
- Samsung Exynos derived Axis Communications ARTPEC-9 SoC support.
These guys literally live next door to me, ARTPEC spells out
"Axis Real-Time Picture Encoding Chip" and is tailored for camera
image streams and is something they have evolved for a quarter of
a century.
- Mediatek MT6878 SoC support.
- Qualcomm Glymur PMIC support (mostly just compatible strings).
- Qualcomm Kaanapali SoC TLMM support.
- Microchip pic64gx "gpio2" SoC support.
- Microchip Polarfire "iomux0" SoC support.
- CIX Semiconductors SKY1 SoC support.
- Rockchip RK3506 SoC support.
- Airhoa AN7583 chip support.
Improvements:
- Improvements for ST Microelectronics STM32 handling of skew
settings so input and output can have different skew settings.
- A whole bunch of device tree binding cleanups: Marvell Armada and
Berlin, Actions Semiconductor S700 and S900, Broadcom Northstar 2
(NS2), Bitmain BM1880 and Spreadtrum SC9860 are moved over to schema.
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Merge tag 'pinctrl-v6.19-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pin control updates from Linus Walleij:
"The technical details below. For me the CIX Semi and Axis
Communications ARTPEC-9 SoCs were the most interesting new drivers in
this merge window.
Core changes:
- Handle per-direction skew control in the generic pin config
- Drop the pointless subsystem boilerplate banner message during
boot. Less noise in the console. It's available as debug message if
someone really want it
New drivers:
- Samsung Exynos 8890 SoC support
- Samsung Exynos derived Axis Communications ARTPEC-9 SoC support.
These guys literally live next door to me, ARTPEC spells out "Axis
Real-Time Picture Encoding Chip" and is tailored for camera image
streams and is something they have evolved for a quarter of a
century
- Mediatek MT6878 SoC support
- Qualcomm Glymur PMIC support (mostly just compatible strings)
- Qualcomm Kaanapali SoC TLMM support
- Microchip pic64gx "gpio2" SoC support
- Microchip Polarfire "iomux0" SoC support
- CIX Semiconductors SKY1 SoC support
- Rockchip RK3506 SoC support
- Airhoa AN7583 chip support
Improvements:
- Improvements for ST Microelectronics STM32 handling of skew
settings so input and output can have different skew settings
- A whole bunch of device tree binding cleanups: Marvell Armada and
Berlin, Actions Semiconductor S700 and S900, Broadcom Northstar 2
(NS2), Bitmain BM1880 and Spreadtrum SC9860 are moved over to
schema"
* tag 'pinctrl-v6.19-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (107 commits)
pinctrl: add CONFIG_OF dependencies for microchip drivers
pinctrl: starfive: use dynamic GPIO base allocation
pinctrl: single: Fix incorrect type for error return variable
MAINTAINERS: Change Linus Walleij mail address
pinctrl: cix: Fix obscure dependency
dt-bindings: pinctrl: cix,sky1-pinctrl: Drop duplicate newline
dt-bindings: pinctrl: aspeed,ast2600-pinctrl: Add PCIe RC PERST# group
pinctrl: airoha: Fix AIROHA_PINCTRL_CONFS_DRIVE_E2 in an7583_pinctrl_match_data
pinctrl: airoha: fix pinctrl function mismatch issue
pinctrl: cherryview: Convert to use intel_gpio_add_pin_ranges()
pinctrl: intel: Export intel_gpio_add_pin_ranges()
pinctrl: renesas: rzg2l: Refactor OEN register PWPR handling
pinctrl: airoha: convert comma to semicolon
pinctrl: elkhartlake: Switch to INTEL_GPP() macro
pinctrl: cherryview: Switch to INTEL_GPP() macro
pinctrl: emmitsburg: Switch to INTEL_GPP() macro
pinctrl: denverton: Switch to INTEL_GPP() macro
pinctrl: cedarfork: Switch to INTEL_GPP() macro
pinctrl: airoha: add support for Airoha AN7583 PINs
dt-bindings: pinctrl: airoha: Document AN7583 Pin Controller
...
|
||
|
Linus Torvalds
|
11efc1cb70 |
soc: driver updates for 6.19, part 2
These updates came a little late, or were based on a later 6.18-rc
tag than the others:
- A new driver for cache management on cxl devices with memory shared
in a coherent cluster. This is part of the drivers/cache/ tree, but
unlike the other drivers that back the dma-mapping interfaces, this
one is needed only during CPU hotplug.
- A shared branch for reset controllers using swnode infrastructure
- Added support for new SoC variants in the Amlogic soc_device
identification
- Minor updates in Freescale, Microchip, Samsung, and Apple SoC drivers
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Merge tag 'soc-drivers-6.19-2' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull more SoC driver updates from Arnd Bergmann:
"These updates came a little late, or were based on a later 6.18-rc tag
than the others:
- A new driver for cache management on cxl devices with memory shared
in a coherent cluster. This is part of the drivers/cache/ tree, but
unlike the other drivers that back the dma-mapping interfaces, this
one is needed only during CPU hotplug.
- A shared branch for reset controllers using swnode infrastructure
- Added support for new SoC variants in the Amlogic soc_device
identification
- Minor updates in Freescale, Microchip, Samsung, and Apple SoC
drivers"
* tag 'soc-drivers-6.19-2' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (24 commits)
soc: samsung: exynos-pmu: fix device leak on regmap lookup
soc: samsung: exynos-pmu: Fix structure initialization
soc: fsl: qbman: use kmalloc_array() instead of kmalloc()
soc: fsl: qbman: add WQ_PERCPU to alloc_workqueue users
MAINTAINERS: Update email address for Christophe Leroy
MAINTAINERS: refer to intended file in STANDALONE CACHE CONTROLLER DRIVERS
cache: Support cache maintenance for HiSilicon SoC Hydra Home Agent
cache: Make top level Kconfig menu a boolean dependent on RISCV
MAINTAINERS: Add Jonathan Cameron to drivers/cache and add lib/cache_maint.c + header
arm64: Select GENERIC_CPU_CACHE_MAINTENANCE
lib: Support ARCH_HAS_CPU_CACHE_INVALIDATE_MEMREGION
soc: amlogic: meson-gx-socinfo: add new SoCs id
dt-bindings: arm: amlogic: meson-gx-ao-secure: support more SoCs
memregion: Support fine grained invalidate by cpu_cache_invalidate_memregion()
memregion: Drop unused IORES_DESC_* parameter from cpu_cache_invalidate_memregion()
dt-bindings: cache: sifive,ccache0: add a pic64gx compatible
MAINTAINERS: rename Microchip RISC-V entry
MAINTAINERS: add new soc drivers to Microchip RISC-V entry
soc: microchip: add mfd drivers for two syscon regions on PolarFire SoC
dt-bindings: soc: microchip: document the simple-mfd syscon on PolarFire SoC
...
|
||
|
Linus Torvalds
|
208eed95fc |
soc: driver updates for 6.19
This is the first half of the driver changes:
- A treewide interface change to the "syscore" operations for
power management, as a preparation for future Tegra specific
changes.
- Reset controller updates with added drivers for LAN969x, eic770
and RZ/G3S SoCs.
- Protection of system controller registers on Renesas and Google SoCs,
to prevent trivially triggering a system crash from e.g. debugfs
access.
- soc_device identification updates on Nvidia, Exynos and Mediatek
- debugfs support in the ST STM32 firewall driver
- Minor updates for SoC drivers on AMD/Xilinx, Renesas, Allwinner, TI
- Cleanups for memory controller support on Nvidia and Renesas
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Merge tag 'soc-drivers-6.19' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull SoC driver updates from Arnd Bergmann:
"This is the first half of the driver changes:
- A treewide interface change to the "syscore" operations for power
management, as a preparation for future Tegra specific changes
- Reset controller updates with added drivers for LAN969x, eic770 and
RZ/G3S SoCs
- Protection of system controller registers on Renesas and Google
SoCs, to prevent trivially triggering a system crash from e.g.
debugfs access
- soc_device identification updates on Nvidia, Exynos and Mediatek
- debugfs support in the ST STM32 firewall driver
- Minor updates for SoC drivers on AMD/Xilinx, Renesas, Allwinner, TI
- Cleanups for memory controller support on Nvidia and Renesas"
* tag 'soc-drivers-6.19' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (114 commits)
memory: tegra186-emc: Fix missing put_bpmp
Documentation: reset: Remove reset_controller_add_lookup()
reset: fix BIT macro reference
reset: rzg2l-usbphy-ctrl: Fix a NULL vs IS_ERR() bug in probe
reset: th1520: Support reset controllers in more subsystems
reset: th1520: Prepare for supporting multiple controllers
dt-bindings: reset: thead,th1520-reset: Add controllers for more subsys
dt-bindings: reset: thead,th1520-reset: Remove non-VO-subsystem resets
reset: remove legacy reset lookup code
clk: davinci: psc: drop unused reset lookup
reset: rzg2l-usbphy-ctrl: Add support for RZ/G3S SoC
reset: rzg2l-usbphy-ctrl: Add support for USB PWRRDY
dt-bindings: reset: renesas,rzg2l-usbphy-ctrl: Document RZ/G3S support
reset: eswin: Add eic7700 reset driver
dt-bindings: reset: eswin: Documentation for eic7700 SoC
reset: sparx5: add LAN969x support
dt-bindings: reset: microchip: Add LAN969x support
soc: rockchip: grf: Add select correct PWM implementation on RK3368
soc/tegra: pmc: Add USB wake events for Tegra234
amba: tegra-ahb: Fix device leak on SMMU enable
...
|
||
|
Linus Torvalds
|
0cac5ce06e |
soc: devicetree updates for 6.19
Three new SoCs got added in existing arm64 chip families:
- Renesas R-Car X5H (R8A78000) is a new generation of automotive SoCs,
based on 16 Cortex-A720 (Armv9.2) cores, which makes the the currently
highest-perforance embedded SoC.
- TI AM62L is a new variant of the AM62 family of industrial SoCs, this
one comes without a GPU.
- Qualcomm MSM8937 (Snapdragon 430) is an older mobile phone chip based
on Cortex-A53, and closely related to MSM8917 (Snapdragn 425), which we
already support.
In addition, there are a good number of newly supported machines
across SoC families:
- Two Aspeed AST2600 (Cortex-A7) based BMC setups for large servers
- Mobile Phones and tables based on Mediatek MT6582, Nvidia Tegra124,
Qualcomm MSM8937 and Qualcomm MSM8939,
- Two Laptops based on Qualcomm SoCs: one using the older sdm850, the
other using x1p42100.
- One Router based on Rockchips RK3568
- 24 variants of the Enclustra Mercury system-on-module, all based on
32-bit Intel/Altera SocFPGA chips, plus two boards using 64-bit
SocFPGA Agilex chips..
- 30 industrial/embedded boards and single-board computers, using
various chips from NXP, Rockchips, Mediatek, TI, Amlogic, Qualcomm,
Spacemit, and Starfive.
In total there are 783 commits here, the majority of these improving
hardware support and cleaning up devicetree files across the tree, with
the majority of the changes going into the Qualcomm, NXP, Renesas and
Rockchips platforms.
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Merge tag 'soc-dt-6.19' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull SoC devicetree updates from Arnd Bergmann:
"Three new SoCs got added in existing arm64 chip families:
- Renesas R-Car X5H (R8A78000) is a new generation of automotive
SoCs, based on 16 Cortex-A720 (Armv9.2) cores, which makes the the
currently highest-perforance embedded SoC.
- TI AM62L is a new variant of the AM62 family of industrial SoCs,
this one comes without a GPU.
- Qualcomm MSM8937 (Snapdragon 430) is an older mobile phone chip
based on Cortex-A53, and closely related to MSM8917 (Snapdragn
425), which we already support.
In addition, there are a good number of newly supported machines
across SoC families:
- Two Aspeed AST2600 (Cortex-A7) based BMC setups for large servers
- Mobile Phones and tables based on Mediatek MT6582, Nvidia Tegra124,
Qualcomm MSM8937 and Qualcomm MSM8939,
- Two Laptops based on Qualcomm SoCs: one using the older sdm850, the
other using x1p42100.
- One Router based on Rockchips RK3568
- 24 variants of the Enclustra Mercury system-on-module, all based on
32-bit Intel/Altera SocFPGA chips, plus two boards using 64-bit
SocFPGA Agilex chips..
- 30 industrial/embedded boards and single-board computers, using
various chips from NXP, Rockchips, Mediatek, TI, Amlogic, Qualcomm,
Spacemit, and Starfive.
In total there are 783 commits here, the majority of these improving
hardware support and cleaning up devicetree files across the tree,
with the majority of the changes going into the Qualcomm, NXP, Renesas
and Rockchips platforms"
* tag 'soc-dt-6.19' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (782 commits)
arm64: dts: mediatek: mt8195: Fix address range for JPEG decoder core 1
ARM: dts: samsung: exynos4412-midas: turn off SDIO WLAN chip during system suspend
ARM: dts: samsung: exynos4210-trats: turn off SDIO WLAN chip during system suspend
ARM: dts: samsung: exynos4210-i9100: turn off SDIO WLAN chip during system suspend
ARM: dts: samsung: universal_c210: turn off SDIO WLAN chip during system suspend
arm64: dts: amlogic: meson-g12b: Fix L2 cache reference for S922X CPUs
arm64: dts: Add gpio_intc node for Amlogic S7D SoCs
arm64: dts: Add gpio_intc node for Amlogic S7 SoCs
arm64: dts: Add gpio_intc node for Amlogic S6 SoCs
arm64: dts: amlogic: s7d: add ao secure node
arm64: dts: amlogic: s7: add ao secure node
arm64: dts: amlogic: s6: add ao secure node
arm64: dts: amlogic: Fix the register name of the 'DBI' region
dts: arm64: amlogic: add a5 pinctrl node
arm64: dts: amlogic: s7d: add power domain controller node
arm64: dts: amlogic: s7: add power domain controller node
arm64: dts: amlogic: s6: add power domain controller node
dts: arm64: amlogic: Add ISP related nodes for C3
arm64: dts: meson: add initial device-tree for Tanix TX9 Pro
dt-bindings: arm: amlogic: add support for Tanix TX9 Pro
...
|
||
|
Linus Torvalds
|
6044a1ee9d |
Devicetree updates for v6.19:
DT bindings:
- Convert lattice,ice40-fpga-mgr, apm,xgene-storm-dma, brcm,sr-thermal,
amazon,al-thermal, brcm,ocotp, mt8173-mdp, Actions Owl SPS, Marvell
AP80x System Controller, Marvell CP110 System Controller,
cznic,moxtet, and apm,xgene-slimpro-mbox to DT schema format
- Add i.MX95 fsl,irqsteer, MT8365 Mali Bifrost GPU, Anvo ANV32C81W
EEPROM, and Microchip pic64gx PLIC
- Add missing LGE, AMD Seattle, and APM X-Gene SoC platform compatibles
- Updates to brcm,bcm2836-l1-intc, brcm,bcm2835-hvs, and bcm2711-hdmi
bindings to fix warnings on BCM2712 platforms
- Drop obsolete db8500-thermal.txt
- Treewide clean-up of extra blank lines and inconsistent quoting
- Ensure all .dtbo targets are applied to a base .dtb
- Speed up dt_binding_check by skipping running validation on empty
examples
DT core:
- Add of_machine_device_match() and of_machine_get_match_data() helpers
and convert users treewide
- Fix bounds checking of address properties in FDT code. Rework the code
to have a single implementation of the bounds checks.
- Rework of_irq_init() to ignore any implicit interrupt-parent (i.e. in
a parent node) on nodes without an interrupt. This matches the spec
description and fixes some RISC-V platforms.
- Avoid a spurious message on overlay removal
- Skip DT kunit tests on RISCV+ACPI
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Merge tag 'devicetree-for-6.19' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux
Pull devicetree updates from Rob Herring:
"DT bindings:
- Convert lattice,ice40-fpga-mgr, apm,xgene-storm-dma,
brcm,sr-thermal, amazon,al-thermal, brcm,ocotp, mt8173-mdp, Actions
Owl SPS, Marvell AP80x System Controller, Marvell CP110 System
Controller, cznic,moxtet, and apm,xgene-slimpro-mbox to DT schema
format
- Add i.MX95 fsl,irqsteer, MT8365 Mali Bifrost GPU, Anvo ANV32C81W
EEPROM, and Microchip pic64gx PLIC
- Add missing LGE, AMD Seattle, and APM X-Gene SoC platform
compatibles
- Updates to brcm,bcm2836-l1-intc, brcm,bcm2835-hvs, and bcm2711-hdmi
bindings to fix warnings on BCM2712 platforms
- Drop obsolete db8500-thermal.txt
- Treewide clean-up of extra blank lines and inconsistent quoting
- Ensure all .dtbo targets are applied to a base .dtb
- Speed up dt_binding_check by skipping running validation on empty
examples
DT core:
- Add of_machine_device_match() and of_machine_get_match_data()
helpers and convert users treewide
- Fix bounds checking of address properties in FDT code. Rework the
code to have a single implementation of the bounds checks.
- Rework of_irq_init() to ignore any implicit interrupt-parent (i.e.
in a parent node) on nodes without an interrupt. This matches the
spec description and fixes some RISC-V platforms.
- Avoid a spurious message on overlay removal
- Skip DT kunit tests on RISCV+ACPI"
* tag 'devicetree-for-6.19' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: (55 commits)
dt-bindings: kbuild: Skip validating empty examples
dt-bindings: interrupt-controller: brcm,bcm2836-l1-intc: Drop interrupt-controller requirement
dt-bindings: display: Fix brcm,bcm2835-hvs bindings for BCM2712
dt-bindings: display: bcm2711-hdmi: Add interrupt details for BCM2712
of: Skip devicetree kunit tests when RISCV+ACPI doesn't populate root node
soc: tegra: Simplify with of_machine_device_match()
soc: qcom: ubwc: Simplify with of_machine_get_match_data()
powercap: dtpm: Simplify with of_machine_get_match_data()
platform: surface: Simplify with of_machine_get_match_data()
irqchip/atmel-aic: Simplify with of_machine_get_match_data()
firmware: qcom: scm: Simplify with of_machine_device_match()
cpuidle: big_little: Simplify with of_machine_device_match()
cpufreq: sun50i: Simplify with of_machine_device_match()
cpufreq: mediatek: Simplify with of_machine_get_match_data()
cpufreq: dt-platdev: Simplify with of_machine_get_match_data()
of: Add wrappers to match root node with OF device ID tables
dt-bindings: eeprom: at25: Add Anvo ANV32C81W
of/reserved_mem: Simplify the logic of __reserved_mem_alloc_size()
of/reserved_mem: Simplify the logic of fdt_scan_reserved_mem_reg_nodes()
of/reserved_mem: Simplify the logic of __reserved_mem_reserve_reg()
...
|
||
|
Arnd Bergmann
|
4b1e815701 |
MediaTek soc driver updates
This adds socinfo entries for MT8189 Kompanio 540, an extra entry for a variant of MT8391 (AV/AZA) Genio 720 SoC, and support for the PMIC Wrapper (by adding a compatible string) in MT8189. -----BEGIN PGP SIGNATURE----- iLoEABYKAGIWIQQn3Xxr56ypAcSHzXSaNgTPrZeEeAUCaRMG/xsUgAAAAAAEAA5t YW51MiwyLjUrMS4xMSwyLDIoHGFuZ2Vsb2dpb2FjY2hpbm8uZGVscmVnbm9AY29s bGFib3JhLmNvbQAKCRCaNgTPrZeEeD10AQDq9xEZ3TYffYjCl9j41Ct8HDSmv0x/ nRTXBWXMH9JhbwD/YRigXkEQQcwPrluqgW/hBnF6a4br5AOns63n7j1xog0= =dYcz -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmkltJIACgkQmmx57+YA GNmqSxAAo0e8EKQhJxG5D90LyrKkJ7c/iDwRuMIvIAlRtzL874/k2brWs00gcQ8D y7VvFFW1pgyuKCHaEV9iz8YHmOdbuzOjT8ZNRgZkgW006pFEys8kQeOIia6KpO1E MGjZi3E77sRx/jlc6OGRs5dHuoRgx6p+RCC9q6y8goYhcO3AO27GmZYttGz1chTe OJJWqomDsQM+zwWzkUbabIocPCmACcS+qcuQuf0PZuY+I2j4Rj/ZWnauW27hjsRp puJremjmzG2XmunUrE9BU7r97ie7Cd2gRNRktiwkvHXn+fp5EJq6hB3J3frFGZjF JMr0HkkekSnuDoJREw3tzJmnR6sAqC3kD75P42r+y9UaUgRKmDfbY89w31ojAUty dTL284D1+35gfLDMeq7GOFDG0gTPGpfDfEZs5onoMwGIM7nZbmREba6n36OHvhHq venYgKTOWv6ggbAc7Q40KYo2B55ZLX4hcJHW2AFuBkGTW+mndBOnIa1EV2BPC7cA LN4L46/46LYP2vUUJ2BqSQxplStgTsLizO16O2AiF3k7culhesCHoiEHE8YHXuqu omsDuqN9XTrIO/pgsYaxqmSZe4ggkRz4kGas1vax6FaayAIsWYTO9eRM0+I8/Row /nSBx2ZEUZs5rMzrOGCo0akFmWLDlS22D9ebuHZB1SFtnG8B3PA= =OEnV -----END PGP SIGNATURE----- Merge tag 'mtk-soc-for-v6.19' of https://git.kernel.org/pub/scm/linux/kernel/git/mediatek/linux into soc/drivers MediaTek soc driver updates This adds socinfo entries for MT8189 Kompanio 540, an extra entry for a variant of MT8391 (AV/AZA) Genio 720 SoC, and support for the PMIC Wrapper (by adding a compatible string) in MT8189. * tag 'mtk-soc-for-v6.19' of https://git.kernel.org/pub/scm/linux/kernel/git/mediatek/linux: dt-bindings: soc: mediatek: pwrap: Add compatible for MT8189 SoC soc: mediatek: mtk-socinfo: Add entry for MT8391AV/AZA Genio 720 soc: mediatek: mtk-socinfo: Add extra entry for MT8189 Signed-off-by: Arnd Bergmann <arnd@arndb.de> |
||
|
Arnd Bergmann
|
3d497bf8ef |
Qualcomm driver updates for v6.19
Support for hardware-keymanager v1 support for wrapped keys is introduce in the ICE driver. Support for the new Kaanapali mobile platform is added to last-level cache controller, pd-mapper, and UBWC drivers. UBWC driver gains support for the Monaco and Glymur platforms. The PMIC GLINK driver is extended to handle the differences found in targets where the related firmware runs on the SoCCP. Support for running on targets without initialized SMEM is provided, by reworking the SMEM driver to differentiate between "not yet probed" and "probed but there was no SMEM". An unwanted WARN_ON() that triggered if clients asked for a SMEM item beyond the currently running system's limit, was removed, to allow new use cases to gracefully fail on old targets. The Qualcomm socinfo driver is extended with support for version 20 through 23 and support for providing version information about more than 32 remote processors. Identifiers for QCS6490 and SM8850 are also added. Additionally, a number of smaller bug fixes and cleanups in PBS, OCMEM, GSBI, TZMEM, and MDT-loader are included. -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEBd4DzF816k8JZtUlCx85Pw2ZrcUFAmkbfWsACgkQCx85Pw2Z rcX64xAAx8b+PBGtPI7BSWzmybVbcwVrodul4z8Gtd++0wVXHOGVwiiBJ5tw3QI4 R58P2ENgRyBqdzH94G8JZ0XfdJ+qP0qYjhiEvr9jJ+aeuOyhDzlFQ6iSdCt/gG3g wBnb8IyqVfLwj6t6erUHOCXv1Wa5GSdbj48cYaAcy2VMZK45UIiQDhPuoI75ZEFK UBTRQkFiMTlOvr0bQznA3QALZwFCFRzkXbIuvYKCBmoWjgqKRekEFtm+PNGPfTUw NKhITaI6UEjJN22uGrSNSzomuGLgfSsAPSIoty2E9c1FYglNsiRLLj80wJHqTK96 zIkTFsR0gJAcC91l7Vj+jAbXBTLZadzXBzlUdLSqeTUJ43RuTspNgWgV+5U+mwPE NxUBEatrPx2tg9pxbnVXdphBEaOhq57XM/nL3wxRLdUw41dJ9hzFG6ieYWSbhPlh 6lx+aJOc2FsBpDkvnEWdkAxSOxnwWLdo+ICCljS/DDUKfBkZkgDX4yacL1QTBWP6 kuLDpmYUQNHlJ0Al/P4YuiOqMVoDz8ZwNHZoXRLPFZsI8rZEjMGoCqLvziOcQKS2 3kwXlC2ds/Q2DtYa/8ASNg/Laby9+5dSZndZWsL9jW8Uj4CgpZkZIa5VKXiQLOOz bgVcJIClbw/+Tg6RH7WDveF3FVKJMu+LoVxogIrhNImBWh60fbA= =Eh2U -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmklqIwACgkQmmx57+YA GNl7/g/+M182m6/83pKU2JZyJQvYMG6r5p3TATOeXmjvsE/0dSbWpJd9/OA+Y0MM VuGJTWLYGcWHl8xZTKakxS/H5Ngmrt+CdwEx9ei6uwLnCLLuXwJy+XhHC6yIM9Ec 7fJBCOUQHxHD/uHlHmu7qb9YpsNYnTfSE9Aj77lwokZGTdPG3yk/wD04EfDIYR0e jYziEJSmcVljQvOusfPycNkEVbimqLAApnwdLthab/hepI0wzdtNJ8hmUYZGlqyt vXtCYRZa8Y00MSdYvGKBJY33mTGNI71W+XJ0tYeetLh2vf9pA80ACxmP2D8FdsW0 3EVz/tWRwYAFVr/CmknXbhY35jXy3H4h83KFLLOwItGwaXfAk1hCCTMbNzMONIpU +yA91hxvWaqNsYvRZUISxKaU9r29rcxpJ7PuehNp9/+f4sAqggjabE7SVt6vaQX2 Dz/PF2iEfm+lzd4+KEz6gx0Q8zNetQJRvy9pihGjBwnbtJJCBXUv+SG7BoCvYlY5 s1281QcEtTDF120VHmZ1HhOrRdsihK2pkGFQUTC6MsRHFECbKAk92otbfNlEY7J2 KdFDdf3cPswDuzNoSYNyUkO1UgWZkLLJbctfaYmd4afzxsLmdRmPMvkO1sy8O823 lRnls0Pukauld+NrppsCkle7DL4vOhX3GdACQrrmjBPDbKEfIA4= =N2C2 -----END PGP SIGNATURE----- Merge tag 'qcom-drivers-for-6.19' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/drivers Qualcomm driver updates for v6.19 Support for hardware-keymanager v1 support for wrapped keys is introduce in the ICE driver. Support for the new Kaanapali mobile platform is added to last-level cache controller, pd-mapper, and UBWC drivers. UBWC driver gains support for the Monaco and Glymur platforms. The PMIC GLINK driver is extended to handle the differences found in targets where the related firmware runs on the SoCCP. Support for running on targets without initialized SMEM is provided, by reworking the SMEM driver to differentiate between "not yet probed" and "probed but there was no SMEM". An unwanted WARN_ON() that triggered if clients asked for a SMEM item beyond the currently running system's limit, was removed, to allow new use cases to gracefully fail on old targets. The Qualcomm socinfo driver is extended with support for version 20 through 23 and support for providing version information about more than 32 remote processors. Identifiers for QCS6490 and SM8850 are also added. Additionally, a number of smaller bug fixes and cleanups in PBS, OCMEM, GSBI, TZMEM, and MDT-loader are included. * tag 'qcom-drivers-for-6.19' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (31 commits) soc: qcom: mdt_loader: rename 'firmware' parameter of qcom_mdt_load() soc: qcom: mdt_loader: merge __qcom_mdt_load() and qcom_mdt_load_no_init() soc: qcom: socinfo: Add reserve field to support future extension soc: qcom: socinfo: Add support for new fields in revision 20 dt-bindings: firmware: qcom,scm: Document SCM on Kaanapali SOC soc: qcom: socinfo: add support to extract more than 32 image versions soc: qcom: smem: drop the WARN_ON() on SMEM item validation soc: qcom: ubwc: Add config for Kaanapali soc: qcom: socinfo: Add SoC ID for QCS6490 dt-bindings: arm: qcom,ids: Add SoC ID for QCS6490 soc: qcom: ice: Add HWKM v1 support for wrapped keys soc: qcom: smem: better track SMEM uninitialized state err.h: add INIT_ERR_PTR() macro soc: qcom: smem: fix hwspinlock resource leak in probe error paths dt-bindings: soc: qcom,aoss-qmp: Document the Glymur AOSS side channel dt-bindings: soc: qcom,aoss-qmp: Document the Kaanapali AOSS channel soc: qcom: ubwc: Add QCS8300 UBWC cfg dt-bindings: firmware: qcom,scm: Document Glymur scm soc: qcom: socinfo: Add SM8850 SoC ID dt-bindings: arm: qcom,ids: Add SoC ID for SM8850 ... Signed-off-by: Arnd Bergmann <arnd@arndb.de> |
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Arnd Bergmann
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a60997452a |
i.MX dt-bindings update for 6.19:
- New board support: Protonic PRT8ML, Toradex SMARC iMX95, Skov Rev.C HDMI, i.MX 95 Verdin Evaluation KitPHYTEC phyBOARD-Segin-i.MX91 board, Skov i.MX8MP variant - One imx-iomuxc-gpr update from Fabio Estevam to document CSI mux - A couple of fpga-qixis bindings updates from Ioana Ciornei - One embedded-controller update from Mathew McBride to add Traverse Ten64 board controller -----BEGIN PGP SIGNATURE----- iQEzBAABCgAdFiEEFmJXigPl4LoGSz08UFdYWoewfM4FAmkbDIwACgkQUFdYWoew fM6EZQf/cf2uQku0yCj1LQ+4l/OxPsKh9aSjb0iV7wI8kylKjLkdQeHYKSbPUFZ3 s3rbsK9FsxPAUfR0lygz6Hx0o4CcASezm/t81GuCCuaYXo4hfZ0ORI8r9kT+Z2rE cVUmnDe29lfPLEaMlpefQ27hJ+Z8Wj6zDm0sTmbveSXtFqzDmYs+1k8p29KRLuzm kfOgSCMo8nWTCYwbBVYODY7Yo1IXX8F0q5bzjBJOALMaQqkxYLJNKdB9MaWm5uQg rSUuEFUmOiwhjZLsXByBDA6I7exU7XjteLTuRRSXabY4XMeXKzJXBlFINDoJtLES 7e/tzzastbPhvwjSl8ywX6yFwimS6A== =wnpe -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmkg1y0ACgkQmmx57+YA GNmZyBAAgXCgtt+/gdMdjc6+niBI4DtILHLH50wp51PZtNxRviCfc7tXSaNpyzhj 8BMSI6KdeXV87tglZ590vfQhPCGF0lx95KPhi2X9+lwBafw1usJr7rDiF8Gw/SDM gTpm3pUWcI4lsjGhAsx102rC0Me5tX2UV822PSEPsAx4s6x8oI1vBpFa7IMtKa9G F3B1ZVGFNj96JzPEIbo9FFHHdaD5rqdHLTNAqTwA8a8lLQlSV3R75qU+GcuXY9Ig ifV/J4dqEczuLMrmh5ky6SNoBhi5iY9cG9R24q6iwBI4hSUNyq360kEuKmKUAk1c 6AUR1RpkmUAWV2TSoty4TDgtNx4VNczeG8tTIxFBJ3jZuF0sGU5pqzVR89fZlKQf afcOMV6nLiL+BlQNpP9W0U4WyuCB4eUVwtTOWlgLJ2Z2s4nsuwnrvczqEo/LSb2J J5HhvB02gpF/NfwVj0cZbqPebmBTY20pARZ0atyRWA1r8+K5DuAy6nQcyjRQx24p VR3VRf4jVWzhXm1v6hXkP2sWLiqkVsu0CEhyQ8HP3W5hJ02CXNlwqRXJjdP0YnUB ZKK8UU8ADuT2Ej5AL+Gyd4euG4PfquxJ5ozLZ40Yc98cX/0fRZP1yj/P0y/+8dgE 1wOMKdTCkkA1bWsZDrzJkfWrMY57HrY80waZ55MFBvmLVE85kus= =Ce4x -----END PGP SIGNATURE----- Merge tag 'imx-bindings-6.19' of https://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into soc/dt i.MX dt-bindings update for 6.19: - New board support: Protonic PRT8ML, Toradex SMARC iMX95, Skov Rev.C HDMI, i.MX 95 Verdin Evaluation KitPHYTEC phyBOARD-Segin-i.MX91 board, Skov i.MX8MP variant - One imx-iomuxc-gpr update from Fabio Estevam to document CSI mux - A couple of fpga-qixis bindings updates from Ioana Ciornei - One embedded-controller update from Mathew McBride to add Traverse Ten64 board controller * tag 'imx-bindings-6.19' of https://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: dt-bindings: arm: fsl: add Toradex SMARC iMX95 dt-bindings: arm: fsl: add Skov Rev.C HDMI support dt-bindings: arm: fsl: Add PHYTEC phyBOARD-Segin-i.MX91 board dt-bindings: fsl,fpga-qixis: describe the gpio child node found on LS1046AQDS dt-bindings: fsl,fpga-qixis-i2c: add support for LX2160ARDB FPGA dt-bindings: arm: fsl: Add Protonic PRT8ML dt-bindings: arm: imx: document i.MX 95 Verdin Evaluation Kit (EVK) dt-bindings: embedded-controller: add Traverse Ten64 board controller dt-bindings: soc: imx-iomuxc-gpr: Document the CSI mux dt-bindings: arm: fsl: add compatible for Skov i.MX8MP variant Signed-off-by: Arnd Bergmann <arnd@arndb.de> |
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Rob Herring (Arm)
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0b2333183a |
dt-bindings: Remove extra blank lines
Generally at most 1 blank line is the standard style for DT schema files. Remove the few cases with more than 1 so that the yamllint check for this can be enabled. Acked-by: Lee Jones <lee@kernel.org> Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org> # remoteproc Acked-by: Georgi Djakov <djakov@kernel.org> Acked-by: Vinod Koul <vkoul@kernel.org> Acked-by: Andi Shyti <andi.shyti@kernel.org> Acked-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Acked-by: Jonathan Cameron <jonathan.cameron@huawei.com> Acked-by: Philipp Zabel <p.zabel@pengutronix.de> Acked-by: Uwe Kleine-König <ukleinek@kernel.org> # for allwinner,sun4i-a10-pwm.yaml Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com> # mtd Acked-by: Guenter Roeck <linux@roeck-us.net> Acked-by: Mark Brown <broonie@kernel.org> Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Acked-by: Sebastian Reichel <sebastian.reichel@collabora.com> Acked-by: Manivannan Sadhasivam <mani@kernel.org> # For PCI controller bindings Link: https://patch.msgid.link/20251023143957.2899600-1-robh@kernel.org Signed-off-by: Rob Herring (Arm) <robh@kernel.org> |
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Krzysztof Kozlowski
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bcc357c8e0 |
dt-bindings: Update Krzysztof Kozlowski's email
Update Krzysztof Kozlowski's email address to kernel.org account to stay reachable. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://patch.msgid.link/20251021095354.86455-2-krzysztof.kozlowski@linaro.org Signed-off-by: Rob Herring (Arm) <robh@kernel.org> |
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Rob Herring (Arm)
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01585d7470 |
dt-bindings: Fix inconsistent quoting
yamllint has gained a new check which checks for inconsistent quoting (mixed " and ' quotes within a file). Fix all the cases yamllint found so we can enable the check (once the check is in a release). As single quotes are (slightly) preferred, use them throughout the modified files even if double quotes are mostly used. Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Jonathan Cameron <jonathan.cameron@huawei.com> Acked-by: Andrew Jeffery <andrew@codeconstruct.com.au> Acked-by: Jassi Brar <jassisinghbrar@gmail.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Lee Jones <lee@kernel.org> Acked-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Link: https://patch.msgid.link/20251015232015.846282-1-robh@kernel.org Signed-off-by: Rob Herring (Arm) <robh@kernel.org> |
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Longbin Li
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565c450124 |
dt-bindings: soc: sophgo: add TOP syscon for CV18XX/SG200X series SoC
The Sophgo CV18XX/SG200X SoC top misc system controller provides register access to configure related modules. It includes a usb2 phy and a dma multiplexer. Co-developed-by: Inochi Amaoto <inochiama@gmail.com> Signed-off-by: Longbin Li <looong.bin@gmail.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20251101014329.18439-2-looong.bin@gmail.com Signed-off-by: Inochi Amaoto <inochiama@gmail.com> Signed-off-by: Chen Wang <unicorn_wang@outlook.com> Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn> |
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Stanimir Varbanov
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34194cb385 |
dt-bindings: soc: bcm: Add bcm2712 compatible
Add bcm2712-pm compatible and update the bindings to satisfy it's requirements. The PM hardware block inside bcm2712 lacks the "asb" and "rpivid_asb" register ranges and also does not have clocks, update the bindings accordingly. Signed-off-by: Stanimir Varbanov <svarbanov@suse.de> Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> |
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Kaustabh Chakraborty
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81280d39a2 |
dt-bindings: soc: samsung: exynos-pmu: allow mipi-phy subnode for Exynos7870 PMU
Exynos7870 PMU is already documented in schema. Add Exynos7870's PMU compatible to the list of nodes which allow a MIPI PHY driver. Signed-off-by: Kaustabh Chakraborty <kauschluss@disroot.org> Acked-by: Rob Herring (Arm) <robh@kernel.org> Link: https://patch.msgid.link/20251031-exynos7870-drm-dts-v4-1-c1f77fb16b87@disroot.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> |
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Louis-Alexis Eyraud
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4459d667a3
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dt-bindings: soc: mediatek: pwrap: Add compatible for MT8189 SoC
Add compatible string for the PWRAP block on MT8189 SoC, which is compatible with the one used on MT8195. Signed-off-by: Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> |