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arm64: dts: renesas: r8a779f0: Add L3 cache controller

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Describe the cache configuration for the first Cortex-A55 CPU core on
the Renesas R-Car S4-8 (R8A779F0) SoC.

Extracted from a larger patch in the BSP by LUU HOAI.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Tested-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/r/a63715ce1d2d2fcc7ab987f7a1b40847965e8d6a.1654701480.git.geert+renesas@glider.be
This commit is contained in:
Geert Uytterhoeven 2022-06-08 17:40:19 +02:00
parent 06279f82da
commit ffeca49a8b
1 changed files with 8 additions and 0 deletions
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arch/arm64/boot/dts/renesas/r8a779f0.dtsi
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@ -23,6 +23,14 @@ a55_0: cpu@0 {
reg = <0>;
device_type = "cpu";
power-domains = <&sysc R8A779F0_PD_A1E0D0C0>;
next-level-cache = <&L3_CA55_0>;
};
L3_CA55_0: cache-controller-0 {
compatible = "cache";
power-domains = <&sysc R8A779F0_PD_A2E0D0>;
cache-unified;
cache-level = <3>;
};
};