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arm64: dts: renesas: r8a779a0: Add CPU0 core clock

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Describe the clock for the first Cortex-A76 CPU core.
For now no operating points are defined.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/3ace4eea4ff1cdc0f7b8ea7d0433c1063d795785.1654701400.git.geert+renesas@glider.be
This commit is contained in:
Geert Uytterhoeven 2022-06-08 17:17:42 +02:00
parent 650fd1d058
commit 06279f82da
1 changed files with 1 additions and 0 deletions
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arch/arm64/boot/dts/renesas/r8a779a0.dtsi
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@ -41,6 +41,7 @@ a76_0: cpu@0 {
device_type = "cpu";
power-domains = <&sysc R8A779A0_PD_A1E0D0C0>;
next-level-cache = <&L3_CA76_0>;
clocks = <&cpg CPG_CORE R8A779A0_CLK_Z0>;
};
L3_CA76_0: cache-controller-0 {