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arm64: dts: renesas: r9a07g044: Rename SDHI clocks

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Rename the below SDHI clocks to match with the clocks used in driver.

     imclk->core
     clk_hs->clkh
     imclk2->cd

Also re-arrange the clocks to match with the sorting order used in the
binding document.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Acked-by: Ulf Hansson <ulf.hansson@linaro.org>
Link: https://lore.kernel.org/r/20211122103905.14439-3-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This commit is contained in:
Biju Das 2021-11-22 10:39:05 +00:00 committed by Geert Uytterhoeven
parent c81bd70f47
commit fee3eae133
1 changed files with 4 additions and 4 deletions
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8
arch/arm64/boot/dts/renesas/r9a07g044.dtsi
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@ -613,10 +613,10 @@ sdhi0: mmc@11c00000 {
interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD R9A07G044_SDHI0_IMCLK>,
<&cpg CPG_MOD R9A07G044_SDHI0_IMCLK2>,
<&cpg CPG_MOD R9A07G044_SDHI0_CLK_HS>,
<&cpg CPG_MOD R9A07G044_SDHI0_IMCLK2>,
<&cpg CPG_MOD R9A07G044_SDHI0_ACLK>;
clock-names = "imclk", "imclk2", "clk_hs", "aclk";
clock-names = "core", "clkh", "cd", "aclk";
resets = <&cpg R9A07G044_SDHI0_IXRST>;
power-domains = <&cpg>;
status = "disabled";
@ -629,10 +629,10 @@ sdhi1: mmc@11c10000 {
interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD R9A07G044_SDHI1_IMCLK>,
<&cpg CPG_MOD R9A07G044_SDHI1_IMCLK2>,
<&cpg CPG_MOD R9A07G044_SDHI1_CLK_HS>,
<&cpg CPG_MOD R9A07G044_SDHI1_IMCLK2>,
<&cpg CPG_MOD R9A07G044_SDHI1_ACLK>;
clock-names = "imclk", "imclk2", "clk_hs", "aclk";
clock-names = "core", "clkh", "cd", "aclk";
resets = <&cpg R9A07G044_SDHI1_IXRST>;
power-domains = <&cpg>;
status = "disabled";