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arm64: dts: renesas: rzg2l-smarc-som: Enable serial NOR flash
Enable mt25qu512a flash connected to QSPI0. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20211121234906.9602-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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@ -186,6 +186,18 @@ gpio-sd0-pwr-en-hog {
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line-name = "gpio_sd0_pwr_en";
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};
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qspi0_pins: qspi0 {
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qspi0-data {
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pins = "QSPI0_IO0", "QSPI0_IO1", "QSPI0_IO2", "QSPI0_IO3";
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power-source = <1800>;
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};
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qspi0-ctrl {
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pins = "QSPI0_SPCLK", "QSPI0_SSL", "QSPI_RESET#";
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power-source = <1800>;
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};
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};
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/*
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* SD0 device selection is XOR between GPIO_SD0_DEV_SEL and SW1[2]
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* The below switch logic can be used to select the device between
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@ -251,6 +263,34 @@ sd0_mux_uhs {
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};
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};
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&sbc {
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pinctrl-0 = <&qspi0_pins>;
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pinctrl-names = "default";
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status = "okay";
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flash@0 {
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compatible = "micron,mt25qu512a", "jedec,spi-nor";
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reg = <0>;
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m25p,fast-read;
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spi-max-frequency = <50000000>;
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spi-rx-bus-width = <4>;
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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boot@0 {
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reg = <0x00000000 0x2000000>;
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read-only;
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};
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user@2000000 {
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reg = <0x2000000 0x2000000>;
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};
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};
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};
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};
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#if SDHI
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&sdhi0 {
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pinctrl-0 = <&sdhi0_pins>;
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