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https://github.com/torvalds/linux.git
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ASoC: SOF: amd: add soundwire IO support for ACP7.0 &
Merge series from Vijendar Mukunda <Vijendar.Mukunda@amd.com>: This patch series contains - ACP sof stack improvements - Add support for ACP7.1 platform. - Soundwire IO support for ACP7.0 & ACP7.1 platforms Link: https://github.com/thesofproject/linux/pull/5392
This commit is contained in:
Mark Brown
commit
fe65ce845c
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@ -94,13 +94,14 @@ config SND_SOC_SOF_AMD_ACP63
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If unsure select "N".
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config SND_SOC_SOF_AMD_ACP70
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tristate "SOF support for ACP7.0 platform"
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tristate "SOF support for ACP7.0/ACP7.1 platforms"
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depends on SND_SOC_SOF_PCI
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depends on AMD_NODE
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select SND_SOC_SOF_AMD_COMMON
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select SND_SOC_SOF_AMD_SOUNDWIRE_LINK_BASELINE
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help
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Select this option for SOF support on
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AMD ACP7.0 version based platforms.
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Say Y if you want to enable SOF on ACP7.0 based platform.
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AMD ACP7.0/ACP7.1 version based platforms.
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Say Y if you want to enable SOF on ACP7.0/ACP7.1 based platforms.
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endif
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@ -130,4 +130,14 @@
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#define ACP_SW0_EN 0x3000
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#define ACP_SW1_EN 0x3C00
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#define ACP70_PME_EN 0x1400
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#define ACP70_EXTERNAL_INTR_CNTL1 0x1A08
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#define ACP70_SW0_WAKE_EN 0x1458
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#define ACP70_SW1_WAKE_EN 0x1460
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#define ACP70_SDW_HOST_WAKE_MASK 0x0C00000
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#define ACP70_SDW0_HOST_WAKE_STAT BIT(24)
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#define ACP70_SDW1_HOST_WAKE_STAT BIT(25)
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#define ACP70_SDW0_PME_STAT BIT(26)
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#define ACP70_SDW1_PME_STAT BIT(27)
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#endif
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@ -58,6 +58,7 @@ static void init_dma_descriptor(struct acp_dev_data *adata)
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switch (acp_data->pci_rev) {
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case ACP70_PCI_ID:
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case ACP71_PCI_ID:
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acp_dma_desc_base_addr = ACP70_DMA_DESC_BASE_ADDR;
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acp_dma_desc_max_num_dscr = ACP70_DMA_DESC_MAX_NUM_DSCR;
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break;
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@ -97,6 +98,7 @@ static int config_dma_channel(struct acp_dev_data *adata, unsigned int ch,
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switch (acp_data->pci_rev) {
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case ACP70_PCI_ID:
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case ACP71_PCI_ID:
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acp_dma_cntl_0 = ACP70_DMA_CNTL_0;
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acp_dma_ch_rst_sts = ACP70_DMA_CH_RST_STS;
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acp_dma_dscr_err_sts_0 = ACP70_DMA_ERR_STS_0;
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@ -336,6 +338,7 @@ int acp_dma_status(struct acp_dev_data *adata, unsigned char ch)
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switch (adata->pci_rev) {
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case ACP70_PCI_ID:
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case ACP71_PCI_ID:
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acp_dma_ch_sts = ACP70_DMA_CH_STS;
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break;
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default:
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@ -383,6 +386,69 @@ static int acp_memory_init(struct snd_sof_dev *sdev)
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return 0;
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}
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static void amd_sof_handle_acp70_sdw_wake_event(struct acp_dev_data *adata)
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{
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struct amd_sdw_manager *amd_manager;
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if (adata->acp70_sdw0_wake_event) {
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amd_manager = dev_get_drvdata(&adata->sdw->pdev[0]->dev);
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if (amd_manager)
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pm_request_resume(amd_manager->dev);
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adata->acp70_sdw0_wake_event = 0;
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}
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if (adata->acp70_sdw1_wake_event) {
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amd_manager = dev_get_drvdata(&adata->sdw->pdev[1]->dev);
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if (amd_manager)
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pm_request_resume(amd_manager->dev);
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adata->acp70_sdw1_wake_event = 0;
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}
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}
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static int amd_sof_check_and_handle_acp70_sdw_wake_irq(struct snd_sof_dev *sdev)
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{
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const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata);
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struct acp_dev_data *adata = sdev->pdata->hw_pdata;
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u32 ext_intr_stat1;
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int irq_flag = 0;
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bool sdw_wake_irq = false;
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ext_intr_stat1 = snd_sof_dsp_read(sdev, ACP_DSP_BAR, desc->ext_intr_stat1);
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if (ext_intr_stat1 & ACP70_SDW0_HOST_WAKE_STAT) {
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snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->ext_intr_stat1,
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ACP70_SDW0_HOST_WAKE_STAT);
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adata->acp70_sdw0_wake_event = true;
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sdw_wake_irq = true;
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}
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if (ext_intr_stat1 & ACP70_SDW1_HOST_WAKE_STAT) {
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snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->ext_intr_stat1,
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ACP70_SDW1_HOST_WAKE_STAT);
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adata->acp70_sdw1_wake_event = true;
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sdw_wake_irq = true;
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}
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if (ext_intr_stat1 & ACP70_SDW0_PME_STAT) {
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snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP70_SW0_WAKE_EN, 0);
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snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->ext_intr_stat1, ACP70_SDW0_PME_STAT);
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adata->acp70_sdw0_wake_event = true;
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sdw_wake_irq = true;
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}
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if (ext_intr_stat1 & ACP70_SDW1_PME_STAT) {
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snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP70_SW1_WAKE_EN, 0);
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snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->ext_intr_stat1, ACP70_SDW1_PME_STAT);
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adata->acp70_sdw1_wake_event = true;
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sdw_wake_irq = true;
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}
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if (sdw_wake_irq) {
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amd_sof_handle_acp70_sdw_wake_event(adata);
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irq_flag = 1;
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}
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return irq_flag;
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}
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static irqreturn_t acp_irq_thread(int irq, void *context)
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{
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struct snd_sof_dev *sdev = context;
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@ -415,7 +481,7 @@ static irqreturn_t acp_irq_handler(int irq, void *dev_id)
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struct acp_dev_data *adata = sdev->pdata->hw_pdata;
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unsigned int base = desc->dsp_intr_base;
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unsigned int val;
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int irq_flag = 0;
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int irq_flag = 0, wake_irq_flag = 0;
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val = snd_sof_dsp_read(sdev, ACP_DSP_BAR, base + DSP_SW_INTR_STAT_OFFSET);
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if (val & ACP_DSP_TO_HOST_IRQ) {
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@ -453,8 +519,14 @@ static irqreturn_t acp_irq_handler(int irq, void *dev_id)
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schedule_work(&amd_manager->amd_sdw_irq_thread);
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irq_flag = 1;
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}
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switch (adata->pci_rev) {
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case ACP70_PCI_ID:
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case ACP71_PCI_ID:
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wake_irq_flag = amd_sof_check_and_handle_acp70_sdw_wake_irq(sdev);
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break;
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}
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}
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if (irq_flag)
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if (irq_flag || wake_irq_flag)
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return IRQ_HANDLED;
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else
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return IRQ_NONE;
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@ -486,6 +558,7 @@ static int acp_power_on(struct snd_sof_dev *sdev)
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acp_pgfsm_cntl_mask = ACP6X_PGFSM_CNTL_POWER_ON_MASK;
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break;
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case ACP70_PCI_ID:
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case ACP71_PCI_ID:
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acp_pgfsm_status_mask = ACP70_PGFSM_STATUS_MASK;
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acp_pgfsm_cntl_mask = ACP70_PGFSM_CNTL_POWER_ON_MASK;
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break;
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@ -507,7 +580,6 @@ static int acp_power_on(struct snd_sof_dev *sdev)
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static int acp_reset(struct snd_sof_dev *sdev)
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{
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const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata);
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unsigned int val;
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int ret;
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@ -528,14 +600,6 @@ static int acp_reset(struct snd_sof_dev *sdev)
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if (ret < 0)
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dev_err(sdev->dev, "timeout in releasing reset\n");
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if (desc->acp_clkmux_sel)
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snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->acp_clkmux_sel, ACP_CLOCK_ACLK);
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if (desc->ext_intr_enb)
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snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->ext_intr_enb, 0x01);
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if (desc->ext_intr_cntl)
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snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->ext_intr_cntl, ACP_ERROR_IRQ_MASK);
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return ret;
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}
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@ -566,9 +630,13 @@ static int acp_dsp_reset(struct snd_sof_dev *sdev)
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static int acp_init(struct snd_sof_dev *sdev)
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{
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const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata);
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struct acp_dev_data *acp_data;
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unsigned int sdw0_wake_en, sdw1_wake_en;
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int ret;
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/* power on */
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acp_data = sdev->pdata->hw_pdata;
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ret = acp_power_on(sdev);
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if (ret) {
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dev_err(sdev->dev, "ACP power on failed\n");
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@ -577,7 +645,32 @@ static int acp_init(struct snd_sof_dev *sdev)
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snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_CONTROL, 0x01);
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/* Reset */
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return acp_reset(sdev);
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ret = acp_reset(sdev);
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if (ret)
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return ret;
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if (desc->acp_clkmux_sel)
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snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->acp_clkmux_sel, ACP_CLOCK_ACLK);
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if (desc->ext_intr_enb)
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snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->ext_intr_enb, 0x01);
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if (desc->ext_intr_cntl)
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snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->ext_intr_cntl, ACP_ERROR_IRQ_MASK);
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switch (acp_data->pci_rev) {
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case ACP70_PCI_ID:
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case ACP71_PCI_ID:
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sdw0_wake_en = snd_sof_dsp_read(sdev, ACP_DSP_BAR, ACP70_SW0_WAKE_EN);
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sdw1_wake_en = snd_sof_dsp_read(sdev, ACP_DSP_BAR, ACP70_SW1_WAKE_EN);
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if (sdw0_wake_en || sdw1_wake_en)
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snd_sof_dsp_update_bits(sdev, ACP_DSP_BAR, ACP70_EXTERNAL_INTR_CNTL1,
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ACP70_SDW_HOST_WAKE_MASK, ACP70_SDW_HOST_WAKE_MASK);
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snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP70_PME_EN, 1);
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break;
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}
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return 0;
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}
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static bool check_acp_sdw_enable_status(struct snd_sof_dev *sdev)
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@ -616,8 +709,12 @@ int amd_sof_acp_suspend(struct snd_sof_dev *sdev, u32 target_state)
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dev_err(sdev->dev, "ACP Reset failed\n");
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return ret;
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}
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if (acp_data->pci_rev == ACP70_PCI_ID)
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switch (acp_data->pci_rev) {
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case ACP70_PCI_ID:
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case ACP71_PCI_ID:
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enable = true;
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break;
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}
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snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_CONTROL, enable);
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return 0;
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@ -637,9 +734,15 @@ int amd_sof_acp_resume(struct snd_sof_dev *sdev)
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return ret;
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}
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return acp_memory_init(sdev);
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} else {
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return acp_dsp_reset(sdev);
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}
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switch (acp_data->pci_rev) {
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case ACP70_PCI_ID:
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case ACP71_PCI_ID:
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snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP70_PME_EN, 1);
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break;
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}
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return acp_dsp_reset(sdev);
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}
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EXPORT_SYMBOL_NS(amd_sof_acp_resume, "SND_SOC_SOF_AMD_COMMON");
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@ -74,6 +74,7 @@
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#define ACP_RMB_PCI_ID 0x6F
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#define ACP63_PCI_ID 0x63
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#define ACP70_PCI_ID 0x70
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#define ACP71_PCI_ID 0x71
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#define HOST_BRIDGE_CZN 0x1630
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#define HOST_BRIDGE_VGH 0x1645
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@ -109,9 +110,11 @@
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#define ACP_SDW0_IRQ_MASK BIT(21)
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#define ACP_SDW1_IRQ_MASK BIT(2)
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#define SDW_ACPI_ADDR_ACP63 5
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#define SDW_ACPI_ADDR_ACP70 SDW_ACPI_ADDR_ACP63
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#define ACP_DEFAULT_SRAM_LENGTH 0x00080000
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#define ACP_SRAM_PAGE_COUNT 128
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#define ACP6X_SDW_MAX_MANAGER_COUNT 2
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#define ACP70_SDW_MAX_MANAGER_COUNT ACP6X_SDW_MAX_MANAGER_COUNT
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enum clock_source {
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ACP_CLOCK_96M = 0,
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@ -260,6 +263,10 @@ struct acp_dev_data {
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bool is_dram_in_use;
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bool is_sram_in_use;
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bool sdw_en_stat;
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/* acp70_sdw0_wake_event flag set to true when wake irq asserted for SW0 instance */
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bool acp70_sdw0_wake_event;
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/* acp70_sdw1_wake_event flag set to true when wake irq asserted for SW1 instance */
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bool acp70_sdw1_wake_event;
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unsigned int pci_rev;
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};
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@ -33,12 +33,15 @@ static const struct sof_amd_acp_desc acp70_chip_info = {
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.ext_intr_cntl = ACP70_EXTERNAL_INTR_CNTL,
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.ext_intr_stat = ACP70_EXT_INTR_STAT,
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.ext_intr_stat1 = ACP70_EXT_INTR_STAT1,
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.acp_error_stat = ACP70_ERROR_STATUS,
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.dsp_intr_base = ACP70_DSP_SW_INTR_BASE,
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.acp_sw0_i2s_err_reason = ACP7X_SW0_I2S_ERROR_REASON,
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.sram_pte_offset = ACP70_SRAM_PTE_OFFSET,
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.hw_semaphore_offset = ACP70_AXI2DAGB_SEM_0,
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.fusion_dsp_offset = ACP70_DSP_FUSION_RUNSTALL,
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.probe_reg_offset = ACP70_FUTURE_REG_ACLK_0,
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.sdw_max_link_count = ACP70_SDW_MAX_MANAGER_COUNT,
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.sdw_acpi_dev_addr = SDW_ACPI_ADDR_ACP70,
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.reg_start_addr = ACP70_REG_START,
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.reg_end_addr = ACP70_REG_END,
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};
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@ -70,8 +73,13 @@ static int acp70_pci_probe(struct pci_dev *pci, const struct pci_device_id *pci_
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{
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unsigned int flag;
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if (pci->revision != ACP70_PCI_ID)
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switch (pci->revision) {
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case ACP70_PCI_ID:
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case ACP71_PCI_ID:
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break;
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default:
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return -ENODEV;
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}
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flag = snd_amd_acp_find_config(pci);
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if (flag != FLAG_AMD_SOF && flag != FLAG_AMD_SOF_ONLY_DMIC)
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