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riscv: fix RVG_SYSTEM_CSR_MASK width mask

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RVG_SYSTEM_CSR_MASK should be 12 bits [31:20], shifted down by 20 bits.
Replace GENMASK(12, 0) by GENMASK(11, 0).

Fixes: cd05483724 ("riscv: Allocate user's vector context in the first-use trap")
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Reviewed-by: Jisheng Zhang <jszhang@kernel.org>
Link: https://patch.msgid.link/20260911194233.3379532-1-aurelien@aurel32.net
Signed-off-by: Paul Walmsley <pjw@kernel.org>
This commit is contained in:
Aurelien Jarno 2026-10-05 19:02:53 -06:00 committed by Paul Walmsley
parent 30755e71ab
commit f89e5ee4d8
1 changed files with 1 additions and 1 deletions
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2
arch/riscv/include/asm/insn.h
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@ -142,7 +142,7 @@
#define RVG_OPCODE_JAL 0x6f
#define RVG_OPCODE_SYSTEM 0x73
#define RVG_SYSTEM_CSR_OFF 20
#define RVG_SYSTEM_CSR_MASK GENMASK(12, 0)
#define RVG_SYSTEM_CSR_MASK GENMASK(11, 0)
/* parts of opcode for RVF, RVD and RVQ */
#define RVFDQ_FL_FS_WIDTH_OFF 12