From f89e5ee4d8c6cd56499cd87e550d4d4e19cf7e17 Mon Sep 17 00:00:00 2001 From: Aurelien Jarno Date: Mon, 5 Oct 2026 19:02:53 -0600 Subject: [PATCH] riscv: fix RVG_SYSTEM_CSR_MASK width mask RVG_SYSTEM_CSR_MASK should be 12 bits [31:20], shifted down by 20 bits. Replace GENMASK(12, 0) by GENMASK(11, 0). Fixes: cd054837243b ("riscv: Allocate user's vector context in the first-use trap") Signed-off-by: Aurelien Jarno Reviewed-by: Jisheng Zhang Link: https://patch.msgid.link/20260911194233.3379532-1-aurelien@aurel32.net Signed-off-by: Paul Walmsley --- arch/riscv/include/asm/insn.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/riscv/include/asm/insn.h b/arch/riscv/include/asm/insn.h index c3005573e8c9..ad348d8b8857 100644 --- a/arch/riscv/include/asm/insn.h +++ b/arch/riscv/include/asm/insn.h @@ -142,7 +142,7 @@ #define RVG_OPCODE_JAL 0x6f #define RVG_OPCODE_SYSTEM 0x73 #define RVG_SYSTEM_CSR_OFF 20 -#define RVG_SYSTEM_CSR_MASK GENMASK(12, 0) +#define RVG_SYSTEM_CSR_MASK GENMASK(11, 0) /* parts of opcode for RVF, RVD and RVQ */ #define RVFDQ_FL_FS_WIDTH_OFF 12