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clk: renesas: Updates for v6.19 (take two)
- Add GPU clocks on R-Car V3U, - Add USB3.0 clocks and resets on RZ/V2H and RZ/V2N, - Add more serial (RSCI) clocks and resets on RZ/G3E, - Add SPI clocks on RZ/T2H and RZ/N2H, - Miscellaneous fixes and improvements. -----BEGIN PGP SIGNATURE----- iHUEABYKAB0WIQQ9qaHoIs/1I4cXmEiKwlD9ZEnxcAUCaRcB/wAKCRCKwlD9ZEnx cK8AAQDJjBIawXyufGkqBaayDycHAQL9/l9hlQPO4XcTi4oTSgEA/O3R9s7X0XkV CjYHLst7M0JjwDUWk1kDKm2GkgBdbgA= =kEdp -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQJIBAABCAAyFiEE9L57QeeUxqYDyoaDrQKIl8bklSUFAmkeD1cUHHN3Ym95ZEBj aHJvbWl1bS5vcmcACgkQrQKIl8bklSWgNg/+No64tB5V47dq+Gcd/XvFbMPPCfFQ dSzY5w8u7CrpyUBG3gkk7Mi7/2Y9eUWZX/hgZnIZq3fSKNFE6MoVMjG4OPfMBvmr F2klOzTs3QpWF9DcYa7gjJjMuC2SR6Ry6deFZNwIBuA8YpkSn8Jzc9Mdiv5pWRXu GZpeeNre7YLEG6qUJpJAamHsQ5HTqc4k0NL9yEV8B/uReEquG8DSwNDfOWr/GRUi hKU4QO93iJRvXj/LrREpFJ1ONi7uS5c7VkOhL8kyJjUTxZv6rkQksh6zw2vSB1C/ nDWdco7JXvvHu/qtBCBn0MfOyf4xkYVWQIST8Q8L/O+vKVMWsscIRu7LkxEJKAZc rlWv2ywjH7xfMJjK/Pp71/mu8beM9nqVnx0VFU9ikozf8zxGLomCu636Q/3AykB3 U7tVf6Y4HUyLZ9PVL1vp850CVbCHvNhSMct9cs8FK7iA1ughJ1miBw/V64avqKME 5py2DpGeh4dxNKK7+o2/5q8bE+KQ6qauU8pIDVC/6I71Ce51W1BOMt3vwBWVTTfh LFHcerFZOAAwZjARfOZrmGgU42H9xNKm7H7ZDn0/f+BOaNlbqmrtr3Av5qrXlhpD MH2wY5h9NVE22KTSP+5UilEGqMaK7+EoUTHZWevzsiJjUYytWIGFYAouN1ave2aB 2GFLg57f0aUiBhI= =RQrw -----END PGP SIGNATURE----- Merge tag 'renesas-clk-for-v6.19-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas Pull Renesas clk driver updates from Geert Uytterhoeven: - Add GPU clocks on R-Car V3U - Add USB3.0 clocks and resets on RZ/V2H and RZ/V2N - Add more serial (RSCI) clocks and resets on RZ/G3E - Add SPI clocks on RZ/T2H and RZ/N2H * tag 'renesas-clk-for-v6.19-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers: clk: renesas: r9a09g077: Add SPI module clocks clk: renesas: r9a09g056: Add USB3.0 clocks/resets clk: renesas: r9a09g057: Add USB3.0 clocks/resets clk: renesas: r9a09g047: Add RSCI clocks/resets dt-bindings: clock: renesas,r9a09g056-cpg: Add USB3.0 core clocks dt-bindings: clock: renesas,r9a09g057-cpg: Add USB3.0 core clocks clk: renesas: r9a06g032: Fix memory leak in error path clk: renesas: r9a09g077: Use devm_ helpers for divider clock registration clk: renesas: r9a09g077: Remove stray blank line clk: renesas: r9a09g077: Propagate rate changes to parent clocks clk: renesas: r8a779a0: Add 3DGE module clock clk: renesas: r8a779a0: Add ZG Core clock clk: renesas: rcar-gen4: Add support for clock dividers in FRQCRB dt-bindings: clock: r8a779a0: Add ZG core clock
This commit is contained in:
Stephen Boyd
commit
f700b882a7
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@ -26,7 +26,7 @@
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enum clk_ids {
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/* Core Clock Outputs exported to DT */
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LAST_DT_CORE_CLK = R8A779A0_CLK_OSC,
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LAST_DT_CORE_CLK = R8A779A0_CLK_ZG,
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/* External Input Clocks */
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CLK_EXTAL,
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@ -39,6 +39,7 @@ enum clk_ids {
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CLK_PLL21,
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CLK_PLL30,
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CLK_PLL31,
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CLK_PLL4,
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CLK_PLL5,
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CLK_PLL1_DIV2,
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CLK_PLL20_DIV2,
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@ -65,6 +66,7 @@ enum clk_ids {
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#define CPG_PLL21CR 0x0838 /* PLL21 Control Register */
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#define CPG_PLL30CR 0x083c /* PLL30 Control Register */
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#define CPG_PLL31CR 0x0840 /* PLL31 Control Register */
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#define CPG_PLL4CR 0x0844 /* PLL4 Control Register */
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static const struct cpg_core_clk r8a779a0_core_clks[] __initconst = {
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/* External Clock Inputs */
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@ -79,6 +81,7 @@ static const struct cpg_core_clk r8a779a0_core_clks[] __initconst = {
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DEF_PLL(".pll21", CLK_PLL21, CPG_PLL21CR),
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DEF_PLL(".pll30", CLK_PLL30, CPG_PLL30CR),
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DEF_PLL(".pll31", CLK_PLL31, CPG_PLL31CR),
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DEF_PLL(".pll4", CLK_PLL4, CPG_PLL4CR),
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DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
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DEF_FIXED(".pll20_div2", CLK_PLL20_DIV2, CLK_PLL20, 2, 1),
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@ -98,6 +101,7 @@ static const struct cpg_core_clk r8a779a0_core_clks[] __initconst = {
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/* Core Clock Outputs */
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DEF_GEN4_Z("z0", R8A779A0_CLK_Z0, CLK_TYPE_GEN4_Z, CLK_PLL20, 2, 0),
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DEF_GEN4_Z("z1", R8A779A0_CLK_Z1, CLK_TYPE_GEN4_Z, CLK_PLL21, 2, 8),
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DEF_GEN4_Z("zg", R8A779A0_CLK_ZG, CLK_TYPE_GEN4_Z, CLK_PLL4, 2, 88),
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DEF_FIXED("zx", R8A779A0_CLK_ZX, CLK_PLL20_DIV2, 2, 1),
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DEF_FIXED("s1d1", R8A779A0_CLK_S1D1, CLK_S1, 1, 1),
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DEF_FIXED("s1d2", R8A779A0_CLK_S1D2, CLK_S1, 2, 1),
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@ -138,6 +142,7 @@ static const struct cpg_core_clk r8a779a0_core_clks[] __initconst = {
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};
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static const struct mssr_mod_clk r8a779a0_mod_clks[] __initconst = {
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DEF_MOD("3dge", 0, R8A779A0_CLK_ZG),
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DEF_MOD("isp0", 16, R8A779A0_CLK_S1D1),
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DEF_MOD("isp1", 17, R8A779A0_CLK_S1D1),
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DEF_MOD("isp2", 18, R8A779A0_CLK_S1D1),
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@ -1333,9 +1333,9 @@ static int __init r9a06g032_clocks_probe(struct platform_device *pdev)
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if (IS_ERR(mclk))
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return PTR_ERR(mclk);
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clocks->reg = of_iomap(np, 0);
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if (WARN_ON(!clocks->reg))
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return -ENOMEM;
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clocks->reg = devm_of_iomap(dev, np, 0, NULL);
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if (IS_ERR(clocks->reg))
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return PTR_ERR(clocks->reg);
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r9a06g032_init_h2mode(clocks);
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@ -44,6 +44,9 @@ enum clk_ids {
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CLK_PLLCLN_DIV8,
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CLK_PLLCLN_DIV16,
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CLK_PLLCLN_DIV20,
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CLK_PLLCLN_DIV64,
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CLK_PLLCLN_DIV256,
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CLK_PLLCLN_DIV1024,
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CLK_PLLDTY_ACPU,
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CLK_PLLDTY_ACPU_DIV2,
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CLK_PLLDTY_ACPU_DIV4,
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@ -142,6 +145,9 @@ static const struct cpg_core_clk r9a09g047_core_clks[] __initconst = {
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DEF_FIXED(".pllcln_div8", CLK_PLLCLN_DIV8, CLK_PLLCLN, 1, 8),
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DEF_FIXED(".pllcln_div16", CLK_PLLCLN_DIV16, CLK_PLLCLN, 1, 16),
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DEF_FIXED(".pllcln_div20", CLK_PLLCLN_DIV20, CLK_PLLCLN, 1, 20),
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DEF_FIXED(".pllcln_div64", CLK_PLLCLN_DIV64, CLK_PLLCLN, 1, 64),
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DEF_FIXED(".pllcln_div256", CLK_PLLCLN_DIV256, CLK_PLLCLN, 1, 256),
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DEF_FIXED(".pllcln_div1024", CLK_PLLCLN_DIV1024, CLK_PLLCLN, 1, 1024),
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DEF_DDIV(".plldty_acpu", CLK_PLLDTY_ACPU, CLK_PLLDTY, CDDIV0_DIVCTL2, dtable_2_64),
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DEF_FIXED(".plldty_acpu_div2", CLK_PLLDTY_ACPU_DIV2, CLK_PLLDTY_ACPU, 1, 2),
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@ -218,6 +224,106 @@ static const struct rzv2h_mod_clk r9a09g047_mod_clks[] __initconst = {
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BUS_MSTOP(5, BIT(13))),
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DEF_MOD("wdt_3_clk_loco", CLK_QEXTAL, 5, 2, 2, 18,
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BUS_MSTOP(5, BIT(13))),
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DEF_MOD("rsci0_pclk", CLK_PLLCLN_DIV16, 5, 13, 2, 29,
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BUS_MSTOP(11, BIT(3))),
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DEF_MOD("rsci0_tclk", CLK_PLLCLN_DIV16, 5, 14, 2, 30,
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BUS_MSTOP(11, BIT(3))),
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DEF_MOD("rsci0_ps_ps3_n", CLK_PLLCLN_DIV1024, 5, 15, 2, 31,
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BUS_MSTOP(11, BIT(3))),
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DEF_MOD("rsci0_ps_ps2_n", CLK_PLLCLN_DIV256, 6, 0, 3, 0,
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BUS_MSTOP(11, BIT(3))),
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DEF_MOD("rsci0_ps_ps1_n", CLK_PLLCLN_DIV64, 6, 1, 3, 1,
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BUS_MSTOP(11, BIT(3))),
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DEF_MOD("rsci1_pclk", CLK_PLLCLN_DIV16, 6, 2, 3, 2,
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BUS_MSTOP(11, BIT(4))),
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DEF_MOD("rsci1_tclk", CLK_PLLCLN_DIV16, 6, 3, 3, 3,
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BUS_MSTOP(11, BIT(4))),
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DEF_MOD("rsci1_ps_ps3_n", CLK_PLLCLN_DIV1024, 6, 4, 3, 4,
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BUS_MSTOP(11, BIT(4))),
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DEF_MOD("rsci1_ps_ps2_n", CLK_PLLCLN_DIV256, 6, 5, 3, 5,
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BUS_MSTOP(11, BIT(4))),
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DEF_MOD("rsci1_ps_ps1_n", CLK_PLLCLN_DIV64, 6, 6, 3, 6,
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BUS_MSTOP(11, BIT(4))),
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DEF_MOD("rsci2_pclk", CLK_PLLCLN_DIV16, 6, 7, 3, 7,
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BUS_MSTOP(11, BIT(5))),
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DEF_MOD("rsci2_tclk", CLK_PLLCLN_DIV16, 6, 8, 3, 8,
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BUS_MSTOP(11, BIT(5))),
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DEF_MOD("rsci2_ps_ps3_n", CLK_PLLCLN_DIV1024, 6, 9, 3, 9,
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BUS_MSTOP(11, BIT(5))),
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DEF_MOD("rsci2_ps_ps2_n", CLK_PLLCLN_DIV256, 6, 10, 3, 10,
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BUS_MSTOP(11, BIT(5))),
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DEF_MOD("rsci2_ps_ps1_n", CLK_PLLCLN_DIV64, 6, 11, 3, 11,
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BUS_MSTOP(11, BIT(5))),
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DEF_MOD("rsci3_pclk", CLK_PLLCLN_DIV16, 6, 12, 3, 12,
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BUS_MSTOP(11, BIT(6))),
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DEF_MOD("rsci3_tclk", CLK_PLLCLN_DIV16, 6, 13, 3, 13,
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BUS_MSTOP(11, BIT(6))),
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DEF_MOD("rsci3_ps_ps3_n", CLK_PLLCLN_DIV1024, 6, 14, 3, 14,
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BUS_MSTOP(11, BIT(6))),
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DEF_MOD("rsci3_ps_ps2_n", CLK_PLLCLN_DIV256, 6, 15, 3, 15,
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BUS_MSTOP(11, BIT(6))),
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DEF_MOD("rsci3_ps_ps1_n", CLK_PLLCLN_DIV64, 7, 0, 3, 16,
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BUS_MSTOP(11, BIT(6))),
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DEF_MOD("rsci4_pclk", CLK_PLLCLN_DIV16, 7, 1, 3, 17,
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BUS_MSTOP(11, BIT(7))),
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DEF_MOD("rsci4_tclk", CLK_PLLCLN_DIV16, 7, 2, 3, 18,
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BUS_MSTOP(11, BIT(7))),
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DEF_MOD("rsci4_ps_ps3_n", CLK_PLLCLN_DIV1024, 7, 3, 3, 19,
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BUS_MSTOP(11, BIT(7))),
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DEF_MOD("rsci4_ps_ps2_n", CLK_PLLCLN_DIV256, 7, 4, 3, 20,
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BUS_MSTOP(11, BIT(7))),
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DEF_MOD("rsci4_ps_ps1_n", CLK_PLLCLN_DIV64, 7, 5, 3, 21,
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BUS_MSTOP(11, BIT(7))),
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DEF_MOD("rsci5_pclk", CLK_PLLCLN_DIV16, 7, 6, 3, 22,
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BUS_MSTOP(11, BIT(8))),
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DEF_MOD("rsci5_tclk", CLK_PLLCLN_DIV16, 7, 7, 3, 23,
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BUS_MSTOP(11, BIT(8))),
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DEF_MOD("rsci5_ps_ps3_n", CLK_PLLCLN_DIV1024, 7, 8, 3, 24,
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BUS_MSTOP(11, BIT(8))),
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DEF_MOD("rsci5_ps_ps2_n", CLK_PLLCLN_DIV256, 7, 9, 3, 25,
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BUS_MSTOP(11, BIT(8))),
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DEF_MOD("rsci5_ps_ps1_n", CLK_PLLCLN_DIV64, 7, 10, 3, 26,
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BUS_MSTOP(11, BIT(8))),
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DEF_MOD("rsci6_pclk", CLK_PLLCLN_DIV16, 7, 11, 3, 27,
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BUS_MSTOP(11, BIT(9))),
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DEF_MOD("rsci6_tclk", CLK_PLLCLN_DIV16, 7, 12, 3, 28,
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BUS_MSTOP(11, BIT(9))),
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DEF_MOD("rsci6_ps_ps3_n", CLK_PLLCLN_DIV1024, 7, 13, 3, 29,
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BUS_MSTOP(11, BIT(9))),
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DEF_MOD("rsci6_ps_ps2_n", CLK_PLLCLN_DIV256, 7, 14, 3, 30,
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BUS_MSTOP(11, BIT(9))),
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DEF_MOD("rsci6_ps_ps1_n", CLK_PLLCLN_DIV64, 7, 15, 3, 31,
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BUS_MSTOP(11, BIT(9))),
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DEF_MOD("rsci7_pclk", CLK_PLLCLN_DIV16, 8, 0, 4, 0,
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BUS_MSTOP(11, BIT(10))),
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DEF_MOD("rsci7_tclk", CLK_PLLCLN_DIV16, 8, 1, 4, 1,
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BUS_MSTOP(11, BIT(10))),
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DEF_MOD("rsci7_ps_ps3_n", CLK_PLLCLN_DIV1024, 8, 2, 4, 2,
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BUS_MSTOP(11, BIT(10))),
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DEF_MOD("rsci7_ps_ps2_n", CLK_PLLCLN_DIV256, 8, 3, 4, 3,
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BUS_MSTOP(11, BIT(10))),
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DEF_MOD("rsci7_ps_ps1_n", CLK_PLLCLN_DIV64, 8, 4, 4, 4,
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BUS_MSTOP(11, BIT(10))),
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DEF_MOD("rsci8_pclk", CLK_PLLCLN_DIV16, 8, 5, 4, 5,
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BUS_MSTOP(11, BIT(11))),
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DEF_MOD("rsci8_tclk", CLK_PLLCLN_DIV16, 8, 6, 4, 6,
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BUS_MSTOP(11, BIT(11))),
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DEF_MOD("rsci8_ps_ps3_n", CLK_PLLCLN_DIV1024, 8, 7, 4, 7,
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BUS_MSTOP(11, BIT(11))),
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DEF_MOD("rsci8_ps_ps2_n", CLK_PLLCLN_DIV256, 8, 8, 4, 8,
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BUS_MSTOP(11, BIT(11))),
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DEF_MOD("rsci8_ps_ps1_n", CLK_PLLCLN_DIV64, 8, 9, 4, 9,
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BUS_MSTOP(11, BIT(11))),
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DEF_MOD("rsci9_pclk", CLK_PLLCLN_DIV16, 8, 10, 4, 10,
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BUS_MSTOP(11, BIT(12))),
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DEF_MOD("rsci9_tclk", CLK_PLLCLN_DIV16, 8, 11, 4, 11,
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BUS_MSTOP(11, BIT(12))),
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DEF_MOD("rsci9_ps_ps3_n", CLK_PLLCLN_DIV1024, 8, 12, 4, 12,
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BUS_MSTOP(11, BIT(12))),
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DEF_MOD("rsci9_ps_ps2_n", CLK_PLLCLN_DIV256, 8, 13, 4, 13,
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BUS_MSTOP(11, BIT(12))),
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DEF_MOD("rsci9_ps_ps1_n", CLK_PLLCLN_DIV64, 8, 14, 4, 14,
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BUS_MSTOP(11, BIT(12))),
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DEF_MOD("scif_0_clk_pck", CLK_PLLCM33_DIV16, 8, 15, 4, 15,
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BUS_MSTOP(3, BIT(14))),
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DEF_MOD("i3c_0_pclkrw", CLK_PLLCLN_DIV16, 9, 0, 4, 16,
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@ -351,6 +457,26 @@ static const struct rzv2h_reset r9a09g047_resets[] __initconst = {
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DEF_RST(7, 6, 3, 7), /* WDT_1_RESET */
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DEF_RST(7, 7, 3, 8), /* WDT_2_RESET */
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DEF_RST(7, 8, 3, 9), /* WDT_3_RESET */
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DEF_RST(8, 1, 3, 18), /* RSCI0_PRESETN */
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DEF_RST(8, 2, 3, 19), /* RSCI0_TRESETN */
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DEF_RST(8, 3, 3, 20), /* RSCI1_PRESETN */
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DEF_RST(8, 4, 3, 21), /* RSCI1_TRESETN */
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DEF_RST(8, 5, 3, 22), /* RSCI2_PRESETN */
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DEF_RST(8, 6, 3, 23), /* RSCI2_TRESETN */
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DEF_RST(8, 7, 3, 24), /* RSCI3_PRESETN */
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DEF_RST(8, 8, 3, 25), /* RSCI3_TRESETN */
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DEF_RST(8, 9, 3, 26), /* RSCI4_PRESETN */
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DEF_RST(8, 10, 3, 27), /* RSCI4_TRESETN */
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DEF_RST(8, 11, 3, 28), /* RSCI5_PRESETN */
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DEF_RST(8, 12, 3, 29), /* RSCI5_TRESETN */
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DEF_RST(8, 13, 3, 30), /* RSCI6_PRESETN */
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DEF_RST(8, 14, 3, 31), /* RSCI6_TRESETN */
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DEF_RST(8, 15, 4, 0), /* RSCI7_PRESETN */
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DEF_RST(9, 0, 4, 1), /* RSCI7_TRESETN */
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DEF_RST(9, 1, 4, 2), /* RSCI8_PRESETN */
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DEF_RST(9, 2, 4, 3), /* RSCI8_TRESETN */
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DEF_RST(9, 3, 4, 4), /* RSCI9_PRESETN */
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DEF_RST(9, 4, 4, 5), /* RSCI9_TRESETN */
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DEF_RST(9, 5, 4, 6), /* SCIF_0_RST_SYSTEM_N */
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DEF_RST(9, 6, 4, 7), /* I3C_0_PRESETN */
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DEF_RST(9, 7, 4, 8), /* I3C_0_TRESETN */
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@ -17,7 +17,7 @@
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enum clk_ids {
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/* Core Clock Outputs exported to DT */
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LAST_DT_CORE_CLK = R9A09G056_SPI_CLK_SPI,
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LAST_DT_CORE_CLK = R9A09G056_USB3_0_CLKCORE,
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/* External Input Clocks */
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CLK_AUDIO_EXTAL,
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@ -226,6 +226,8 @@ static const struct cpg_core_clk r9a09g056_core_clks[] __initconst = {
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CLK_PLLETH_DIV_125_FIX, 1, 1),
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DEF_FIXED_MOD_STATUS("spi_clk_spi", R9A09G056_SPI_CLK_SPI, CLK_PLLCM33_XSPI, 1, 2,
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FIXED_MOD_CONF_XSPI),
|
||||
DEF_FIXED("usb3_0_ref_alt_clk_p", R9A09G056_USB3_0_REF_ALT_CLK_P, CLK_QEXTAL, 1, 1),
|
||||
DEF_FIXED("usb3_0_core_clk", R9A09G056_USB3_0_CLKCORE, CLK_QEXTAL, 1, 1),
|
||||
};
|
||||
|
||||
static const struct rzv2h_mod_clk r9a09g056_mod_clks[] __initconst = {
|
||||
|
|
@ -319,6 +321,10 @@ static const struct rzv2h_mod_clk r9a09g056_mod_clks[] __initconst = {
|
|||
BUS_MSTOP(8, BIT(4))),
|
||||
DEF_MOD("sdhi_2_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 14, 5, 14,
|
||||
BUS_MSTOP(8, BIT(4))),
|
||||
DEF_MOD("usb3_0_aclk", CLK_PLLDTY_DIV8, 10, 15, 5, 15,
|
||||
BUS_MSTOP(7, BIT(12))),
|
||||
DEF_MOD("usb3_0_pclk_usbtst", CLK_PLLDTY_ACPU_DIV4, 11, 0, 5, 16,
|
||||
BUS_MSTOP(7, BIT(14))),
|
||||
DEF_MOD("usb2_0_u2h0_hclk", CLK_PLLDTY_DIV8, 11, 3, 5, 19,
|
||||
BUS_MSTOP(7, BIT(7))),
|
||||
DEF_MOD("usb2_0_u2p_exr_cpuclk", CLK_PLLDTY_ACPU_DIV4, 11, 5, 5, 21,
|
||||
|
|
@ -426,6 +432,7 @@ static const struct rzv2h_reset r9a09g056_resets[] __initconst = {
|
|||
DEF_RST(10, 7, 4, 24), /* SDHI_0_IXRST */
|
||||
DEF_RST(10, 8, 4, 25), /* SDHI_1_IXRST */
|
||||
DEF_RST(10, 9, 4, 26), /* SDHI_2_IXRST */
|
||||
DEF_RST(10, 10, 4, 27), /* USB3_0_ARESETN */
|
||||
DEF_RST(10, 12, 4, 29), /* USB2_0_U2H0_HRESETN */
|
||||
DEF_RST(10, 14, 4, 31), /* USB2_0_U2P_EXL_SYSRST */
|
||||
DEF_RST(10, 15, 5, 0), /* USB2_0_PRESETN */
|
||||
|
|
|
|||
|
|
@ -17,7 +17,7 @@
|
|||
|
||||
enum clk_ids {
|
||||
/* Core Clock Outputs exported to DT */
|
||||
LAST_DT_CORE_CLK = R9A09G057_SPI_CLK_SPI,
|
||||
LAST_DT_CORE_CLK = R9A09G057_USB3_1_CLKCORE,
|
||||
|
||||
/* External Input Clocks */
|
||||
CLK_AUDIO_EXTAL,
|
||||
|
|
@ -235,6 +235,10 @@ static const struct cpg_core_clk r9a09g057_core_clks[] __initconst = {
|
|||
CLK_PLLETH_DIV_125_FIX, 1, 1),
|
||||
DEF_FIXED_MOD_STATUS("spi_clk_spi", R9A09G057_SPI_CLK_SPI, CLK_PLLCM33_XSPI, 1, 2,
|
||||
FIXED_MOD_CONF_XSPI),
|
||||
DEF_FIXED("usb3_0_ref_alt_clk_p", R9A09G057_USB3_0_REF_ALT_CLK_P, CLK_QEXTAL, 1, 1),
|
||||
DEF_FIXED("usb3_0_core_clk", R9A09G057_USB3_0_CLKCORE, CLK_QEXTAL, 1, 1),
|
||||
DEF_FIXED("usb3_1_ref_alt_clk_p", R9A09G057_USB3_1_REF_ALT_CLK_P, CLK_QEXTAL, 1, 1),
|
||||
DEF_FIXED("usb3_1_core_clk", R9A09G057_USB3_1_CLKCORE, CLK_QEXTAL, 1, 1),
|
||||
};
|
||||
|
||||
static const struct rzv2h_mod_clk r9a09g057_mod_clks[] __initconst = {
|
||||
|
|
@ -360,6 +364,14 @@ static const struct rzv2h_mod_clk r9a09g057_mod_clks[] __initconst = {
|
|||
BUS_MSTOP(8, BIT(4))),
|
||||
DEF_MOD("sdhi_2_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 14, 5, 14,
|
||||
BUS_MSTOP(8, BIT(4))),
|
||||
DEF_MOD("usb3_0_aclk", CLK_PLLDTY_DIV8, 10, 15, 5, 15,
|
||||
BUS_MSTOP(7, BIT(12))),
|
||||
DEF_MOD("usb3_0_pclk_usbtst", CLK_PLLDTY_ACPU_DIV4, 11, 0, 5, 16,
|
||||
BUS_MSTOP(7, BIT(14))),
|
||||
DEF_MOD("usb3_1_aclk", CLK_PLLDTY_DIV8, 11, 1, 5, 17,
|
||||
BUS_MSTOP(7, BIT(13))),
|
||||
DEF_MOD("usb3_1_pclk_usbtst", CLK_PLLDTY_ACPU_DIV4, 11, 2, 5, 18,
|
||||
BUS_MSTOP(7, BIT(15))),
|
||||
DEF_MOD("usb2_0_u2h0_hclk", CLK_PLLDTY_DIV8, 11, 3, 5, 19,
|
||||
BUS_MSTOP(7, BIT(7))),
|
||||
DEF_MOD("usb2_0_u2h1_hclk", CLK_PLLDTY_DIV8, 11, 4, 5, 20,
|
||||
|
|
@ -501,6 +513,8 @@ static const struct rzv2h_reset r9a09g057_resets[] __initconst = {
|
|||
DEF_RST(10, 7, 4, 24), /* SDHI_0_IXRST */
|
||||
DEF_RST(10, 8, 4, 25), /* SDHI_1_IXRST */
|
||||
DEF_RST(10, 9, 4, 26), /* SDHI_2_IXRST */
|
||||
DEF_RST(10, 10, 4, 27), /* USB3_0_ARESETN */
|
||||
DEF_RST(10, 11, 4, 28), /* USB3_1_ARESETN */
|
||||
DEF_RST(10, 12, 4, 29), /* USB2_0_U2H0_HRESETN */
|
||||
DEF_RST(10, 13, 4, 30), /* USB2_0_U2H1_HRESETN */
|
||||
DEF_RST(10, 14, 4, 31), /* USB2_0_U2P_EXL_SYSRST */
|
||||
|
|
|
|||
|
|
@ -46,8 +46,12 @@
|
|||
#define DIVCA55C2 CONF_PACK(SCKCR2, 10, 1)
|
||||
#define DIVCA55C3 CONF_PACK(SCKCR2, 11, 1)
|
||||
#define DIVCA55S CONF_PACK(SCKCR2, 12, 1)
|
||||
#define DIVSPI3ASYNC CONF_PACK(SCKCR2, 16, 2)
|
||||
#define DIVSCI5ASYNC CONF_PACK(SCKCR2, 18, 2)
|
||||
|
||||
#define DIVSPI0ASYNC CONF_PACK(SCKCR3, 0, 2)
|
||||
#define DIVSPI1ASYNC CONF_PACK(SCKCR3, 2, 2)
|
||||
#define DIVSPI2ASYNC CONF_PACK(SCKCR3, 4, 2)
|
||||
#define DIVSCI0ASYNC CONF_PACK(SCKCR3, 6, 2)
|
||||
#define DIVSCI1ASYNC CONF_PACK(SCKCR3, 8, 2)
|
||||
#define DIVSCI2ASYNC CONF_PACK(SCKCR3, 10, 2)
|
||||
|
|
@ -56,7 +60,6 @@
|
|||
|
||||
#define SEL_PLL CONF_PACK(SCKCR, 22, 1)
|
||||
|
||||
|
||||
enum rzt2h_clk_types {
|
||||
CLK_TYPE_RZT2H_DIV = CLK_TYPE_CUSTOM, /* Clock with divider */
|
||||
CLK_TYPE_RZT2H_MUX, /* Clock with clock source selector */
|
||||
|
|
@ -94,6 +97,10 @@ enum clk_ids {
|
|||
CLK_SCI3ASYNC,
|
||||
CLK_SCI4ASYNC,
|
||||
CLK_SCI5ASYNC,
|
||||
CLK_SPI0ASYNC,
|
||||
CLK_SPI1ASYNC,
|
||||
CLK_SPI2ASYNC,
|
||||
CLK_SPI3ASYNC,
|
||||
|
||||
/* Module Clocks */
|
||||
MOD_CLK_BASE,
|
||||
|
|
@ -154,6 +161,15 @@ static const struct cpg_core_clk r9a09g077_core_clks[] __initconst = {
|
|||
DEF_DIV(".sci5async", CLK_SCI5ASYNC, CLK_PLL4D1, DIVSCI5ASYNC,
|
||||
dtable_24_25_30_32),
|
||||
|
||||
DEF_DIV(".spi0async", CLK_SPI0ASYNC, CLK_PLL4D1, DIVSPI0ASYNC,
|
||||
dtable_24_25_30_32),
|
||||
DEF_DIV(".spi1async", CLK_SPI1ASYNC, CLK_PLL4D1, DIVSPI1ASYNC,
|
||||
dtable_24_25_30_32),
|
||||
DEF_DIV(".spi2async", CLK_SPI2ASYNC, CLK_PLL4D1, DIVSPI2ASYNC,
|
||||
dtable_24_25_30_32),
|
||||
DEF_DIV(".spi3async", CLK_SPI3ASYNC, CLK_PLL4D1, DIVSPI3ASYNC,
|
||||
dtable_24_25_30_32),
|
||||
|
||||
/* Core output clk */
|
||||
DEF_DIV("CA55C0", R9A09G077_CLK_CA55C0, CLK_SEL_CLK_PLL0, DIVCA55C0,
|
||||
dtable_1_2),
|
||||
|
|
@ -188,6 +204,9 @@ static const struct mssr_mod_clk r9a09g077_mod_clks[] __initconst = {
|
|||
DEF_MOD("sci4fck", 12, CLK_SCI4ASYNC),
|
||||
DEF_MOD("iic0", 100, R9A09G077_CLK_PCLKL),
|
||||
DEF_MOD("iic1", 101, R9A09G077_CLK_PCLKL),
|
||||
DEF_MOD("spi0", 104, CLK_SPI0ASYNC),
|
||||
DEF_MOD("spi1", 105, CLK_SPI1ASYNC),
|
||||
DEF_MOD("spi2", 106, CLK_SPI2ASYNC),
|
||||
DEF_MOD("adc0", 206, R9A09G077_CLK_PCLKH),
|
||||
DEF_MOD("adc1", 207, R9A09G077_CLK_PCLKH),
|
||||
DEF_MOD("adc2", 225, R9A09G077_CLK_PCLKM),
|
||||
|
|
@ -200,6 +219,7 @@ static const struct mssr_mod_clk r9a09g077_mod_clks[] __initconst = {
|
|||
DEF_MOD("gmac2", 417, R9A09G077_CLK_PCLKAM),
|
||||
DEF_MOD("sci5fck", 600, CLK_SCI5ASYNC),
|
||||
DEF_MOD("iic2", 601, R9A09G077_CLK_PCLKL),
|
||||
DEF_MOD("spi3", 602, CLK_SPI3ASYNC),
|
||||
DEF_MOD("sdhi0", 1212, R9A09G077_CLK_PCLKAM),
|
||||
DEF_MOD("sdhi1", 1213, R9A09G077_CLK_PCLKAM),
|
||||
};
|
||||
|
|
@ -220,27 +240,28 @@ r9a09g077_cpg_div_clk_register(struct device *dev,
|
|||
parent_name = __clk_get_name(parent);
|
||||
|
||||
if (core->dtable)
|
||||
clk_hw = clk_hw_register_divider_table(dev, core->name,
|
||||
parent_name, 0,
|
||||
addr,
|
||||
GET_SHIFT(core->conf),
|
||||
GET_WIDTH(core->conf),
|
||||
core->flag,
|
||||
core->dtable,
|
||||
&pub->rmw_lock);
|
||||
clk_hw = devm_clk_hw_register_divider_table(dev, core->name,
|
||||
parent_name,
|
||||
CLK_SET_RATE_PARENT,
|
||||
addr,
|
||||
GET_SHIFT(core->conf),
|
||||
GET_WIDTH(core->conf),
|
||||
core->flag,
|
||||
core->dtable,
|
||||
&pub->rmw_lock);
|
||||
else
|
||||
clk_hw = clk_hw_register_divider(dev, core->name,
|
||||
parent_name, 0,
|
||||
addr,
|
||||
GET_SHIFT(core->conf),
|
||||
GET_WIDTH(core->conf),
|
||||
core->flag, &pub->rmw_lock);
|
||||
clk_hw = devm_clk_hw_register_divider(dev, core->name,
|
||||
parent_name,
|
||||
CLK_SET_RATE_PARENT,
|
||||
addr,
|
||||
GET_SHIFT(core->conf),
|
||||
GET_WIDTH(core->conf),
|
||||
core->flag, &pub->rmw_lock);
|
||||
|
||||
if (IS_ERR(clk_hw))
|
||||
return ERR_CAST(clk_hw);
|
||||
|
||||
return clk_hw->clk;
|
||||
|
||||
}
|
||||
|
||||
static struct clk * __init
|
||||
|
|
|
|||
|
|
@ -257,7 +257,7 @@ static struct clk * __init cpg_pll_clk_register(const char *name,
|
|||
}
|
||||
|
||||
/*
|
||||
* Z0 Clock & Z1 Clock
|
||||
* Z0, Z1 and ZG Clock
|
||||
*/
|
||||
#define CPG_FRQCRB 0x00000804
|
||||
#define CPG_FRQCRB_KICK BIT(31)
|
||||
|
|
@ -389,9 +389,14 @@ static struct clk * __init cpg_z_clk_register(const char *name,
|
|||
|
||||
if (offset < 32) {
|
||||
zclk->reg = reg + CPG_FRQCRC0;
|
||||
} else {
|
||||
} else if (offset < 64) {
|
||||
zclk->reg = reg + CPG_FRQCRC1;
|
||||
offset -= 32;
|
||||
} else if (offset < 96) {
|
||||
zclk->reg = reg + CPG_FRQCRB;
|
||||
offset -= 64;
|
||||
} else {
|
||||
return ERR_PTR(-EINVAL);
|
||||
}
|
||||
zclk->kick_reg = reg + CPG_FRQCRB;
|
||||
zclk->hw.init = &init;
|
||||
|
|
|
|||
|
|
@ -51,5 +51,6 @@
|
|||
#define R8A779A0_CLK_CBFUSA 40
|
||||
#define R8A779A0_CLK_R 41
|
||||
#define R8A779A0_CLK_OSC 42
|
||||
#define R8A779A0_CLK_ZG 43
|
||||
|
||||
#endif /* __DT_BINDINGS_CLOCK_R8A779A0_CPG_MSSR_H__ */
|
||||
|
|
|
|||
|
|
@ -21,5 +21,7 @@
|
|||
#define R9A09G056_GBETH_0_CLK_PTP_REF_I 10
|
||||
#define R9A09G056_GBETH_1_CLK_PTP_REF_I 11
|
||||
#define R9A09G056_SPI_CLK_SPI 12
|
||||
#define R9A09G056_USB3_0_REF_ALT_CLK_P 13
|
||||
#define R9A09G056_USB3_0_CLKCORE 14
|
||||
|
||||
#endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G056_CPG_H__ */
|
||||
|
|
|
|||
|
|
@ -22,5 +22,9 @@
|
|||
#define R9A09G057_GBETH_0_CLK_PTP_REF_I 11
|
||||
#define R9A09G057_GBETH_1_CLK_PTP_REF_I 12
|
||||
#define R9A09G057_SPI_CLK_SPI 13
|
||||
#define R9A09G057_USB3_0_REF_ALT_CLK_P 14
|
||||
#define R9A09G057_USB3_0_CLKCORE 15
|
||||
#define R9A09G057_USB3_1_REF_ALT_CLK_P 16
|
||||
#define R9A09G057_USB3_1_CLKCORE 17
|
||||
|
||||
#endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G057_CPG_H__ */
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user