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clk: renesas: Updates for v6.19
- Various fixes for the module reset procedure on R-Car Gen4 SoCs, - Add ADC and thermal (TSU) clocks on RZ/T2H and RZ/N2H, - Add USB clocks and resets on RZ/G3E, - Add ISP and display (DSI, LCDC) clocks and resets on RZ/V2H and RZ/V2N, - Add thermal (TSU) and RTC clocks and resets on RZ/V2H, - Add reset support on RZ/T2H and RZ/N2H, - Fix the module stop disable procedure on RZ/T2H and RZ/N2H, - Add camera (CRU) clocks and resets on RZ/V2N, - Miscellaneous fixes and improvements. -----BEGIN PGP SIGNATURE----- iHUEABYKAB0WIQQ9qaHoIs/1I4cXmEiKwlD9ZEnxcAUCaQSODgAKCRCKwlD9ZEnx cADZAP4xm+4mGciCjAkvNotnZiE6UvJrDJGLuRPEMxxSP/IZQgD+Nks2rsHwnVQQ VMySY0DrTG0aopWDAqaXfKXK4l22Xwk= =GNXF -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQJIBAABCAAyFiEE9L57QeeUxqYDyoaDrQKIl8bklSUFAmkSjCUUHHN3Ym95ZEBj aHJvbWl1bS5vcmcACgkQrQKIl8bklSXbfxAAmH/TRPw/VG1L6l3d7927XCUESCh7 tHXG4fHa0SF4eTxZBaNWHWRmOBkjBgOwdwyngyPS4rDQtFH0enUpPbfPYOmYYmPe 5XzewfvnfOqSw3Zo23rDF/6OijZRCnoFlwXDdi1OXYTRNaYSyYcXsnjXpjyBoF98 0N7v+wpWo2NkFZ9EMQ6rpf2VE1/TCy87/hHMMx29uPQvgpjE3clPYN6OMaoaOZMc dyJx8otwIbNTeLms/oj0oLSgplJlvQlm8CZ4lLkkUQsEeV/UJmqNACnNVUC5VCiK chflc6OQMozC16vaWxs0dFYDvk0IwRmJCy6pY2rnCHqXr0SFgOyPGAjNZK3Uwk1e UbV79V0eJ5c8C7azMcFQ/pF8mvagArSHMZ47jf3oFzRF/E+kLqXzY34H00GxZskY kWfD6UwU69fjfZYXLm4qbbQbhSih4saRutvwBBKwn0OP0MaAHFcIMx6WvgN6qltq m2Sg2VwfNpCIe6QOlPMMTOjPt0lBHbO1dRG32hIg7s60imRzp/RjlWVX/XgOgnvr 7W7SZhHERqxEfT/i0e8ED8Rtix9AOy08bn3Foie3mCwF1Qz3aLECTkj9w+iucyWw yHzRMu8kpcEfQoMkpd+ILNfjEWd5HBTuBH6nlV3lyTWIkUhtadGmb0kgt4f1ECsL r2Uw0y1NcAsdfzI= =1gJz -----END PGP SIGNATURE----- Merge tag 'renesas-clk-for-v6.19-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas Pull Renesas clk driver updates from Geert Uytterhoeven: - Various fixes for the module reset procedure on R-Car Gen4 SoCs - Add ADC and thermal (TSU) clocks on RZ/T2H and RZ/N2H - Add USB clocks and resets on RZ/G3E - Add ISP and display (DSI, LCDC) clocks and resets on RZ/V2H and RZ/V2N - Add thermal (TSU) and RTC clocks and resets on RZ/V2H - Add reset support on RZ/T2H and RZ/N2H - Fix the module stop disable procedure on RZ/T2H and RZ/N2H - Add camera (CRU) clocks and resets on RZ/V2N * tag 'renesas-clk-for-v6.19-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers: (21 commits) clk: renesas: r9a09g056: Add clock and reset entries for ISP clk: renesas: r9a09g056: Add support for PLLVDO, CRU clocks, and resets clk: renesas: r9a09g056: Add clocks and resets for DSI and LCDC modules clk: renesas: r9a09g077: Add TSU module clock clk: renesas: r9a09g057: Add clock and reset entries for DSI and LCDC clk: renesas: rzv2h: Add support for DSI clocks clk: renesas: rzv2h: Use GENMASK for PLL fields clk: renesas: rzv2h: Add instance field to struct pll clk: renesas: r9a09g057: Add clock and reset entries for RTC clk: renesas: cpg-mssr: Spelling s/offets/offsets/ clk: renesas: r9a09g057: Add clock and reset entries for TSU clk: renesas: cpg-mssr: Add read-back and delay handling for RZ/T2H MSTP clk: renesas: cpg-mssr: Add module reset support for RZ/T2H clk: renesas: r9a09g057: Add clock and reset entries for ISP clk: renesas: r9a09g047: Add clock and reset entries for USB2 clk: renesas: Use IS_ERR() for pointers that cannot be NULL dt-bindings: clock: renesas,r9a09g047-cpg: Add USB2 PHY core clocks clk: renesas: cpg-lib: Remove unneeded semicolon clk: renesas: r9a09g077: Add ADC module clocks clk: renesas: cpg-mssr: Read back reset registers to assure values latched ...
This commit is contained in:
Stephen Boyd
commit
1f2d68c354
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@ -16,7 +16,7 @@
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enum clk_ids {
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/* Core Clock Outputs exported to DT */
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LAST_DT_CORE_CLK = R9A09G047_USB3_0_CLKCORE,
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LAST_DT_CORE_CLK = R9A09G047_USB2_0_CLK_CORE1,
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/* External Input Clocks */
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CLK_AUDIO_EXTAL,
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@ -177,6 +177,8 @@ static const struct cpg_core_clk r9a09g047_core_clks[] __initconst = {
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CDDIV1_DIVCTL3, dtable_1_8),
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DEF_FIXED("iotop_0_shclk", R9A09G047_IOTOP_0_SHCLK, CLK_PLLCM33_DIV16, 1, 1),
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DEF_FIXED("spi_clk_spi", R9A09G047_SPI_CLK_SPI, CLK_PLLCM33_XSPI, 1, 2),
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DEF_FIXED("usb2_0_clk_core0", R9A09G047_USB2_0_CLK_CORE0, CLK_QEXTAL, 1, 1),
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DEF_FIXED("usb2_0_clk_core1", R9A09G047_USB2_0_CLK_CORE1, CLK_QEXTAL, 1, 1),
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DEF_FIXED("gbeth_0_clk_ptp_ref_i", R9A09G047_GBETH_0_CLK_PTP_REF_I,
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CLK_PLLETH_DIV_125_FIX, 1, 1),
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DEF_FIXED("gbeth_1_clk_ptp_ref_i", R9A09G047_GBETH_1_CLK_PTP_REF_I,
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@ -282,6 +284,16 @@ static const struct rzv2h_mod_clk r9a09g047_mod_clks[] __initconst = {
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BUS_MSTOP(7, BIT(12))),
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DEF_MOD("usb3_0_pclk_usbtst", CLK_PLLDTY_ACPU_DIV4, 11, 0, 5, 16,
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BUS_MSTOP(7, BIT(14))),
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DEF_MOD("usb2_0_u2h0_hclk", CLK_PLLDTY_DIV8, 11, 3, 5, 19,
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BUS_MSTOP(7, BIT(7))),
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DEF_MOD("usb2_0_u2h1_hclk", CLK_PLLDTY_DIV8, 11, 4, 5, 20,
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BUS_MSTOP(7, BIT(8))),
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DEF_MOD("usb2_0_u2p_exr_cpuclk", CLK_PLLDTY_ACPU_DIV4, 11, 5, 5, 21,
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BUS_MSTOP(7, BIT(9))),
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DEF_MOD("usb2_0_pclk_usbtst0", CLK_PLLDTY_ACPU_DIV4, 11, 6, 5, 22,
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BUS_MSTOP(7, BIT(10))),
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DEF_MOD("usb2_0_pclk_usbtst1", CLK_PLLDTY_ACPU_DIV4, 11, 7, 5, 23,
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BUS_MSTOP(7, BIT(11))),
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DEF_MOD_MUX_EXTERNAL("gbeth_0_clk_tx_i", CLK_SMUX2_GBE0_TXCLK, 11, 8, 5, 24,
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BUS_MSTOP(8, BIT(5)), 1),
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DEF_MOD_MUX_EXTERNAL("gbeth_0_clk_rx_i", CLK_SMUX2_GBE0_RXCLK, 11, 9, 5, 25,
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@ -359,6 +371,10 @@ static const struct rzv2h_reset r9a09g047_resets[] __initconst = {
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DEF_RST(10, 8, 4, 25), /* SDHI_1_IXRST */
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DEF_RST(10, 9, 4, 26), /* SDHI_2_IXRST */
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DEF_RST(10, 10, 4, 27), /* USB3_0_ARESETN */
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DEF_RST(10, 12, 4, 29), /* USB2_0_U2H0_HRESETN */
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DEF_RST(10, 13, 4, 30), /* USB2_0_U2H1_HRESETN */
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DEF_RST(10, 14, 4, 31), /* USB2_0_U2P_EXL_SYSRST */
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DEF_RST(10, 15, 5, 0), /* USB2_0_PRESETN */
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DEF_RST(11, 0, 5, 1), /* GBETH_0_ARESETN_I */
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DEF_RST(11, 1, 5, 2), /* GBETH_1_ARESETN_I */
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DEF_RST(12, 5, 5, 22), /* CRU_0_PRESETN */
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@ -6,6 +6,7 @@
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*/
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#include <linux/clk-provider.h>
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#include <linux/clk/renesas.h>
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#include <linux/device.h>
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#include <linux/init.h>
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#include <linux/kernel.h>
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@ -28,7 +29,9 @@ enum clk_ids {
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CLK_PLLCLN,
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CLK_PLLDTY,
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CLK_PLLCA55,
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CLK_PLLVDO,
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CLK_PLLETH,
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CLK_PLLDSI,
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CLK_PLLGPU,
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/* Internal Core Clocks */
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@ -47,6 +50,10 @@ enum clk_ids {
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CLK_PLLDTY_ACPU_DIV2,
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CLK_PLLDTY_ACPU_DIV4,
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CLK_PLLDTY_DIV8,
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CLK_PLLDTY_DIV16,
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CLK_PLLVDO_CRU0,
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CLK_PLLVDO_CRU1,
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CLK_PLLVDO_ISP,
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CLK_PLLETH_DIV_250_FIX,
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CLK_PLLETH_DIV_125_FIX,
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CLK_CSDIV_PLLETH_GBE0,
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@ -55,6 +62,9 @@ enum clk_ids {
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CLK_SMUX2_GBE0_RXCLK,
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CLK_SMUX2_GBE1_TXCLK,
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CLK_SMUX2_GBE1_RXCLK,
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CLK_CDIV4_PLLETH_LPCLK,
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CLK_PLLETH_LPCLK_GEAR,
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CLK_PLLDSI_GEAR,
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CLK_PLLGPU_GEAR,
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/* Module Clocks */
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@ -69,6 +79,12 @@ static const struct clk_div_table dtable_1_8[] = {
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{0, 0},
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};
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static const struct clk_div_table dtable_2_4[] = {
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{0, 2},
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{1, 4},
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{0, 0},
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};
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static const struct clk_div_table dtable_2_16[] = {
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{0, 2},
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{1, 4},
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@ -77,6 +93,26 @@ static const struct clk_div_table dtable_2_16[] = {
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{0, 0},
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};
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static const struct clk_div_table dtable_2_32[] = {
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{0, 2},
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{1, 4},
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{2, 6},
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{3, 8},
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{4, 10},
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{5, 12},
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{6, 14},
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{7, 16},
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{8, 18},
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{9, 20},
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{10, 22},
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{11, 24},
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{12, 26},
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{13, 28},
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{14, 30},
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{15, 32},
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{0, 0},
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};
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static const struct clk_div_table dtable_2_64[] = {
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{0, 2},
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{1, 4},
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@ -93,6 +129,17 @@ static const struct clk_div_table dtable_2_100[] = {
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{0, 0},
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};
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static const struct clk_div_table dtable_16_128[] = {
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{0, 16},
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{1, 32},
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{2, 64},
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{3, 128},
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{0, 0},
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};
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RZV2H_CPG_PLL_DSI_LIMITS(rzv2n_cpg_pll_dsi_limits);
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#define PLLDSI PLL_PACK_LIMITS(0xc0, 1, 0, &rzv2n_cpg_pll_dsi_limits)
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/* Mux clock tables */
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static const char * const smux2_gbe0_rxclk[] = { ".plleth_gbe0", "et0_rxclk" };
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static const char * const smux2_gbe0_txclk[] = { ".plleth_gbe0", "et0_txclk" };
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@ -112,7 +159,9 @@ static const struct cpg_core_clk r9a09g056_core_clks[] __initconst = {
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DEF_FIXED(".pllcln", CLK_PLLCLN, CLK_QEXTAL, 200, 3),
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DEF_FIXED(".plldty", CLK_PLLDTY, CLK_QEXTAL, 200, 3),
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DEF_PLL(".pllca55", CLK_PLLCA55, CLK_QEXTAL, PLLCA55),
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DEF_FIXED(".pllvdo", CLK_PLLVDO, CLK_QEXTAL, 105, 2),
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DEF_FIXED(".plleth", CLK_PLLETH, CLK_QEXTAL, 125, 3),
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DEF_PLLDSI(".plldsi", CLK_PLLDSI, CLK_QEXTAL, PLLDSI),
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DEF_PLL(".pllgpu", CLK_PLLGPU, CLK_QEXTAL, PLLGPU),
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/* Internal Core Clocks */
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@ -134,6 +183,11 @@ static const struct cpg_core_clk r9a09g056_core_clks[] __initconst = {
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DEF_FIXED(".plldty_acpu_div2", CLK_PLLDTY_ACPU_DIV2, CLK_PLLDTY_ACPU, 1, 2),
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DEF_FIXED(".plldty_acpu_div4", CLK_PLLDTY_ACPU_DIV4, CLK_PLLDTY_ACPU, 1, 4),
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DEF_FIXED(".plldty_div8", CLK_PLLDTY_DIV8, CLK_PLLDTY, 1, 8),
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DEF_FIXED(".plldty_div16", CLK_PLLDTY_DIV16, CLK_PLLDTY, 1, 16),
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DEF_DDIV(".pllvdo_cru0", CLK_PLLVDO_CRU0, CLK_PLLVDO, CDDIV3_DIVCTL3, dtable_2_4),
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DEF_DDIV(".pllvdo_cru1", CLK_PLLVDO_CRU1, CLK_PLLVDO, CDDIV4_DIVCTL0, dtable_2_4),
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DEF_DDIV(".pllvdo_isp", CLK_PLLVDO_ISP, CLK_PLLVDO, CDDIV2_DIVCTL3, dtable_2_64),
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DEF_FIXED(".plleth_250_fix", CLK_PLLETH_DIV_250_FIX, CLK_PLLETH, 1, 4),
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DEF_FIXED(".plleth_125_fix", CLK_PLLETH_DIV_125_FIX, CLK_PLLETH_DIV_250_FIX, 1, 2),
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@ -145,6 +199,12 @@ static const struct cpg_core_clk r9a09g056_core_clks[] __initconst = {
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DEF_SMUX(".smux2_gbe0_rxclk", CLK_SMUX2_GBE0_RXCLK, SSEL0_SELCTL3, smux2_gbe0_rxclk),
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DEF_SMUX(".smux2_gbe1_txclk", CLK_SMUX2_GBE1_TXCLK, SSEL1_SELCTL0, smux2_gbe1_txclk),
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DEF_SMUX(".smux2_gbe1_rxclk", CLK_SMUX2_GBE1_RXCLK, SSEL1_SELCTL1, smux2_gbe1_rxclk),
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DEF_FIXED(".cdiv4_plleth_lpclk", CLK_CDIV4_PLLETH_LPCLK, CLK_PLLETH, 1, 4),
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DEF_CSDIV(".plleth_lpclk_gear", CLK_PLLETH_LPCLK_GEAR, CLK_CDIV4_PLLETH_LPCLK,
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CSDIV0_DIVCTL2, dtable_16_128),
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DEF_PLLDSI_DIV(".plldsi_gear", CLK_PLLDSI_GEAR, CLK_PLLDSI,
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CSDIV1_DIVCTL2, dtable_2_32),
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DEF_DDIV(".pllgpu_gear", CLK_PLLGPU_GEAR, CLK_PLLGPU, CDDIV3_DIVCTL1, dtable_2_64),
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@ -289,6 +349,42 @@ static const struct rzv2h_mod_clk r9a09g056_mod_clks[] __initconst = {
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BUS_MSTOP(8, BIT(6))),
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DEF_MOD("gbeth_1_aclk_i", CLK_PLLDTY_DIV8, 12, 3, 6, 3,
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BUS_MSTOP(8, BIT(6))),
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DEF_MOD("cru_0_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 2, 6, 18,
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BUS_MSTOP(9, BIT(4))),
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DEF_MOD_NO_PM("cru_0_vclk", CLK_PLLVDO_CRU0, 13, 3, 6, 19,
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BUS_MSTOP(9, BIT(4))),
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DEF_MOD("cru_0_pclk", CLK_PLLDTY_DIV16, 13, 4, 6, 20,
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BUS_MSTOP(9, BIT(4))),
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DEF_MOD("cru_1_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 5, 6, 21,
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BUS_MSTOP(9, BIT(5))),
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DEF_MOD_NO_PM("cru_1_vclk", CLK_PLLVDO_CRU1, 13, 6, 6, 22,
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BUS_MSTOP(9, BIT(5))),
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DEF_MOD("cru_1_pclk", CLK_PLLDTY_DIV16, 13, 7, 6, 23,
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BUS_MSTOP(9, BIT(5))),
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DEF_MOD("isp_0_reg_aclk", CLK_PLLDTY_ACPU_DIV2, 14, 2, 7, 2,
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BUS_MSTOP(9, BIT(8))),
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DEF_MOD("isp_0_pclk", CLK_PLLDTY_DIV16, 14, 3, 7, 3,
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BUS_MSTOP(9, BIT(8))),
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DEF_MOD("isp_0_vin_aclk", CLK_PLLDTY_ACPU_DIV2, 14, 4, 7, 4,
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BUS_MSTOP(9, BIT(9))),
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DEF_MOD("isp_0_isp_sclk", CLK_PLLVDO_ISP, 14, 5, 7, 5,
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BUS_MSTOP(9, BIT(9))),
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DEF_MOD("dsi_0_pclk", CLK_PLLDTY_DIV16, 14, 8, 7, 8,
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BUS_MSTOP(9, BIT(14) | BIT(15))),
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DEF_MOD("dsi_0_aclk", CLK_PLLDTY_ACPU_DIV2, 14, 9, 7, 9,
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BUS_MSTOP(9, BIT(14) | BIT(15))),
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DEF_MOD("dsi_0_vclk1", CLK_PLLDSI_GEAR, 14, 10, 7, 10,
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BUS_MSTOP(9, BIT(14) | BIT(15))),
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DEF_MOD("dsi_0_lpclk", CLK_PLLETH_LPCLK_GEAR, 14, 11, 7, 11,
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BUS_MSTOP(9, BIT(14) | BIT(15))),
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DEF_MOD("dsi_0_pllref_clk", CLK_QEXTAL, 14, 12, 7, 12,
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BUS_MSTOP(9, BIT(14) | BIT(15))),
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DEF_MOD("lcdc_0_clk_a", CLK_PLLDTY_ACPU_DIV2, 14, 13, 7, 13,
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BUS_MSTOP(10, BIT(1) | BIT(2) | BIT(3))),
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DEF_MOD("lcdc_0_clk_p", CLK_PLLDTY_DIV16, 14, 14, 7, 14,
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BUS_MSTOP(10, BIT(1) | BIT(2) | BIT(3))),
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DEF_MOD("lcdc_0_clk_d", CLK_PLLDSI_GEAR, 14, 15, 7, 15,
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BUS_MSTOP(10, BIT(1) | BIT(2) | BIT(3))),
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DEF_MOD("gpu_0_clk", CLK_PLLGPU_GEAR, 15, 0, 7, 16,
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BUS_MSTOP(3, BIT(4))),
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DEF_MOD("gpu_0_axi_clk", CLK_PLLDTY_ACPU_DIV2, 15, 1, 7, 17,
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@ -335,6 +431,19 @@ static const struct rzv2h_reset r9a09g056_resets[] __initconst = {
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DEF_RST(10, 15, 5, 0), /* USB2_0_PRESETN */
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DEF_RST(11, 0, 5, 1), /* GBETH_0_ARESETN_I */
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DEF_RST(11, 1, 5, 2), /* GBETH_1_ARESETN_I */
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DEF_RST(12, 5, 5, 22), /* CRU_0_PRESETN */
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DEF_RST(12, 6, 5, 23), /* CRU_0_ARESETN */
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DEF_RST(12, 7, 5, 24), /* CRU_0_S_RESETN */
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DEF_RST(12, 8, 5, 25), /* CRU_1_PRESETN */
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DEF_RST(12, 9, 5, 26), /* CRU_1_ARESETN */
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DEF_RST(12, 10, 5, 27), /* CRU_1_S_RESETN */
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DEF_RST(13, 1, 6, 2), /* ISP_0_VIN_ARESETN */
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DEF_RST(13, 2, 6, 3), /* ISP_0_REG_ARESETN */
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||||
DEF_RST(13, 3, 6, 4), /* ISP_0_ISP_SRESETN */
|
||||
DEF_RST(13, 4, 6, 5), /* ISP_0_PRESETN */
|
||||
DEF_RST(13, 7, 6, 8), /* DSI_0_PRESETN */
|
||||
DEF_RST(13, 8, 6, 9), /* DSI_0_ARESETN */
|
||||
DEF_RST(13, 12, 6, 13), /* LCDC_0_RESET_N */
|
||||
DEF_RST(13, 13, 6, 14), /* GPU_0_RESETN */
|
||||
DEF_RST(13, 14, 6, 15), /* GPU_0_AXI_RESETN */
|
||||
DEF_RST(13, 15, 6, 16), /* GPU_0_ACE_RESETN */
|
||||
|
|
|
|||
|
|
@ -6,6 +6,7 @@
|
|||
*/
|
||||
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/clk/renesas.h>
|
||||
#include <linux/device.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/kernel.h>
|
||||
|
|
@ -30,6 +31,7 @@ enum clk_ids {
|
|||
CLK_PLLCA55,
|
||||
CLK_PLLVDO,
|
||||
CLK_PLLETH,
|
||||
CLK_PLLDSI,
|
||||
CLK_PLLGPU,
|
||||
|
||||
/* Internal Core Clocks */
|
||||
|
|
@ -55,6 +57,7 @@ enum clk_ids {
|
|||
CLK_PLLVDO_CRU1,
|
||||
CLK_PLLVDO_CRU2,
|
||||
CLK_PLLVDO_CRU3,
|
||||
CLK_PLLVDO_ISP,
|
||||
CLK_PLLETH_DIV_250_FIX,
|
||||
CLK_PLLETH_DIV_125_FIX,
|
||||
CLK_CSDIV_PLLETH_GBE0,
|
||||
|
|
@ -63,6 +66,9 @@ enum clk_ids {
|
|||
CLK_SMUX2_GBE0_RXCLK,
|
||||
CLK_SMUX2_GBE1_TXCLK,
|
||||
CLK_SMUX2_GBE1_RXCLK,
|
||||
CLK_CDIV4_PLLETH_LPCLK,
|
||||
CLK_PLLETH_LPCLK_GEAR,
|
||||
CLK_PLLDSI_GEAR,
|
||||
CLK_PLLGPU_GEAR,
|
||||
|
||||
/* Module Clocks */
|
||||
|
|
@ -91,6 +97,26 @@ static const struct clk_div_table dtable_2_16[] = {
|
|||
{0, 0},
|
||||
};
|
||||
|
||||
static const struct clk_div_table dtable_2_32[] = {
|
||||
{0, 2},
|
||||
{1, 4},
|
||||
{2, 6},
|
||||
{3, 8},
|
||||
{4, 10},
|
||||
{5, 12},
|
||||
{6, 14},
|
||||
{7, 16},
|
||||
{8, 18},
|
||||
{9, 20},
|
||||
{10, 22},
|
||||
{11, 24},
|
||||
{12, 26},
|
||||
{13, 28},
|
||||
{14, 30},
|
||||
{15, 32},
|
||||
{0, 0},
|
||||
};
|
||||
|
||||
static const struct clk_div_table dtable_2_64[] = {
|
||||
{0, 2},
|
||||
{1, 4},
|
||||
|
|
@ -107,6 +133,17 @@ static const struct clk_div_table dtable_2_100[] = {
|
|||
{0, 0},
|
||||
};
|
||||
|
||||
static const struct clk_div_table dtable_16_128[] = {
|
||||
{0, 16},
|
||||
{1, 32},
|
||||
{2, 64},
|
||||
{3, 128},
|
||||
{0, 0},
|
||||
};
|
||||
|
||||
RZV2H_CPG_PLL_DSI_LIMITS(rzv2h_cpg_pll_dsi_limits);
|
||||
#define PLLDSI PLL_PACK_LIMITS(0xc0, 1, 0, &rzv2h_cpg_pll_dsi_limits)
|
||||
|
||||
/* Mux clock tables */
|
||||
static const char * const smux2_gbe0_rxclk[] = { ".plleth_gbe0", "et0_rxclk" };
|
||||
static const char * const smux2_gbe0_txclk[] = { ".plleth_gbe0", "et0_txclk" };
|
||||
|
|
@ -128,6 +165,7 @@ static const struct cpg_core_clk r9a09g057_core_clks[] __initconst = {
|
|||
DEF_PLL(".pllca55", CLK_PLLCA55, CLK_QEXTAL, PLLCA55),
|
||||
DEF_FIXED(".pllvdo", CLK_PLLVDO, CLK_QEXTAL, 105, 2),
|
||||
DEF_FIXED(".plleth", CLK_PLLETH, CLK_QEXTAL, 125, 3),
|
||||
DEF_PLLDSI(".plldsi", CLK_PLLDSI, CLK_QEXTAL, PLLDSI),
|
||||
DEF_PLL(".pllgpu", CLK_PLLGPU, CLK_QEXTAL, PLLGPU),
|
||||
|
||||
/* Internal Core Clocks */
|
||||
|
|
@ -157,6 +195,7 @@ static const struct cpg_core_clk r9a09g057_core_clks[] __initconst = {
|
|||
DEF_DDIV(".pllvdo_cru1", CLK_PLLVDO_CRU1, CLK_PLLVDO, CDDIV4_DIVCTL0, dtable_2_4),
|
||||
DEF_DDIV(".pllvdo_cru2", CLK_PLLVDO_CRU2, CLK_PLLVDO, CDDIV4_DIVCTL1, dtable_2_4),
|
||||
DEF_DDIV(".pllvdo_cru3", CLK_PLLVDO_CRU3, CLK_PLLVDO, CDDIV4_DIVCTL2, dtable_2_4),
|
||||
DEF_DDIV(".pllvdo_isp", CLK_PLLVDO_ISP, CLK_PLLVDO, CDDIV2_DIVCTL3, dtable_2_64),
|
||||
|
||||
DEF_FIXED(".plleth_250_fix", CLK_PLLETH_DIV_250_FIX, CLK_PLLETH, 1, 4),
|
||||
DEF_FIXED(".plleth_125_fix", CLK_PLLETH_DIV_125_FIX, CLK_PLLETH_DIV_250_FIX, 1, 2),
|
||||
|
|
@ -168,6 +207,12 @@ static const struct cpg_core_clk r9a09g057_core_clks[] __initconst = {
|
|||
DEF_SMUX(".smux2_gbe0_rxclk", CLK_SMUX2_GBE0_RXCLK, SSEL0_SELCTL3, smux2_gbe0_rxclk),
|
||||
DEF_SMUX(".smux2_gbe1_txclk", CLK_SMUX2_GBE1_TXCLK, SSEL1_SELCTL0, smux2_gbe1_txclk),
|
||||
DEF_SMUX(".smux2_gbe1_rxclk", CLK_SMUX2_GBE1_RXCLK, SSEL1_SELCTL1, smux2_gbe1_rxclk),
|
||||
DEF_FIXED(".cdiv4_plleth_lpclk", CLK_CDIV4_PLLETH_LPCLK, CLK_PLLETH, 1, 4),
|
||||
DEF_CSDIV(".plleth_lpclk_gear", CLK_PLLETH_LPCLK_GEAR, CLK_CDIV4_PLLETH_LPCLK,
|
||||
CSDIV0_DIVCTL2, dtable_16_128),
|
||||
|
||||
DEF_PLLDSI_DIV(".plldsi_gear", CLK_PLLDSI_GEAR, CLK_PLLDSI,
|
||||
CSDIV1_DIVCTL2, dtable_2_32),
|
||||
|
||||
DEF_DDIV(".pllgpu_gear", CLK_PLLGPU_GEAR, CLK_PLLGPU, CDDIV3_DIVCTL1, dtable_2_64),
|
||||
|
||||
|
|
@ -239,6 +284,8 @@ static const struct rzv2h_mod_clk r9a09g057_mod_clks[] __initconst = {
|
|||
BUS_MSTOP(5, BIT(13))),
|
||||
DEF_MOD("wdt_3_clk_loco", CLK_QEXTAL, 5, 2, 2, 18,
|
||||
BUS_MSTOP(5, BIT(13))),
|
||||
DEF_MOD("rtc_0_clk_rtc", CLK_PLLCM33_DIV16, 5, 3, 2, 19,
|
||||
BUS_MSTOP(3, BIT(11) | BIT(12))),
|
||||
DEF_MOD("rspi_0_pclk", CLK_PLLCLN_DIV8, 5, 4, 2, 20,
|
||||
BUS_MSTOP(11, BIT(0))),
|
||||
DEF_MOD("rspi_0_pclk_sfr", CLK_PLLCLN_DIV8, 5, 5, 2, 21,
|
||||
|
|
@ -371,12 +418,40 @@ static const struct rzv2h_mod_clk r9a09g057_mod_clks[] __initconst = {
|
|||
BUS_MSTOP(9, BIT(7))),
|
||||
DEF_MOD("cru_3_pclk", CLK_PLLDTY_DIV16, 13, 13, 6, 29,
|
||||
BUS_MSTOP(9, BIT(7))),
|
||||
DEF_MOD("isp_0_reg_aclk", CLK_PLLDTY_ACPU_DIV2, 14, 2, 7, 2,
|
||||
BUS_MSTOP(9, BIT(8))),
|
||||
DEF_MOD("isp_0_pclk", CLK_PLLDTY_DIV16, 14, 3, 7, 3,
|
||||
BUS_MSTOP(9, BIT(8))),
|
||||
DEF_MOD("isp_0_vin_aclk", CLK_PLLDTY_ACPU_DIV2, 14, 4, 7, 4,
|
||||
BUS_MSTOP(9, BIT(9))),
|
||||
DEF_MOD("isp_0_isp_sclk", CLK_PLLVDO_ISP, 14, 5, 7, 5,
|
||||
BUS_MSTOP(9, BIT(9))),
|
||||
DEF_MOD("dsi_0_pclk", CLK_PLLDTY_DIV16, 14, 8, 7, 8,
|
||||
BUS_MSTOP(9, BIT(14) | BIT(15))),
|
||||
DEF_MOD("dsi_0_aclk", CLK_PLLDTY_ACPU_DIV2, 14, 9, 7, 9,
|
||||
BUS_MSTOP(9, BIT(14) | BIT(15))),
|
||||
DEF_MOD("dsi_0_vclk1", CLK_PLLDSI_GEAR, 14, 10, 7, 10,
|
||||
BUS_MSTOP(9, BIT(14) | BIT(15))),
|
||||
DEF_MOD("dsi_0_lpclk", CLK_PLLETH_LPCLK_GEAR, 14, 11, 7, 11,
|
||||
BUS_MSTOP(9, BIT(14) | BIT(15))),
|
||||
DEF_MOD("dsi_0_pllref_clk", CLK_QEXTAL, 14, 12, 7, 12,
|
||||
BUS_MSTOP(9, BIT(14) | BIT(15))),
|
||||
DEF_MOD("lcdc_0_clk_a", CLK_PLLDTY_ACPU_DIV2, 14, 13, 7, 13,
|
||||
BUS_MSTOP(10, BIT(1) | BIT(2) | BIT(3))),
|
||||
DEF_MOD("lcdc_0_clk_p", CLK_PLLDTY_DIV16, 14, 14, 7, 14,
|
||||
BUS_MSTOP(10, BIT(1) | BIT(2) | BIT(3))),
|
||||
DEF_MOD("lcdc_0_clk_d", CLK_PLLDSI_GEAR, 14, 15, 7, 15,
|
||||
BUS_MSTOP(10, BIT(1) | BIT(2) | BIT(3))),
|
||||
DEF_MOD("gpu_0_clk", CLK_PLLGPU_GEAR, 15, 0, 7, 16,
|
||||
BUS_MSTOP(3, BIT(4))),
|
||||
DEF_MOD("gpu_0_axi_clk", CLK_PLLDTY_ACPU_DIV2, 15, 1, 7, 17,
|
||||
BUS_MSTOP(3, BIT(4))),
|
||||
DEF_MOD("gpu_0_ace_clk", CLK_PLLDTY_ACPU_DIV2, 15, 2, 7, 18,
|
||||
BUS_MSTOP(3, BIT(4))),
|
||||
DEF_MOD("tsu_0_pclk", CLK_QEXTAL, 16, 9, 8, 9,
|
||||
BUS_MSTOP(5, BIT(2))),
|
||||
DEF_MOD("tsu_1_pclk", CLK_QEXTAL, 16, 10, 8, 10,
|
||||
BUS_MSTOP(2, BIT(15))),
|
||||
};
|
||||
|
||||
static const struct rzv2h_reset r9a09g057_resets[] __initconst = {
|
||||
|
|
@ -401,6 +476,8 @@ static const struct rzv2h_reset r9a09g057_resets[] __initconst = {
|
|||
DEF_RST(7, 6, 3, 7), /* WDT_1_RESET */
|
||||
DEF_RST(7, 7, 3, 8), /* WDT_2_RESET */
|
||||
DEF_RST(7, 8, 3, 9), /* WDT_3_RESET */
|
||||
DEF_RST(7, 9, 3, 10), /* RTC_0_RST_RTC */
|
||||
DEF_RST(7, 10, 3, 11), /* RTC_0_RST_RTC_V */
|
||||
DEF_RST(7, 11, 3, 12), /* RSPI_0_PRESETN */
|
||||
DEF_RST(7, 12, 3, 13), /* RSPI_0_TRESETN */
|
||||
DEF_RST(7, 13, 3, 14), /* RSPI_1_PRESETN */
|
||||
|
|
@ -442,9 +519,18 @@ static const struct rzv2h_reset r9a09g057_resets[] __initconst = {
|
|||
DEF_RST(12, 14, 5, 31), /* CRU_3_PRESETN */
|
||||
DEF_RST(12, 15, 6, 0), /* CRU_3_ARESETN */
|
||||
DEF_RST(13, 0, 6, 1), /* CRU_3_S_RESETN */
|
||||
DEF_RST(13, 1, 6, 2), /* ISP_0_VIN_ARESETN */
|
||||
DEF_RST(13, 2, 6, 3), /* ISP_0_REG_ARESETN */
|
||||
DEF_RST(13, 3, 6, 4), /* ISP_0_ISP_SRESETN */
|
||||
DEF_RST(13, 4, 6, 5), /* ISP_0_PRESETN */
|
||||
DEF_RST(13, 7, 6, 8), /* DSI_0_PRESETN */
|
||||
DEF_RST(13, 8, 6, 9), /* DSI_0_ARESETN */
|
||||
DEF_RST(13, 12, 6, 13), /* LCDC_0_RESET_N */
|
||||
DEF_RST(13, 13, 6, 14), /* GPU_0_RESETN */
|
||||
DEF_RST(13, 14, 6, 15), /* GPU_0_AXI_RESETN */
|
||||
DEF_RST(13, 15, 6, 16), /* GPU_0_ACE_RESETN */
|
||||
DEF_RST(15, 7, 7, 8), /* TSU_0_PRESETN */
|
||||
DEF_RST(15, 8, 7, 9), /* TSU_1_PRESETN */
|
||||
};
|
||||
|
||||
const struct rzv2h_cpg_info r9a09g057_cpg_info __initconst = {
|
||||
|
|
|
|||
|
|
@ -188,6 +188,10 @@ static const struct mssr_mod_clk r9a09g077_mod_clks[] __initconst = {
|
|||
DEF_MOD("sci4fck", 12, CLK_SCI4ASYNC),
|
||||
DEF_MOD("iic0", 100, R9A09G077_CLK_PCLKL),
|
||||
DEF_MOD("iic1", 101, R9A09G077_CLK_PCLKL),
|
||||
DEF_MOD("adc0", 206, R9A09G077_CLK_PCLKH),
|
||||
DEF_MOD("adc1", 207, R9A09G077_CLK_PCLKH),
|
||||
DEF_MOD("adc2", 225, R9A09G077_CLK_PCLKM),
|
||||
DEF_MOD("tsu", 307, R9A09G077_CLK_PCLKL),
|
||||
DEF_MOD("gmac0", 400, R9A09G077_CLK_PCLKM),
|
||||
DEF_MOD("ethsw", 401, R9A09G077_CLK_PCLKM),
|
||||
DEF_MOD("ethss", 403, R9A09G077_CLK_PCLKM),
|
||||
|
|
|
|||
|
|
@ -35,7 +35,7 @@ void cpg_reg_modify(void __iomem *reg, u32 clear, u32 set)
|
|||
val |= set;
|
||||
writel(val, reg);
|
||||
spin_unlock_irqrestore(&cpg_lock, flags);
|
||||
};
|
||||
}
|
||||
|
||||
static int cpg_simple_notifier_call(struct notifier_block *nb,
|
||||
unsigned long action, void *data)
|
||||
|
|
|
|||
|
|
@ -40,8 +40,10 @@
|
|||
#define WARN_DEBUG(x) do { } while (0)
|
||||
#endif
|
||||
|
||||
#define RZT2H_RESET_REG_READ_COUNT 7
|
||||
|
||||
/*
|
||||
* Module Standby and Software Reset register offets.
|
||||
* Module Standby and Software Reset register offsets.
|
||||
*
|
||||
* If the registers exist, these are valid for SH-Mobile, R-Mobile,
|
||||
* R-Car Gen2, R-Car Gen3, and RZ/G1.
|
||||
|
|
@ -137,6 +139,22 @@ static const u16 srcr_for_gen4[] = {
|
|||
0x2C60, 0x2C64, 0x2C68, 0x2C6C, 0x2C70, 0x2C74,
|
||||
};
|
||||
|
||||
static const u16 mrcr_for_rzt2h[] = {
|
||||
0x240, /* MRCTLA */
|
||||
0x244, /* Reserved */
|
||||
0x248, /* Reserved */
|
||||
0x24C, /* Reserved */
|
||||
0x250, /* MRCTLE */
|
||||
0x254, /* Reserved */
|
||||
0x258, /* Reserved */
|
||||
0x25C, /* Reserved */
|
||||
0x260, /* MRCTLI */
|
||||
0x264, /* Reserved */
|
||||
0x268, /* Reserved */
|
||||
0x26C, /* Reserved */
|
||||
0x270, /* MRCTLM */
|
||||
};
|
||||
|
||||
/*
|
||||
* Software Reset Clearing Register offsets
|
||||
*/
|
||||
|
|
@ -290,10 +308,21 @@ static int cpg_mstp_clock_endisable(struct clk_hw *hw, bool enable)
|
|||
|
||||
spin_unlock_irqrestore(&priv->pub.rmw_lock, flags);
|
||||
|
||||
if (!enable || priv->reg_layout == CLK_REG_LAYOUT_RZ_A ||
|
||||
priv->reg_layout == CLK_REG_LAYOUT_RZ_T2H)
|
||||
if (!enable || priv->reg_layout == CLK_REG_LAYOUT_RZ_A)
|
||||
return 0;
|
||||
|
||||
if (priv->reg_layout == CLK_REG_LAYOUT_RZ_T2H) {
|
||||
/*
|
||||
* For the RZ/T2H case, it is necessary to perform a read-back after
|
||||
* accessing the MSTPCRm register and to dummy-read any register of
|
||||
* the IP at least seven times. Instead of memory-mapping the IP
|
||||
* register, we simply add a delay after the read operation.
|
||||
*/
|
||||
cpg_rzt2h_mstp_read(hw, priv->control_regs[reg]);
|
||||
udelay(10);
|
||||
return 0;
|
||||
}
|
||||
|
||||
error = readl_poll_timeout_atomic(priv->pub.base0 + priv->status_regs[reg],
|
||||
value, !(value & bitmask), 0, 10);
|
||||
if (error)
|
||||
|
|
@ -451,7 +480,7 @@ static void __init cpg_mssr_register_core_clk(const struct cpg_core_clk *core,
|
|||
break;
|
||||
}
|
||||
|
||||
if (IS_ERR_OR_NULL(clk))
|
||||
if (IS_ERR(clk))
|
||||
goto fail;
|
||||
|
||||
dev_dbg(dev, "Core clock %pC at %lu Hz\n", clk, clk_get_rate(clk));
|
||||
|
|
@ -676,53 +705,56 @@ static int __init cpg_mssr_add_clk_domain(struct device *dev,
|
|||
|
||||
#define rcdev_to_priv(x) container_of(x, struct cpg_mssr_priv, rcdev)
|
||||
|
||||
static int cpg_mssr_reset(struct reset_controller_dev *rcdev,
|
||||
unsigned long id)
|
||||
static int cpg_mssr_reset_operate(struct reset_controller_dev *rcdev,
|
||||
const char *func, bool set, unsigned long id)
|
||||
{
|
||||
struct cpg_mssr_priv *priv = rcdev_to_priv(rcdev);
|
||||
unsigned int reg = id / 32;
|
||||
unsigned int bit = id % 32;
|
||||
const u16 off = set ? priv->reset_regs[reg] : priv->reset_clear_regs[reg];
|
||||
u32 bitmask = BIT(bit);
|
||||
|
||||
dev_dbg(priv->dev, "reset %u%02u\n", reg, bit);
|
||||
if (func)
|
||||
dev_dbg(priv->dev, "%s %u%02u\n", func, reg, bit);
|
||||
|
||||
/* Reset module */
|
||||
writel(bitmask, priv->pub.base0 + priv->reset_regs[reg]);
|
||||
|
||||
/* Wait for at least one cycle of the RCLK clock (@ ca. 32 kHz) */
|
||||
udelay(35);
|
||||
|
||||
/* Release module from reset state */
|
||||
writel(bitmask, priv->pub.base0 + priv->reset_clear_regs[reg]);
|
||||
writel(bitmask, priv->pub.base0 + off);
|
||||
readl(priv->pub.base0 + off);
|
||||
barrier_data(priv->pub.base0 + off);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int cpg_mssr_assert(struct reset_controller_dev *rcdev, unsigned long id)
|
||||
static int cpg_mssr_reset(struct reset_controller_dev *rcdev,
|
||||
unsigned long id)
|
||||
{
|
||||
struct cpg_mssr_priv *priv = rcdev_to_priv(rcdev);
|
||||
unsigned int reg = id / 32;
|
||||
unsigned int bit = id % 32;
|
||||
u32 bitmask = BIT(bit);
|
||||
|
||||
dev_dbg(priv->dev, "assert %u%02u\n", reg, bit);
|
||||
/* Reset module */
|
||||
cpg_mssr_reset_operate(rcdev, "reset", true, id);
|
||||
|
||||
writel(bitmask, priv->pub.base0 + priv->reset_regs[reg]);
|
||||
return 0;
|
||||
/*
|
||||
* On R-Car Gen4, delay after SRCR has been written is 1ms.
|
||||
* On older SoCs, delay after SRCR has been written is 35us
|
||||
* (one cycle of the RCLK clock @ ca. 32 kHz).
|
||||
*/
|
||||
if (priv->reg_layout == CLK_REG_LAYOUT_RCAR_GEN4)
|
||||
usleep_range(1000, 2000);
|
||||
else
|
||||
usleep_range(35, 1000);
|
||||
|
||||
/* Release module from reset state */
|
||||
return cpg_mssr_reset_operate(rcdev, NULL, false, id);
|
||||
}
|
||||
|
||||
static int cpg_mssr_assert(struct reset_controller_dev *rcdev, unsigned long id)
|
||||
{
|
||||
return cpg_mssr_reset_operate(rcdev, "assert", true, id);
|
||||
}
|
||||
|
||||
static int cpg_mssr_deassert(struct reset_controller_dev *rcdev,
|
||||
unsigned long id)
|
||||
{
|
||||
struct cpg_mssr_priv *priv = rcdev_to_priv(rcdev);
|
||||
unsigned int reg = id / 32;
|
||||
unsigned int bit = id % 32;
|
||||
u32 bitmask = BIT(bit);
|
||||
|
||||
dev_dbg(priv->dev, "deassert %u%02u\n", reg, bit);
|
||||
|
||||
writel(bitmask, priv->pub.base0 + priv->reset_clear_regs[reg]);
|
||||
return 0;
|
||||
return cpg_mssr_reset_operate(rcdev, "deassert", false, id);
|
||||
}
|
||||
|
||||
static int cpg_mssr_status(struct reset_controller_dev *rcdev,
|
||||
|
|
@ -736,6 +768,72 @@ static int cpg_mssr_status(struct reset_controller_dev *rcdev,
|
|||
return !!(readl(priv->pub.base0 + priv->reset_regs[reg]) & bitmask);
|
||||
}
|
||||
|
||||
static int cpg_mrcr_set_reset_state(struct reset_controller_dev *rcdev,
|
||||
unsigned long id, bool set)
|
||||
{
|
||||
struct cpg_mssr_priv *priv = rcdev_to_priv(rcdev);
|
||||
unsigned int reg = id / 32;
|
||||
unsigned int bit = id % 32;
|
||||
u32 bitmask = BIT(bit);
|
||||
void __iomem *reg_addr;
|
||||
unsigned long flags;
|
||||
unsigned int i;
|
||||
u32 val;
|
||||
|
||||
dev_dbg(priv->dev, "%s %u%02u\n", set ? "assert" : "deassert", reg, bit);
|
||||
|
||||
spin_lock_irqsave(&priv->pub.rmw_lock, flags);
|
||||
|
||||
reg_addr = priv->pub.base0 + priv->reset_regs[reg];
|
||||
/* Read current value and modify */
|
||||
val = readl(reg_addr);
|
||||
if (set)
|
||||
val |= bitmask;
|
||||
else
|
||||
val &= ~bitmask;
|
||||
writel(val, reg_addr);
|
||||
|
||||
/*
|
||||
* For secure processing after release from a module reset, one must
|
||||
* perform multiple dummy reads of the same register.
|
||||
*/
|
||||
for (i = 0; !set && i < RZT2H_RESET_REG_READ_COUNT; i++)
|
||||
readl(reg_addr);
|
||||
|
||||
/* Verify the operation */
|
||||
val = readl(reg_addr);
|
||||
if (set == !(bitmask & val)) {
|
||||
dev_err(priv->dev, "Reset register %u%02u operation failed\n", reg, bit);
|
||||
spin_unlock_irqrestore(&priv->pub.rmw_lock, flags);
|
||||
return -EIO;
|
||||
}
|
||||
|
||||
spin_unlock_irqrestore(&priv->pub.rmw_lock, flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int cpg_mrcr_reset(struct reset_controller_dev *rcdev, unsigned long id)
|
||||
{
|
||||
int ret;
|
||||
|
||||
ret = cpg_mrcr_set_reset_state(rcdev, id, true);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
return cpg_mrcr_set_reset_state(rcdev, id, false);
|
||||
}
|
||||
|
||||
static int cpg_mrcr_assert(struct reset_controller_dev *rcdev, unsigned long id)
|
||||
{
|
||||
return cpg_mrcr_set_reset_state(rcdev, id, true);
|
||||
}
|
||||
|
||||
static int cpg_mrcr_deassert(struct reset_controller_dev *rcdev, unsigned long id)
|
||||
{
|
||||
return cpg_mrcr_set_reset_state(rcdev, id, false);
|
||||
}
|
||||
|
||||
static const struct reset_control_ops cpg_mssr_reset_ops = {
|
||||
.reset = cpg_mssr_reset,
|
||||
.assert = cpg_mssr_assert,
|
||||
|
|
@ -743,6 +841,13 @@ static const struct reset_control_ops cpg_mssr_reset_ops = {
|
|||
.status = cpg_mssr_status,
|
||||
};
|
||||
|
||||
static const struct reset_control_ops cpg_mrcr_reset_ops = {
|
||||
.reset = cpg_mrcr_reset,
|
||||
.assert = cpg_mrcr_assert,
|
||||
.deassert = cpg_mrcr_deassert,
|
||||
.status = cpg_mssr_status,
|
||||
};
|
||||
|
||||
static int cpg_mssr_reset_xlate(struct reset_controller_dev *rcdev,
|
||||
const struct of_phandle_args *reset_spec)
|
||||
{
|
||||
|
|
@ -760,11 +865,23 @@ static int cpg_mssr_reset_xlate(struct reset_controller_dev *rcdev,
|
|||
|
||||
static int cpg_mssr_reset_controller_register(struct cpg_mssr_priv *priv)
|
||||
{
|
||||
priv->rcdev.ops = &cpg_mssr_reset_ops;
|
||||
/*
|
||||
* RZ/T2H (and family) has the Module Reset Control Registers
|
||||
* which allows control resets of certain modules.
|
||||
* The number of resets is not equal to the number of module clocks.
|
||||
*/
|
||||
if (priv->reg_layout == CLK_REG_LAYOUT_RZ_T2H) {
|
||||
priv->rcdev.ops = &cpg_mrcr_reset_ops;
|
||||
priv->rcdev.nr_resets = ARRAY_SIZE(mrcr_for_rzt2h) * 32;
|
||||
} else {
|
||||
priv->rcdev.ops = &cpg_mssr_reset_ops;
|
||||
priv->rcdev.nr_resets = priv->num_mod_clks;
|
||||
}
|
||||
|
||||
priv->rcdev.of_node = priv->dev->of_node;
|
||||
priv->rcdev.of_reset_n_cells = 1;
|
||||
priv->rcdev.of_xlate = cpg_mssr_reset_xlate;
|
||||
priv->rcdev.nr_resets = priv->num_mod_clks;
|
||||
|
||||
return devm_reset_controller_register(priv->dev, &priv->rcdev);
|
||||
}
|
||||
|
||||
|
|
@ -1169,6 +1286,7 @@ static int __init cpg_mssr_common_init(struct device *dev,
|
|||
priv->control_regs = stbcr;
|
||||
} else if (priv->reg_layout == CLK_REG_LAYOUT_RZ_T2H) {
|
||||
priv->control_regs = mstpcr_for_rzt2h;
|
||||
priv->reset_regs = mrcr_for_rzt2h;
|
||||
} else if (priv->reg_layout == CLK_REG_LAYOUT_RCAR_GEN4) {
|
||||
priv->status_regs = mstpsr_for_gen4;
|
||||
priv->control_regs = mstpcr_for_gen4;
|
||||
|
|
@ -1265,8 +1383,7 @@ static int __init cpg_mssr_probe(struct platform_device *pdev)
|
|||
goto reserve_exit;
|
||||
|
||||
/* Reset Controller not supported for Standby Control SoCs */
|
||||
if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A ||
|
||||
priv->reg_layout == CLK_REG_LAYOUT_RZ_T2H)
|
||||
if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A)
|
||||
goto reserve_exit;
|
||||
|
||||
error = cpg_mssr_reset_controller_register(priv);
|
||||
|
|
|
|||
|
|
@ -1177,7 +1177,7 @@ rzg2l_cpg_register_core_clk(const struct cpg_core_clk *core,
|
|||
goto fail;
|
||||
}
|
||||
|
||||
if (IS_ERR_OR_NULL(clk))
|
||||
if (IS_ERR(clk))
|
||||
goto fail;
|
||||
|
||||
dev_dbg(dev, "Core clock %pC at %lu Hz\n", clk, clk_get_rate(clk));
|
||||
|
|
|
|||
|
|
@ -14,9 +14,14 @@
|
|||
#include <linux/bitfield.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/clk/renesas.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/iopoll.h>
|
||||
#include <linux/limits.h>
|
||||
#include <linux/math.h>
|
||||
#include <linux/math64.h>
|
||||
#include <linux/minmax.h>
|
||||
#include <linux/mod_devicetable.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/of.h>
|
||||
|
|
@ -26,6 +31,7 @@
|
|||
#include <linux/refcount.h>
|
||||
#include <linux/reset-controller.h>
|
||||
#include <linux/string_choices.h>
|
||||
#include <linux/units.h>
|
||||
|
||||
#include <dt-bindings/clock/renesas-cpg-mssr.h>
|
||||
|
||||
|
|
@ -47,13 +53,15 @@
|
|||
|
||||
#define CPG_PLL_STBY(x) ((x))
|
||||
#define CPG_PLL_STBY_RESETB BIT(0)
|
||||
#define CPG_PLL_STBY_SSC_EN BIT(2)
|
||||
#define CPG_PLL_STBY_RESETB_WEN BIT(16)
|
||||
#define CPG_PLL_STBY_SSC_EN_WEN BIT(18)
|
||||
#define CPG_PLL_CLK1(x) ((x) + 0x004)
|
||||
#define CPG_PLL_CLK1_KDIV(x) ((s16)FIELD_GET(GENMASK(31, 16), (x)))
|
||||
#define CPG_PLL_CLK1_MDIV(x) FIELD_GET(GENMASK(15, 6), (x))
|
||||
#define CPG_PLL_CLK1_PDIV(x) FIELD_GET(GENMASK(5, 0), (x))
|
||||
#define CPG_PLL_CLK1_KDIV GENMASK(31, 16)
|
||||
#define CPG_PLL_CLK1_MDIV GENMASK(15, 6)
|
||||
#define CPG_PLL_CLK1_PDIV GENMASK(5, 0)
|
||||
#define CPG_PLL_CLK2(x) ((x) + 0x008)
|
||||
#define CPG_PLL_CLK2_SDIV(x) FIELD_GET(GENMASK(2, 0), (x))
|
||||
#define CPG_PLL_CLK2_SDIV GENMASK(2, 0)
|
||||
#define CPG_PLL_MON(x) ((x) + 0x010)
|
||||
#define CPG_PLL_MON_RESETB BIT(0)
|
||||
#define CPG_PLL_MON_LOCK BIT(4)
|
||||
|
|
@ -65,6 +73,22 @@
|
|||
|
||||
#define CPG_CLKSTATUS0 (0x700)
|
||||
|
||||
/* On RZ/G3E SoC we have two DSI PLLs */
|
||||
#define MAX_CPG_DSI_PLL 2
|
||||
|
||||
/**
|
||||
* struct rzv2h_pll_dsi_info - PLL DSI information, holds the limits and parameters
|
||||
*
|
||||
* @pll_dsi_limits: PLL DSI parameters limits
|
||||
* @pll_dsi_parameters: Calculated PLL DSI parameters
|
||||
* @req_pll_dsi_rate: Requested PLL DSI rate
|
||||
*/
|
||||
struct rzv2h_pll_dsi_info {
|
||||
const struct rzv2h_pll_limits *pll_dsi_limits;
|
||||
struct rzv2h_pll_div_pars pll_dsi_parameters;
|
||||
unsigned long req_pll_dsi_rate;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct rzv2h_cpg_priv - Clock Pulse Generator Private Data
|
||||
*
|
||||
|
|
@ -80,6 +104,7 @@
|
|||
* @ff_mod_status_ops: Fixed Factor Module Status Clock operations
|
||||
* @mstop_count: Array of mstop values
|
||||
* @rcdev: Reset controller entity
|
||||
* @pll_dsi_info: Array of PLL DSI information, holds the limits and parameters
|
||||
*/
|
||||
struct rzv2h_cpg_priv {
|
||||
struct device *dev;
|
||||
|
|
@ -98,6 +123,8 @@ struct rzv2h_cpg_priv {
|
|||
atomic_t *mstop_count;
|
||||
|
||||
struct reset_controller_dev rcdev;
|
||||
|
||||
struct rzv2h_pll_dsi_info pll_dsi_info[MAX_CPG_DSI_PLL];
|
||||
};
|
||||
|
||||
#define rcdev_to_priv(x) container_of(x, struct rzv2h_cpg_priv, rcdev)
|
||||
|
|
@ -168,6 +195,460 @@ struct rzv2h_ff_mod_status_clk {
|
|||
#define to_rzv2h_ff_mod_status_clk(_hw) \
|
||||
container_of(_hw, struct rzv2h_ff_mod_status_clk, fix.hw)
|
||||
|
||||
/**
|
||||
* struct rzv2h_plldsi_div_clk - PLL DSI DDIV clock
|
||||
*
|
||||
* @dtable: divider table
|
||||
* @priv: CPG private data
|
||||
* @hw: divider clk
|
||||
* @ddiv: divider configuration
|
||||
*/
|
||||
struct rzv2h_plldsi_div_clk {
|
||||
const struct clk_div_table *dtable;
|
||||
struct rzv2h_cpg_priv *priv;
|
||||
struct clk_hw hw;
|
||||
struct ddiv ddiv;
|
||||
};
|
||||
|
||||
#define to_plldsi_div_clk(_hw) \
|
||||
container_of(_hw, struct rzv2h_plldsi_div_clk, hw)
|
||||
|
||||
#define RZ_V2H_OSC_CLK_IN_MEGA (24 * MEGA)
|
||||
#define RZV2H_MAX_DIV_TABLES (16)
|
||||
|
||||
/**
|
||||
* rzv2h_get_pll_pars - Finds the best combination of PLL parameters
|
||||
* for a given frequency.
|
||||
*
|
||||
* @limits: Pointer to the structure containing the limits for the PLL parameters
|
||||
* @pars: Pointer to the structure where the best calculated PLL parameters values
|
||||
* will be stored
|
||||
* @freq_millihz: Target output frequency in millihertz
|
||||
*
|
||||
* This function calculates the best set of PLL parameters (M, K, P, S) to achieve
|
||||
* the desired frequency.
|
||||
* There is no direct formula to calculate the PLL parameters, as it's an open
|
||||
* system of equations, therefore this function uses an iterative approach to
|
||||
* determine the best solution. The best solution is one that minimizes the error
|
||||
* (desired frequency - actual frequency).
|
||||
*
|
||||
* Return: true if a valid set of parameters values is found, false otherwise.
|
||||
*/
|
||||
bool rzv2h_get_pll_pars(const struct rzv2h_pll_limits *limits,
|
||||
struct rzv2h_pll_pars *pars, u64 freq_millihz)
|
||||
{
|
||||
u64 fout_min_millihz = mul_u32_u32(limits->fout.min, MILLI);
|
||||
u64 fout_max_millihz = mul_u32_u32(limits->fout.max, MILLI);
|
||||
struct rzv2h_pll_pars p, best;
|
||||
|
||||
if (freq_millihz > fout_max_millihz ||
|
||||
freq_millihz < fout_min_millihz)
|
||||
return false;
|
||||
|
||||
/* Initialize best error to maximum possible value */
|
||||
best.error_millihz = S64_MAX;
|
||||
|
||||
for (p.p = limits->p.min; p.p <= limits->p.max; p.p++) {
|
||||
u32 fref = RZ_V2H_OSC_CLK_IN_MEGA / p.p;
|
||||
u16 divider;
|
||||
|
||||
for (divider = 1 << limits->s.min, p.s = limits->s.min;
|
||||
p.s <= limits->s.max; p.s++, divider <<= 1) {
|
||||
for (p.m = limits->m.min; p.m <= limits->m.max; p.m++) {
|
||||
u64 output_m, output_k_range;
|
||||
s64 pll_k, output_k;
|
||||
u64 fvco, output;
|
||||
|
||||
/*
|
||||
* The frequency generated by the PLL + divider
|
||||
* is calculated as follows:
|
||||
*
|
||||
* With:
|
||||
* Freq = Ffout = Ffvco / 2^(pll_s)
|
||||
* Ffvco = (pll_m + (pll_k / 65536)) * Ffref
|
||||
* Ffref = 24MHz / pll_p
|
||||
*
|
||||
* Freq can also be rewritten as:
|
||||
* Freq = Ffvco / 2^(pll_s)
|
||||
* = ((pll_m + (pll_k / 65536)) * Ffref) / 2^(pll_s)
|
||||
* = (pll_m * Ffref) / 2^(pll_s) + ((pll_k / 65536) * Ffref) / 2^(pll_s)
|
||||
* = output_m + output_k
|
||||
*
|
||||
* Every parameter has been determined at this
|
||||
* point, but pll_k.
|
||||
*
|
||||
* Considering that:
|
||||
* limits->k.min <= pll_k <= limits->k.max
|
||||
* Then:
|
||||
* -0.5 <= (pll_k / 65536) < 0.5
|
||||
* Therefore:
|
||||
* -Ffref / (2 * 2^(pll_s)) <= output_k < Ffref / (2 * 2^(pll_s))
|
||||
*/
|
||||
|
||||
/* Compute output M component (in mHz) */
|
||||
output_m = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(p.m, fref) * MILLI,
|
||||
divider);
|
||||
/* Compute range for output K (in mHz) */
|
||||
output_k_range = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(fref, MILLI),
|
||||
2 * divider);
|
||||
/*
|
||||
* No point in continuing if we can't achieve
|
||||
* the desired frequency
|
||||
*/
|
||||
if (freq_millihz < (output_m - output_k_range) ||
|
||||
freq_millihz >= (output_m + output_k_range)) {
|
||||
continue;
|
||||
}
|
||||
|
||||
/*
|
||||
* Compute the K component
|
||||
*
|
||||
* Since:
|
||||
* Freq = output_m + output_k
|
||||
* Then:
|
||||
* output_k = Freq - output_m
|
||||
* = ((pll_k / 65536) * Ffref) / 2^(pll_s)
|
||||
* Therefore:
|
||||
* pll_k = (output_k * 65536 * 2^(pll_s)) / Ffref
|
||||
*/
|
||||
output_k = freq_millihz - output_m;
|
||||
pll_k = div_s64(output_k * 65536ULL * divider,
|
||||
fref);
|
||||
pll_k = DIV_S64_ROUND_CLOSEST(pll_k, MILLI);
|
||||
|
||||
/* Validate K value within allowed limits */
|
||||
if (pll_k < limits->k.min ||
|
||||
pll_k > limits->k.max)
|
||||
continue;
|
||||
|
||||
p.k = pll_k;
|
||||
|
||||
/* Compute (Ffvco * 65536) */
|
||||
fvco = mul_u32_u32(p.m * 65536 + p.k, fref);
|
||||
if (fvco < mul_u32_u32(limits->fvco.min, 65536) ||
|
||||
fvco > mul_u32_u32(limits->fvco.max, 65536))
|
||||
continue;
|
||||
|
||||
/* PLL_M component of (output * 65536 * PLL_P) */
|
||||
output = mul_u32_u32(p.m * 65536, RZ_V2H_OSC_CLK_IN_MEGA);
|
||||
/* PLL_K component of (output * 65536 * PLL_P) */
|
||||
output += p.k * RZ_V2H_OSC_CLK_IN_MEGA;
|
||||
/* Make it in mHz */
|
||||
output *= MILLI;
|
||||
output = DIV_U64_ROUND_CLOSEST(output, 65536 * p.p * divider);
|
||||
|
||||
/* Check output frequency against limits */
|
||||
if (output < fout_min_millihz ||
|
||||
output > fout_max_millihz)
|
||||
continue;
|
||||
|
||||
p.error_millihz = freq_millihz - output;
|
||||
p.freq_millihz = output;
|
||||
|
||||
/* If an exact match is found, return immediately */
|
||||
if (p.error_millihz == 0) {
|
||||
*pars = p;
|
||||
return true;
|
||||
}
|
||||
|
||||
/* Update best match if error is smaller */
|
||||
if (abs(best.error_millihz) > abs(p.error_millihz))
|
||||
best = p;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* If no valid parameters were found, return false */
|
||||
if (best.error_millihz == S64_MAX)
|
||||
return false;
|
||||
|
||||
*pars = best;
|
||||
return true;
|
||||
}
|
||||
EXPORT_SYMBOL_NS_GPL(rzv2h_get_pll_pars, "RZV2H_CPG");
|
||||
|
||||
/*
|
||||
* rzv2h_get_pll_divs_pars - Finds the best combination of PLL parameters
|
||||
* and divider value for a given frequency.
|
||||
*
|
||||
* @limits: Pointer to the structure containing the limits for the PLL parameters
|
||||
* @pars: Pointer to the structure where the best calculated PLL parameters and
|
||||
* divider values will be stored
|
||||
* @table: Pointer to the array of valid divider values
|
||||
* @table_size: Size of the divider values array
|
||||
* @freq_millihz: Target output frequency in millihertz
|
||||
*
|
||||
* This function calculates the best set of PLL parameters (M, K, P, S) and divider
|
||||
* value to achieve the desired frequency. See rzv2h_get_pll_pars() for more details
|
||||
* on how the PLL parameters are calculated.
|
||||
*
|
||||
* freq_millihz is the desired frequency generated by the PLL followed by a
|
||||
* a gear.
|
||||
*/
|
||||
bool rzv2h_get_pll_divs_pars(const struct rzv2h_pll_limits *limits,
|
||||
struct rzv2h_pll_div_pars *pars,
|
||||
const u8 *table, u8 table_size, u64 freq_millihz)
|
||||
{
|
||||
struct rzv2h_pll_div_pars p, best;
|
||||
|
||||
best.div.error_millihz = S64_MAX;
|
||||
p.div.error_millihz = S64_MAX;
|
||||
for (unsigned int i = 0; i < table_size; i++) {
|
||||
if (!rzv2h_get_pll_pars(limits, &p.pll, freq_millihz * table[i]))
|
||||
continue;
|
||||
|
||||
p.div.divider_value = table[i];
|
||||
p.div.freq_millihz = DIV_U64_ROUND_CLOSEST(p.pll.freq_millihz, table[i]);
|
||||
p.div.error_millihz = freq_millihz - p.div.freq_millihz;
|
||||
|
||||
if (p.div.error_millihz == 0) {
|
||||
*pars = p;
|
||||
return true;
|
||||
}
|
||||
|
||||
if (abs(best.div.error_millihz) > abs(p.div.error_millihz))
|
||||
best = p;
|
||||
}
|
||||
|
||||
if (best.div.error_millihz == S64_MAX)
|
||||
return false;
|
||||
|
||||
*pars = best;
|
||||
return true;
|
||||
}
|
||||
EXPORT_SYMBOL_NS_GPL(rzv2h_get_pll_divs_pars, "RZV2H_CPG");
|
||||
|
||||
static unsigned long rzv2h_cpg_plldsi_div_recalc_rate(struct clk_hw *hw,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
struct rzv2h_plldsi_div_clk *dsi_div = to_plldsi_div_clk(hw);
|
||||
struct rzv2h_cpg_priv *priv = dsi_div->priv;
|
||||
struct ddiv ddiv = dsi_div->ddiv;
|
||||
u32 div;
|
||||
|
||||
div = readl(priv->base + ddiv.offset);
|
||||
div >>= ddiv.shift;
|
||||
div &= clk_div_mask(ddiv.width);
|
||||
div = dsi_div->dtable[div].div;
|
||||
|
||||
return DIV_ROUND_CLOSEST_ULL(parent_rate, div);
|
||||
}
|
||||
|
||||
static int rzv2h_cpg_plldsi_div_determine_rate(struct clk_hw *hw,
|
||||
struct clk_rate_request *req)
|
||||
{
|
||||
struct rzv2h_plldsi_div_clk *dsi_div = to_plldsi_div_clk(hw);
|
||||
struct pll_clk *pll_clk = to_pll(clk_hw_get_parent(hw));
|
||||
struct rzv2h_cpg_priv *priv = dsi_div->priv;
|
||||
u8 table[RZV2H_MAX_DIV_TABLES] = { 0 };
|
||||
struct rzv2h_pll_div_pars *dsi_params;
|
||||
struct rzv2h_pll_dsi_info *dsi_info;
|
||||
const struct clk_div_table *div;
|
||||
unsigned int i = 0;
|
||||
u64 rate_millihz;
|
||||
|
||||
dsi_info = &priv->pll_dsi_info[pll_clk->pll.instance];
|
||||
dsi_params = &dsi_info->pll_dsi_parameters;
|
||||
|
||||
rate_millihz = mul_u32_u32(req->rate, MILLI);
|
||||
if (rate_millihz == dsi_params->div.error_millihz + dsi_params->div.freq_millihz)
|
||||
goto exit_determine_rate;
|
||||
|
||||
for (div = dsi_div->dtable; div->div; div++) {
|
||||
if (i >= RZV2H_MAX_DIV_TABLES)
|
||||
return -EINVAL;
|
||||
table[i++] = div->div;
|
||||
}
|
||||
|
||||
if (!rzv2h_get_pll_divs_pars(dsi_info->pll_dsi_limits, dsi_params, table, i,
|
||||
rate_millihz)) {
|
||||
dev_err(priv->dev, "failed to determine rate for req->rate: %lu\n",
|
||||
req->rate);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
exit_determine_rate:
|
||||
req->rate = DIV_ROUND_CLOSEST_ULL(dsi_params->div.freq_millihz, MILLI);
|
||||
req->best_parent_rate = req->rate * dsi_params->div.divider_value;
|
||||
dsi_info->req_pll_dsi_rate = req->best_parent_rate;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int rzv2h_cpg_plldsi_div_set_rate(struct clk_hw *hw,
|
||||
unsigned long rate,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
struct rzv2h_plldsi_div_clk *dsi_div = to_plldsi_div_clk(hw);
|
||||
struct pll_clk *pll_clk = to_pll(clk_hw_get_parent(hw));
|
||||
struct rzv2h_cpg_priv *priv = dsi_div->priv;
|
||||
struct rzv2h_pll_div_pars *dsi_params;
|
||||
struct rzv2h_pll_dsi_info *dsi_info;
|
||||
struct ddiv ddiv = dsi_div->ddiv;
|
||||
const struct clk_div_table *clkt;
|
||||
bool divider_found = false;
|
||||
u32 val, shift;
|
||||
|
||||
dsi_info = &priv->pll_dsi_info[pll_clk->pll.instance];
|
||||
dsi_params = &dsi_info->pll_dsi_parameters;
|
||||
|
||||
for (clkt = dsi_div->dtable; clkt->div; clkt++) {
|
||||
if (clkt->div == dsi_params->div.divider_value) {
|
||||
divider_found = true;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if (!divider_found)
|
||||
return -EINVAL;
|
||||
|
||||
shift = ddiv.shift;
|
||||
val = readl(priv->base + ddiv.offset) | DDIV_DIVCTL_WEN(shift);
|
||||
val &= ~(clk_div_mask(ddiv.width) << shift);
|
||||
val |= clkt->val << shift;
|
||||
writel(val, priv->base + ddiv.offset);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct clk_ops rzv2h_cpg_plldsi_div_ops = {
|
||||
.recalc_rate = rzv2h_cpg_plldsi_div_recalc_rate,
|
||||
.determine_rate = rzv2h_cpg_plldsi_div_determine_rate,
|
||||
.set_rate = rzv2h_cpg_plldsi_div_set_rate,
|
||||
};
|
||||
|
||||
static struct clk * __init
|
||||
rzv2h_cpg_plldsi_div_clk_register(const struct cpg_core_clk *core,
|
||||
struct rzv2h_cpg_priv *priv)
|
||||
{
|
||||
struct rzv2h_plldsi_div_clk *clk_hw_data;
|
||||
struct clk **clks = priv->clks;
|
||||
struct clk_init_data init;
|
||||
const struct clk *parent;
|
||||
const char *parent_name;
|
||||
struct clk_hw *clk_hw;
|
||||
int ret;
|
||||
|
||||
parent = clks[core->parent];
|
||||
if (IS_ERR(parent))
|
||||
return ERR_CAST(parent);
|
||||
|
||||
clk_hw_data = devm_kzalloc(priv->dev, sizeof(*clk_hw_data), GFP_KERNEL);
|
||||
if (!clk_hw_data)
|
||||
return ERR_PTR(-ENOMEM);
|
||||
|
||||
clk_hw_data->priv = priv;
|
||||
clk_hw_data->ddiv = core->cfg.ddiv;
|
||||
clk_hw_data->dtable = core->dtable;
|
||||
|
||||
parent_name = __clk_get_name(parent);
|
||||
init.name = core->name;
|
||||
init.ops = &rzv2h_cpg_plldsi_div_ops;
|
||||
init.flags = core->flag;
|
||||
init.parent_names = &parent_name;
|
||||
init.num_parents = 1;
|
||||
|
||||
clk_hw = &clk_hw_data->hw;
|
||||
clk_hw->init = &init;
|
||||
|
||||
ret = devm_clk_hw_register(priv->dev, clk_hw);
|
||||
if (ret)
|
||||
return ERR_PTR(ret);
|
||||
|
||||
return clk_hw->clk;
|
||||
}
|
||||
|
||||
static int rzv2h_cpg_plldsi_determine_rate(struct clk_hw *hw,
|
||||
struct clk_rate_request *req)
|
||||
{
|
||||
struct pll_clk *pll_clk = to_pll(hw);
|
||||
struct rzv2h_cpg_priv *priv = pll_clk->priv;
|
||||
struct rzv2h_pll_dsi_info *dsi_info;
|
||||
u64 rate_millihz;
|
||||
|
||||
dsi_info = &priv->pll_dsi_info[pll_clk->pll.instance];
|
||||
/* check if the divider has already invoked the algorithm */
|
||||
if (req->rate == dsi_info->req_pll_dsi_rate)
|
||||
return 0;
|
||||
|
||||
/* If the req->rate doesn't match we do the calculation assuming there is no divider */
|
||||
rate_millihz = mul_u32_u32(req->rate, MILLI);
|
||||
if (!rzv2h_get_pll_pars(dsi_info->pll_dsi_limits,
|
||||
&dsi_info->pll_dsi_parameters.pll, rate_millihz)) {
|
||||
dev_err(priv->dev,
|
||||
"failed to determine rate for req->rate: %lu\n",
|
||||
req->rate);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
req->rate = DIV_ROUND_CLOSEST_ULL(dsi_info->pll_dsi_parameters.pll.freq_millihz, MILLI);
|
||||
dsi_info->req_pll_dsi_rate = req->rate;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int rzv2h_cpg_pll_set_rate(struct pll_clk *pll_clk,
|
||||
struct rzv2h_pll_pars *params,
|
||||
bool ssc_disable)
|
||||
{
|
||||
struct rzv2h_cpg_priv *priv = pll_clk->priv;
|
||||
u16 offset = pll_clk->pll.offset;
|
||||
u32 val;
|
||||
int ret;
|
||||
|
||||
/* Put PLL into standby mode */
|
||||
writel(CPG_PLL_STBY_RESETB_WEN, priv->base + CPG_PLL_STBY(offset));
|
||||
ret = readl_poll_timeout_atomic(priv->base + CPG_PLL_MON(offset),
|
||||
val, !(val & CPG_PLL_MON_LOCK),
|
||||
100, 2000);
|
||||
if (ret) {
|
||||
dev_err(priv->dev, "Failed to put PLLDSI into standby mode");
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* Output clock setting 1 */
|
||||
writel(FIELD_PREP(CPG_PLL_CLK1_KDIV, (u16)params->k) |
|
||||
FIELD_PREP(CPG_PLL_CLK1_MDIV, params->m) |
|
||||
FIELD_PREP(CPG_PLL_CLK1_PDIV, params->p),
|
||||
priv->base + CPG_PLL_CLK1(offset));
|
||||
|
||||
/* Output clock setting 2 */
|
||||
val = readl(priv->base + CPG_PLL_CLK2(offset));
|
||||
writel((val & ~CPG_PLL_CLK2_SDIV) | FIELD_PREP(CPG_PLL_CLK2_SDIV, params->s),
|
||||
priv->base + CPG_PLL_CLK2(offset));
|
||||
|
||||
/* Put PLL to normal mode */
|
||||
if (ssc_disable)
|
||||
val = CPG_PLL_STBY_SSC_EN_WEN;
|
||||
else
|
||||
val = CPG_PLL_STBY_SSC_EN_WEN | CPG_PLL_STBY_SSC_EN;
|
||||
writel(val | CPG_PLL_STBY_RESETB_WEN | CPG_PLL_STBY_RESETB,
|
||||
priv->base + CPG_PLL_STBY(offset));
|
||||
|
||||
/* PLL normal mode transition, output clock stability check */
|
||||
ret = readl_poll_timeout_atomic(priv->base + CPG_PLL_MON(offset),
|
||||
val, (val & CPG_PLL_MON_LOCK),
|
||||
100, 2000);
|
||||
if (ret) {
|
||||
dev_err(priv->dev, "Failed to put PLLDSI into normal mode");
|
||||
return ret;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int rzv2h_cpg_plldsi_set_rate(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
struct pll_clk *pll_clk = to_pll(hw);
|
||||
struct rzv2h_pll_dsi_info *dsi_info;
|
||||
struct rzv2h_cpg_priv *priv = pll_clk->priv;
|
||||
|
||||
dsi_info = &priv->pll_dsi_info[pll_clk->pll.instance];
|
||||
|
||||
return rzv2h_cpg_pll_set_rate(pll_clk, &dsi_info->pll_dsi_parameters.pll, true);
|
||||
}
|
||||
|
||||
static int rzv2h_cpg_pll_clk_is_enabled(struct clk_hw *hw)
|
||||
{
|
||||
struct pll_clk *pll_clk = to_pll(hw);
|
||||
|
|
@ -231,12 +712,19 @@ static unsigned long rzv2h_cpg_pll_clk_recalc_rate(struct clk_hw *hw,
|
|||
clk1 = readl(priv->base + CPG_PLL_CLK1(pll.offset));
|
||||
clk2 = readl(priv->base + CPG_PLL_CLK2(pll.offset));
|
||||
|
||||
rate = mul_u64_u32_shr(parent_rate, (CPG_PLL_CLK1_MDIV(clk1) << 16) +
|
||||
CPG_PLL_CLK1_KDIV(clk1), 16 + CPG_PLL_CLK2_SDIV(clk2));
|
||||
rate = mul_u64_u32_shr(parent_rate, (FIELD_GET(CPG_PLL_CLK1_MDIV, clk1) << 16) +
|
||||
(s16)FIELD_GET(CPG_PLL_CLK1_KDIV, clk1),
|
||||
16 + FIELD_GET(CPG_PLL_CLK2_SDIV, clk2));
|
||||
|
||||
return DIV_ROUND_CLOSEST_ULL(rate, CPG_PLL_CLK1_PDIV(clk1));
|
||||
return DIV_ROUND_CLOSEST_ULL(rate, FIELD_GET(CPG_PLL_CLK1_PDIV, clk1));
|
||||
}
|
||||
|
||||
static const struct clk_ops rzv2h_cpg_plldsi_ops = {
|
||||
.recalc_rate = rzv2h_cpg_pll_clk_recalc_rate,
|
||||
.determine_rate = rzv2h_cpg_plldsi_determine_rate,
|
||||
.set_rate = rzv2h_cpg_plldsi_set_rate,
|
||||
};
|
||||
|
||||
static const struct clk_ops rzv2h_cpg_pll_ops = {
|
||||
.is_enabled = rzv2h_cpg_pll_clk_is_enabled,
|
||||
.enable = rzv2h_cpg_pll_clk_enable,
|
||||
|
|
@ -263,6 +751,10 @@ rzv2h_cpg_pll_clk_register(const struct cpg_core_clk *core,
|
|||
if (!pll_clk)
|
||||
return ERR_PTR(-ENOMEM);
|
||||
|
||||
if (core->type == CLK_TYPE_PLLDSI)
|
||||
priv->pll_dsi_info[core->cfg.pll.instance].pll_dsi_limits =
|
||||
core->cfg.pll.limits;
|
||||
|
||||
parent_name = __clk_get_name(parent);
|
||||
init.name = core->name;
|
||||
init.ops = ops;
|
||||
|
|
@ -587,11 +1079,17 @@ rzv2h_cpg_register_core_clk(const struct cpg_core_clk *core,
|
|||
case CLK_TYPE_SMUX:
|
||||
clk = rzv2h_cpg_mux_clk_register(core, priv);
|
||||
break;
|
||||
case CLK_TYPE_PLLDSI:
|
||||
clk = rzv2h_cpg_pll_clk_register(core, priv, &rzv2h_cpg_plldsi_ops);
|
||||
break;
|
||||
case CLK_TYPE_PLLDSI_DIV:
|
||||
clk = rzv2h_cpg_plldsi_div_clk_register(core, priv);
|
||||
break;
|
||||
default:
|
||||
goto fail;
|
||||
}
|
||||
|
||||
if (IS_ERR_OR_NULL(clk))
|
||||
if (IS_ERR(clk))
|
||||
goto fail;
|
||||
|
||||
dev_dbg(dev, "Core clock %pC at %lu Hz\n", clk, clk_get_rate(clk));
|
||||
|
|
|
|||
|
|
@ -16,20 +16,28 @@
|
|||
*
|
||||
* @offset: STBY register offset
|
||||
* @has_clkn: Flag to indicate if CLK1/2 are accessible or not
|
||||
* @instance: PLL instance number
|
||||
*/
|
||||
struct pll {
|
||||
unsigned int offset:9;
|
||||
unsigned int has_clkn:1;
|
||||
unsigned int instance:2;
|
||||
const struct rzv2h_pll_limits *limits;
|
||||
};
|
||||
|
||||
#define PLL_PACK(_offset, _has_clkn) \
|
||||
#define PLL_PACK_LIMITS(_offset, _has_clkn, _instance, _limits) \
|
||||
((struct pll){ \
|
||||
.offset = _offset, \
|
||||
.has_clkn = _has_clkn \
|
||||
.has_clkn = _has_clkn, \
|
||||
.instance = _instance, \
|
||||
.limits = _limits \
|
||||
})
|
||||
|
||||
#define PLLCA55 PLL_PACK(0x60, 1)
|
||||
#define PLLGPU PLL_PACK(0x120, 1)
|
||||
#define PLL_PACK(_offset, _has_clkn, _instance) \
|
||||
PLL_PACK_LIMITS(_offset, _has_clkn, _instance, NULL)
|
||||
|
||||
#define PLLCA55 PLL_PACK(0x60, 1, 0)
|
||||
#define PLLGPU PLL_PACK(0x120, 1, 0)
|
||||
|
||||
/**
|
||||
* struct ddiv - Structure for dynamic switching divider
|
||||
|
|
@ -115,9 +123,11 @@ struct fixed_mod_conf {
|
|||
#define CPG_SSEL1 (0x304)
|
||||
#define CPG_CDDIV0 (0x400)
|
||||
#define CPG_CDDIV1 (0x404)
|
||||
#define CPG_CDDIV2 (0x408)
|
||||
#define CPG_CDDIV3 (0x40C)
|
||||
#define CPG_CDDIV4 (0x410)
|
||||
#define CPG_CSDIV0 (0x500)
|
||||
#define CPG_CSDIV1 (0x504)
|
||||
|
||||
#define CDDIV0_DIVCTL1 DDIV_PACK(CPG_CDDIV0, 4, 3, 1)
|
||||
#define CDDIV0_DIVCTL2 DDIV_PACK(CPG_CDDIV0, 8, 3, 2)
|
||||
|
|
@ -125,6 +135,7 @@ struct fixed_mod_conf {
|
|||
#define CDDIV1_DIVCTL1 DDIV_PACK(CPG_CDDIV1, 4, 2, 5)
|
||||
#define CDDIV1_DIVCTL2 DDIV_PACK(CPG_CDDIV1, 8, 2, 6)
|
||||
#define CDDIV1_DIVCTL3 DDIV_PACK(CPG_CDDIV1, 12, 2, 7)
|
||||
#define CDDIV2_DIVCTL3 DDIV_PACK(CPG_CDDIV2, 12, 3, 11)
|
||||
#define CDDIV3_DIVCTL1 DDIV_PACK(CPG_CDDIV3, 4, 3, 13)
|
||||
#define CDDIV3_DIVCTL2 DDIV_PACK(CPG_CDDIV3, 8, 3, 14)
|
||||
#define CDDIV3_DIVCTL3 DDIV_PACK(CPG_CDDIV3, 12, 1, 15)
|
||||
|
|
@ -134,7 +145,9 @@ struct fixed_mod_conf {
|
|||
|
||||
#define CSDIV0_DIVCTL0 DDIV_PACK(CPG_CSDIV0, 0, 2, CSDIV_NO_MON)
|
||||
#define CSDIV0_DIVCTL1 DDIV_PACK(CPG_CSDIV0, 4, 2, CSDIV_NO_MON)
|
||||
#define CSDIV0_DIVCTL2 DDIV_PACK(CPG_CSDIV0, 8, 2, CSDIV_NO_MON)
|
||||
#define CSDIV0_DIVCTL3 DDIV_PACK_NO_RMW(CPG_CSDIV0, 12, 2, CSDIV_NO_MON)
|
||||
#define CSDIV1_DIVCTL2 DDIV_PACK(CPG_CSDIV1, 8, 4, CSDIV_NO_MON)
|
||||
|
||||
#define SSEL0_SELCTL2 SMUX_PACK(CPG_SSEL0, 8, 1)
|
||||
#define SSEL0_SELCTL3 SMUX_PACK(CPG_SSEL0, 12, 1)
|
||||
|
|
@ -188,6 +201,8 @@ enum clk_types {
|
|||
CLK_TYPE_PLL,
|
||||
CLK_TYPE_DDIV, /* Dynamic Switching Divider */
|
||||
CLK_TYPE_SMUX, /* Static Mux */
|
||||
CLK_TYPE_PLLDSI, /* PLLDSI */
|
||||
CLK_TYPE_PLLDSI_DIV, /* PLLDSI divider */
|
||||
};
|
||||
|
||||
#define DEF_TYPE(_name, _id, _type...) \
|
||||
|
|
@ -218,6 +233,14 @@ enum clk_types {
|
|||
.num_parents = ARRAY_SIZE(_parent_names), \
|
||||
.flag = CLK_SET_RATE_PARENT, \
|
||||
.mux_flags = CLK_MUX_HIWORD_MASK)
|
||||
#define DEF_PLLDSI(_name, _id, _parent, _pll_packed) \
|
||||
DEF_TYPE(_name, _id, CLK_TYPE_PLLDSI, .parent = _parent, .cfg.pll = _pll_packed)
|
||||
#define DEF_PLLDSI_DIV(_name, _id, _parent, _ddiv_packed, _dtable) \
|
||||
DEF_TYPE(_name, _id, CLK_TYPE_PLLDSI_DIV, \
|
||||
.cfg.ddiv = _ddiv_packed, \
|
||||
.dtable = _dtable, \
|
||||
.parent = _parent, \
|
||||
.flag = CLK_SET_RATE_PARENT)
|
||||
|
||||
/**
|
||||
* struct rzv2h_mod_clk - Module Clocks definitions
|
||||
|
|
|
|||
|
|
@ -22,5 +22,7 @@
|
|||
#define R9A09G047_GBETH_1_CLK_PTP_REF_I 11
|
||||
#define R9A09G047_USB3_0_REF_ALT_CLK_P 12
|
||||
#define R9A09G047_USB3_0_CLKCORE 13
|
||||
#define R9A09G047_USB2_0_CLK_CORE0 14
|
||||
#define R9A09G047_USB2_0_CLK_CORE1 15
|
||||
|
||||
#endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G047_CPG_H__ */
|
||||
|
|
|
|||
|
|
@ -10,7 +10,9 @@
|
|||
#ifndef __LINUX_CLK_RENESAS_H_
|
||||
#define __LINUX_CLK_RENESAS_H_
|
||||
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/types.h>
|
||||
#include <linux/units.h>
|
||||
|
||||
struct device;
|
||||
struct device_node;
|
||||
|
|
@ -32,4 +34,147 @@ void cpg_mssr_detach_dev(struct generic_pm_domain *unused, struct device *dev);
|
|||
#define cpg_mssr_attach_dev NULL
|
||||
#define cpg_mssr_detach_dev NULL
|
||||
#endif
|
||||
|
||||
/**
|
||||
* struct rzv2h_pll_limits - PLL parameter constraints
|
||||
*
|
||||
* This structure defines the minimum and maximum allowed values for
|
||||
* various parameters used to configure a PLL. These limits ensure
|
||||
* the PLL operates within valid and stable ranges.
|
||||
*
|
||||
* @fout: Output frequency range (in MHz)
|
||||
* @fout.min: Minimum allowed output frequency
|
||||
* @fout.max: Maximum allowed output frequency
|
||||
*
|
||||
* @fvco: PLL oscillation frequency range (in MHz)
|
||||
* @fvco.min: Minimum allowed VCO frequency
|
||||
* @fvco.max: Maximum allowed VCO frequency
|
||||
*
|
||||
* @m: Main-divider range
|
||||
* @m.min: Minimum main-divider value
|
||||
* @m.max: Maximum main-divider value
|
||||
*
|
||||
* @p: Pre-divider range
|
||||
* @p.min: Minimum pre-divider value
|
||||
* @p.max: Maximum pre-divider value
|
||||
*
|
||||
* @s: Divider range
|
||||
* @s.min: Minimum divider value
|
||||
* @s.max: Maximum divider value
|
||||
*
|
||||
* @k: Delta-sigma modulator range (signed)
|
||||
* @k.min: Minimum delta-sigma value
|
||||
* @k.max: Maximum delta-sigma value
|
||||
*/
|
||||
struct rzv2h_pll_limits {
|
||||
struct {
|
||||
u32 min;
|
||||
u32 max;
|
||||
} fout;
|
||||
|
||||
struct {
|
||||
u32 min;
|
||||
u32 max;
|
||||
} fvco;
|
||||
|
||||
struct {
|
||||
u16 min;
|
||||
u16 max;
|
||||
} m;
|
||||
|
||||
struct {
|
||||
u8 min;
|
||||
u8 max;
|
||||
} p;
|
||||
|
||||
struct {
|
||||
u8 min;
|
||||
u8 max;
|
||||
} s;
|
||||
|
||||
struct {
|
||||
s16 min;
|
||||
s16 max;
|
||||
} k;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct rzv2h_pll_pars - PLL configuration parameters
|
||||
*
|
||||
* This structure contains the configuration parameters for the
|
||||
* Phase-Locked Loop (PLL), used to achieve a specific output frequency.
|
||||
*
|
||||
* @m: Main divider value
|
||||
* @p: Pre-divider value
|
||||
* @s: Output divider value
|
||||
* @k: Delta-sigma modulation value
|
||||
* @freq_millihz: Calculated PLL output frequency in millihertz
|
||||
* @error_millihz: Frequency error from target in millihertz (signed)
|
||||
*/
|
||||
struct rzv2h_pll_pars {
|
||||
u16 m;
|
||||
u8 p;
|
||||
u8 s;
|
||||
s16 k;
|
||||
u64 freq_millihz;
|
||||
s64 error_millihz;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct rzv2h_pll_div_pars - PLL parameters with post-divider
|
||||
*
|
||||
* This structure is used for PLLs that include an additional post-divider
|
||||
* stage after the main PLL block. It contains both the PLL configuration
|
||||
* parameters and the resulting frequency/error values after the divider.
|
||||
*
|
||||
* @pll: Main PLL configuration parameters (see struct rzv2h_pll_pars)
|
||||
*
|
||||
* @div: Post-divider configuration and result
|
||||
* @div.divider_value: Divider applied to the PLL output
|
||||
* @div.freq_millihz: Output frequency after divider in millihertz
|
||||
* @div.error_millihz: Frequency error from target in millihertz (signed)
|
||||
*/
|
||||
struct rzv2h_pll_div_pars {
|
||||
struct rzv2h_pll_pars pll;
|
||||
struct {
|
||||
u8 divider_value;
|
||||
u64 freq_millihz;
|
||||
s64 error_millihz;
|
||||
} div;
|
||||
};
|
||||
|
||||
#define RZV2H_CPG_PLL_DSI_LIMITS(name) \
|
||||
static const struct rzv2h_pll_limits (name) = { \
|
||||
.fout = { .min = 25 * MEGA, .max = 375 * MEGA }, \
|
||||
.fvco = { .min = 1600 * MEGA, .max = 3200 * MEGA }, \
|
||||
.m = { .min = 64, .max = 533 }, \
|
||||
.p = { .min = 1, .max = 4 }, \
|
||||
.s = { .min = 0, .max = 6 }, \
|
||||
.k = { .min = -32768, .max = 32767 }, \
|
||||
} \
|
||||
|
||||
#ifdef CONFIG_CLK_RZV2H
|
||||
bool rzv2h_get_pll_pars(const struct rzv2h_pll_limits *limits,
|
||||
struct rzv2h_pll_pars *pars, u64 freq_millihz);
|
||||
|
||||
bool rzv2h_get_pll_divs_pars(const struct rzv2h_pll_limits *limits,
|
||||
struct rzv2h_pll_div_pars *pars,
|
||||
const u8 *table, u8 table_size, u64 freq_millihz);
|
||||
#else
|
||||
static inline bool rzv2h_get_pll_pars(const struct rzv2h_pll_limits *limits,
|
||||
struct rzv2h_pll_pars *pars,
|
||||
u64 freq_millihz)
|
||||
{
|
||||
return false;
|
||||
}
|
||||
|
||||
static inline bool rzv2h_get_pll_divs_pars(const struct rzv2h_pll_limits *limits,
|
||||
struct rzv2h_pll_div_pars *pars,
|
||||
const u8 *table, u8 table_size,
|
||||
u64 freq_millihz)
|
||||
{
|
||||
return false;
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user