arm64: dts: renesas: r8a779g0: Add MFIS node

Describe the MFIS core which is used for various tasks including
inter-processor communication.  Interrupt numbers look irregular but
they all work as expected on a Renesas R-Car V4H SparrowHawk board.

Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20260602182157.304964-2-wsa+renesas@sang-engineering.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This commit is contained in:
Wolfram Sang 2026-06-02 20:21:09 +02:00 committed by Geert Uytterhoeven
parent 9f115f9c31
commit f0de09f7de

View File

@ -589,6 +589,23 @@ tmu4: timer@ffc00000 {
status = "disabled";
};
mfis: system-controller@e6260000 {
compatible = "renesas,r8a779g0-mfis";
reg = <0 0xe6260000 0 0x10000>;
reg-names = "common";
interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 916 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 918 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 920 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 922 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "ch0e", "ch1e", "ch2e", "ch3e", "ch4e", "ch5e",
"ch6e", "ch7e", "ch8e", "ch9e", "ch10e", "ch11e";
#hwlock-cells = <1>;
#mbox-cells = <2>;
status = "disabled";
};
tsn0: ethernet@e6460000 {
compatible = "renesas,r8a779g0-ethertsn", "renesas,rcar-gen4-ethertsn";
reg = <0 0xe6460000 0 0x7000>,