github-mirror/linux
1
0
Fork 0
mirror of https://github.com/torvalds/linux.git synced 2026-09-28 12:02:03 +02:00
Code Issues Actions Packages Projects Releases Wiki Activity Graph

arm64: dts: renesas: r8a78000: Enable application CPU cores via PSCI

Browse Source 
Add PSCI "enable-method" DT properties to all application CPU cores.
This allows the OS to bring application CPU cores up and down.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20260601113919.8327-1-marek.vasut+renesas@mailbox.org
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This commit is contained in:
Marek Vasut 2026-06-01 13:38:51 +02:00 committed by Geert Uytterhoeven
parent db60b8a615
commit 9f115f9c31
1 changed files with 32 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

32
arch/arm64/boot/dts/renesas/r8a78000.dtsi
View File

@ -143,6 +143,7 @@ a720_0: cpu@0 {
compatible = "arm,cortex-a720ae";
reg = <0x0 0x0>;
device_type = "cpu";
enable-method = "psci";
next-level-cache = <&L2_CA720_0>;
};
@ -150,6 +151,7 @@ a720_1: cpu@100 {
compatible = "arm,cortex-a720ae";
reg = <0x0 0x100>;
device_type = "cpu";
enable-method = "psci";
next-level-cache = <&L2_CA720_1>;
};
@ -157,6 +159,7 @@ a720_2: cpu@200 {
compatible = "arm,cortex-a720ae";
reg = <0x0 0x200>;
device_type = "cpu";
enable-method = "psci";
next-level-cache = <&L2_CA720_2>;
};
@ -164,6 +167,7 @@ a720_3: cpu@300 {
compatible = "arm,cortex-a720ae";
reg = <0x0 0x300>;
device_type = "cpu";
enable-method = "psci";
next-level-cache = <&L2_CA720_3>;
};
@ -171,6 +175,7 @@ a720_4: cpu@10000 {
compatible = "arm,cortex-a720ae";
reg = <0x0 0x10000>;
device_type = "cpu";
enable-method = "psci";
next-level-cache = <&L2_CA720_4>;
};
@ -178,6 +183,7 @@ a720_5: cpu@10100 {
compatible = "arm,cortex-a720ae";
reg = <0x0 0x10100>;
device_type = "cpu";
enable-method = "psci";
next-level-cache = <&L2_CA720_5>;
};
@ -185,6 +191,7 @@ a720_6: cpu@10200 {
compatible = "arm,cortex-a720ae";
reg = <0x0 0x10200>;
device_type = "cpu";
enable-method = "psci";
next-level-cache = <&L2_CA720_6>;
};
@ -192,6 +199,7 @@ a720_7: cpu@10300 {
compatible = "arm,cortex-a720ae";
reg = <0x0 0x10300>;
device_type = "cpu";
enable-method = "psci";
next-level-cache = <&L2_CA720_7>;
};
@ -199,6 +207,7 @@ a720_8: cpu@20000 {
compatible = "arm,cortex-a720ae";
reg = <0x0 0x20000>;
device_type = "cpu";
enable-method = "psci";
next-level-cache = <&L2_CA720_8>;
};
@ -206,6 +215,7 @@ a720_9: cpu@20100 {
compatible = "arm,cortex-a720ae";
reg = <0x0 0x20100>;
device_type = "cpu";
enable-method = "psci";
next-level-cache = <&L2_CA720_9>;
};
@ -213,6 +223,7 @@ a720_10: cpu@20200 {
compatible = "arm,cortex-a720ae";
reg = <0x0 0x20200>;
device_type = "cpu";
enable-method = "psci";
next-level-cache = <&L2_CA720_10>;
};
@ -220,6 +231,7 @@ a720_11: cpu@20300 {
compatible = "arm,cortex-a720ae";
reg = <0x0 0x20300>;
device_type = "cpu";
enable-method = "psci";
next-level-cache = <&L2_CA720_11>;
};
@ -227,6 +239,7 @@ a720_12: cpu@30000 {
compatible = "arm,cortex-a720ae";
reg = <0x0 0x30000>;
device_type = "cpu";
enable-method = "psci";
next-level-cache = <&L2_CA720_12>;
};
@ -234,6 +247,7 @@ a720_13: cpu@30100 {
compatible = "arm,cortex-a720ae";
reg = <0x0 0x30100>;
device_type = "cpu";
enable-method = "psci";
next-level-cache = <&L2_CA720_13>;
};
@ -241,6 +255,7 @@ a720_14: cpu@30200 {
compatible = "arm,cortex-a720ae";
reg = <0x0 0x30200>;
device_type = "cpu";
enable-method = "psci";
next-level-cache = <&L2_CA720_14>;
};
@ -248,6 +263,7 @@ a720_15: cpu@30300 {
compatible = "arm,cortex-a720ae";
reg = <0x0 0x30300>;
device_type = "cpu";
enable-method = "psci";
next-level-cache = <&L2_CA720_15>;
};
@ -255,6 +271,7 @@ a720_16: cpu@40000 {
compatible = "arm,cortex-a720ae";
reg = <0x0 0x40000>;
device_type = "cpu";
enable-method = "psci";
next-level-cache = <&L2_CA720_16>;
};
@ -262,6 +279,7 @@ a720_17: cpu@40100 {
compatible = "arm,cortex-a720ae";
reg = <0x0 0x40100>;
device_type = "cpu";
enable-method = "psci";
next-level-cache = <&L2_CA720_17>;
};
@ -269,6 +287,7 @@ a720_18: cpu@40200 {
compatible = "arm,cortex-a720ae";
reg = <0x0 0x40200>;
device_type = "cpu";
enable-method = "psci";
next-level-cache = <&L2_CA720_18>;
};
@ -276,6 +295,7 @@ a720_19: cpu@40300 {
compatible = "arm,cortex-a720ae";
reg = <0x0 0x40300>;
device_type = "cpu";
enable-method = "psci";
next-level-cache = <&L2_CA720_19>;
};
@ -283,6 +303,7 @@ a720_20: cpu@50000 {
compatible = "arm,cortex-a720ae";
reg = <0x0 0x50000>;
device_type = "cpu";
enable-method = "psci";
next-level-cache = <&L2_CA720_20>;
};
@ -290,6 +311,7 @@ a720_21: cpu@50100 {
compatible = "arm,cortex-a720ae";
reg = <0x0 0x50100>;
device_type = "cpu";
enable-method = "psci";
next-level-cache = <&L2_CA720_21>;
};
@ -297,6 +319,7 @@ a720_22: cpu@50200 {
compatible = "arm,cortex-a720ae";
reg = <0x0 0x50200>;
device_type = "cpu";
enable-method = "psci";
next-level-cache = <&L2_CA720_22>;
};
@ -304,6 +327,7 @@ a720_23: cpu@50300 {
compatible = "arm,cortex-a720ae";
reg = <0x0 0x50300>;
device_type = "cpu";
enable-method = "psci";
next-level-cache = <&L2_CA720_23>;
};
@ -311,6 +335,7 @@ a720_24: cpu@60000 {
compatible = "arm,cortex-a720ae";
reg = <0x0 0x60000>;
device_type = "cpu";
enable-method = "psci";
next-level-cache = <&L2_CA720_24>;
};
@ -318,6 +343,7 @@ a720_25: cpu@60100 {
compatible = "arm,cortex-a720ae";
reg = <0x0 0x60100>;
device_type = "cpu";
enable-method = "psci";
next-level-cache = <&L2_CA720_25>;
};
@ -325,6 +351,7 @@ a720_26: cpu@60200 {
compatible = "arm,cortex-a720ae";
reg = <0x0 0x60200>;
device_type = "cpu";
enable-method = "psci";
next-level-cache = <&L2_CA720_26>;
};
@ -332,6 +359,7 @@ a720_27: cpu@60300 {
compatible = "arm,cortex-a720ae";
reg = <0x0 0x60300>;
device_type = "cpu";
enable-method = "psci";
next-level-cache = <&L2_CA720_27>;
};
@ -339,6 +367,7 @@ a720_28: cpu@70000 {
compatible = "arm,cortex-a720ae";
reg = <0x0 0x70000>;
device_type = "cpu";
enable-method = "psci";
next-level-cache = <&L2_CA720_28>;
};
@ -346,6 +375,7 @@ a720_29: cpu@70100 {
compatible = "arm,cortex-a720ae";
reg = <0x0 0x70100>;
device_type = "cpu";
enable-method = "psci";
next-level-cache = <&L2_CA720_29>;
};
@ -353,6 +383,7 @@ a720_30: cpu@70200 {
compatible = "arm,cortex-a720ae";
reg = <0x0 0x70200>;
device_type = "cpu";
enable-method = "psci";
next-level-cache = <&L2_CA720_30>;
};
@ -360,6 +391,7 @@ a720_31: cpu@70300 {
compatible = "arm,cortex-a720ae";
reg = <0x0 0x70300>;
device_type = "cpu";
enable-method = "psci";
next-level-cache = <&L2_CA720_31>;
};