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arm64: dts: renesas: r8a779g0: Add L3 cache controller

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Describe the cache configuration for the first Cortex-A76 CPU core on
the Renesas R-Car V4H (R8A779G0) SoC.

Extracted from a larger patch in the BSP by Takeshi Kihara.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/dfd743b32198295afb78bc0ac337ef283fa3879a.1668429870.git.geert+renesas@glider.be
This commit is contained in:
Geert Uytterhoeven 2022-11-14 13:49:00 +01:00
parent c6b1737f45
commit f08407210d
1 changed files with 8 additions and 0 deletions
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arch/arm64/boot/dts/renesas/r8a779g0.dtsi
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@ -23,6 +23,14 @@ a76_0: cpu@0 {
reg = <0>;
device_type = "cpu";
power-domains = <&sysc R8A779G0_PD_A1E0D0C0>;
next-level-cache = <&L3_CA76_0>;
};
L3_CA76_0: cache-controller-0 {
compatible = "cache";
power-domains = <&sysc R8A779G0_PD_A2E0D0>;
cache-unified;
cache-level = <3>;
};
};