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arm64: dts: renesas: r9a09g011: Add L2 Cache node

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The Cortex-A53 processor on RZ/V2M has 512 KB L2 Cache.
Add L2 Cache node to SoC dtsi.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20221110160931.101539-1-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This commit is contained in:
Biju Das 2022-11-10 16:09:31 +00:00 committed by Geert Uytterhoeven
parent 594edf2c61
commit c6b1737f45
1 changed files with 7 additions and 0 deletions
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arch/arm64/boot/dts/renesas/r9a09g011.dtsi
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@ -37,8 +37,15 @@ cpu0: cpu@0 {
compatible = "arm,cortex-a53";
reg = <0>;
device_type = "cpu";
next-level-cache = <&L2_CA53>;
clocks = <&cpg CPG_MOD R9A09G011_CA53_CLK>;
};
L2_CA53: cache-controller-0 {
compatible = "cache";
cache-unified;
cache-level = <2>;
};
};
soc: soc {