github-mirror/linux
1
0
Fork 0
mirror of https://github.com/torvalds/linux.git synced 2026-06-02 03:24:19 +02:00
Code Issues Actions Packages Projects Releases Wiki Activity Graph

arm64: dts: renesas: r8a779g0: Add CPU core clocks

Browse Source 
Describe the clocks for the four Cortex-A76 CPU cores.
CA76 Sub-Systems 0/1 (both clusters / all CPU cores) are clocked by Z0φ.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/aa6e9ae21e451ebd40d54d986bd0296571128d5b.1668429870.git.geert+renesas@glider.be
This commit is contained in:
Geert Uytterhoeven 2022-11-14 13:49:03 +01:00
parent 5bb355a8d6
commit ee8ce199c7
1 changed files with 4 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
arch/arm64/boot/dts/renesas/r8a779g0.dtsi
View File

@ -46,6 +46,7 @@ a76_0: cpu@0 {
next-level-cache = <&L3_CA76_0>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0>;
clocks = <&cpg CPG_CORE R8A779G0_CLK_Z0>;
};
a76_1: cpu@100 {
@ -56,6 +57,7 @@ a76_1: cpu@100 {
next-level-cache = <&L3_CA76_0>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0>;
clocks = <&cpg CPG_CORE R8A779G0_CLK_Z0>;
};
a76_2: cpu@10000 {
@ -66,6 +68,7 @@ a76_2: cpu@10000 {
next-level-cache = <&L3_CA76_1>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0>;
clocks = <&cpg CPG_CORE R8A779G0_CLK_Z0>;
};
a76_3: cpu@10100 {
@ -76,6 +79,7 @@ a76_3: cpu@10100 {
next-level-cache = <&L3_CA76_1>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0>;
clocks = <&cpg CPG_CORE R8A779G0_CLK_Z0>;
};
idle-states {