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iio: adc: qcom-spmi-adc5-gen3: Increase HS_READY poll wait time to 15 ms

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Currently, before configuring ADC/ADC_TM, we poll for HS_READY
bit to be set which has a max poll wait time of 2 ms. As per the
recent hardware guidelines, increase this to 15 ms as HS_READY
won't be set within 2 ms in some circumstances.

Change-Id: I1cafa5052c80c2ef9512e794afd7e01eb39a53f4
Signed-off-by: Subbaraman Narayanamurthy <quic_subbaram@quicinc.com>
This commit is contained in:
Subbaraman Narayanamurthy 2022-08-08 19:47:46 -07:00 committed by Anjelique Melendez
parent 6d4fecae07
commit ec6dcfacd3
1 changed files with 1 additions and 1 deletions
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2
drivers/iio/adc/qcom-spmi-adc5-gen3.c
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@ -400,7 +400,7 @@ static int adc5_gen3_configure(struct adc5_chip *adc,
#define ADC5_GEN3_HS_DELAY_MIN_US 100
#define ADC5_GEN3_HS_DELAY_MAX_US 110
#define ADC5_GEN3_HS_RETRY_COUNT 20
#define ADC5_GEN3_HS_RETRY_COUNT 150
static int adc5_gen3_poll_wait_hs(struct adc5_chip *adc, struct adc5_channel_prop *prop)
{