From ec6dcfacd3d596086c49b4c9f23958fcdaf1713a Mon Sep 17 00:00:00 2001 From: Subbaraman Narayanamurthy Date: Mon, 8 Aug 2022 19:47:46 -0700 Subject: [PATCH] iio: adc: qcom-spmi-adc5-gen3: Increase HS_READY poll wait time to 15 ms Currently, before configuring ADC/ADC_TM, we poll for HS_READY bit to be set which has a max poll wait time of 2 ms. As per the recent hardware guidelines, increase this to 15 ms as HS_READY won't be set within 2 ms in some circumstances. Change-Id: I1cafa5052c80c2ef9512e794afd7e01eb39a53f4 Signed-off-by: Subbaraman Narayanamurthy --- drivers/iio/adc/qcom-spmi-adc5-gen3.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/iio/adc/qcom-spmi-adc5-gen3.c b/drivers/iio/adc/qcom-spmi-adc5-gen3.c index b0c13efc0797..5560625e462d 100644 --- a/drivers/iio/adc/qcom-spmi-adc5-gen3.c +++ b/drivers/iio/adc/qcom-spmi-adc5-gen3.c @@ -400,7 +400,7 @@ static int adc5_gen3_configure(struct adc5_chip *adc, #define ADC5_GEN3_HS_DELAY_MIN_US 100 #define ADC5_GEN3_HS_DELAY_MAX_US 110 -#define ADC5_GEN3_HS_RETRY_COUNT 20 +#define ADC5_GEN3_HS_RETRY_COUNT 150 static int adc5_gen3_poll_wait_hs(struct adc5_chip *adc, struct adc5_channel_prop *prop) {