mirror of
https://github.com/torvalds/linux.git
synced 2026-05-23 06:31:58 +02:00
Samsung SoC driver changes for v6.8
1. Add support for Google GS101 SoC to different drivers: clock
controller, serial and watchdog.
The clock driver changes depend on few bindings headers, which I put
in a topic branch with the bindings refactoring and GS101 support,
therefore this this pull request includes that bindings topic branch.
The rest of the bindings topic branch is not necessary here, however
keeping everything together makes it easier to share between
branches. The bindings topic branch is mostly refactoring all the
compatibles to add SoC-specific compatible followed by fallback.
2. Exynos ChipID: recognize ExynosAutov920.
-----BEGIN PGP SIGNATURE-----
iQJEBAABCgAuFiEE3dJiKD0RGyM7briowTdm5oaLg9cFAmWCp0MQHGtyemtAa2Vy
bmVsLm9yZwAKCRDBN2bmhouD13d5D/9jRfyTX36FvmGsRaHZieXFT2TzhLKtnpsP
7xdP34HLWjY5ig4Gd4gWwaS3skLxlMa1Ilc8177vHaDSbWGnqFmWJgO600Yr66BR
zBc0RKiujMTpBIEseOAltzAkKfp2TJ4LGFEokqB/LAU1SqE7tiPR9PzeKMi0yqLg
7bio5yRSSp0PpoX60vYHR5whcJV6uJUMC8IGdT9arslW/9UNndi+KtFcbdxqiuWS
VOXHHpPjcedY1TliaeHxKVUhQe+J1Vsfr5QCYYgkJY5KuH4cGx9DVPdAJ6zSn6Ti
qBMu4x6xKI+317i2bY6vFy2+kzAQCsYG0L3RV94zrWlkuDx04CHbsHKkchhQbfOV
23Kge0qcIgO09r+EEj2MyUtXfYAJl4RDVGMOALdGAn2Kd4iSprfAJ9icxcmrOufe
0x4RWjoo9xlLG5cszgSbqOE55o8GfDS6XZOI0X+aBURpj9wg8EEJpUiSVz9JBR4M
smsBU/nLGenhuPx62L30YZZRc081Ut59Gpd3u4/VQjHgsvVowsgEai7D/a4cNBr5
aYpKBQE4qJyqFLOCvIVnhIaEKOvDAMqLi3+nh9b6Fn5cIkZxAIgObaXy8fmcmYJu
VmVNGwLyYoDVEBvPIBLL4asRC6l7xmqiO8uDhvF+wFVKtJyGv0eD7fAgEvIh/M6x
UokSkwMH+A==
=65h3
-----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEiK/NIGsWEZVxh/FrYKtH/8kJUicFAmWFcLgACgkQYKtH/8kJ
Uid6RQ/6A+RY+lxqaPAs8g4q/yDWvJpuAgeGEFhO9ZYtCZx1NCPKuQQ77KHmZP0Q
+p95CNmuyPYWEPdr0c+qS6Mvd6UlotarXl0T+TyH7DjQwnNf42sjHvB0bS3/llck
SZn0azWo1ms2G1SdvGY9A/l8Efj5NzdYLx8IomlDtorxaAibXZk62i0+RxJVpni5
0e6C4f/tUee8INk6teNg74aUmZNesHthj8lmuVO8pJoExwBG4HLxBaDi/gDFqhn1
qnILr3a3J2I7y2xYD9TllbfYaZl4bufmiWyQpD2Mis92us6BiSGjJ2HuBfQf10IC
0ywd1mjPxQxYBN3Lvpg2htW5+6U31V7cLXneLeH75uE+G4uQkd5asegKPIx1E15m
eHn0psifzNejRy0e9E/136Gh4PY0xBXD5YpS0xdVq+8Dd9gjiawq0Sg4/C3TOqV6
Fc2eArnesXqWs8AqWaY948MZyqnEAR2FFJtpAaRBs3vw8zkW8NnlXesBoC7f0sO3
maLNA7druharcCSF1PPOPOMMgqtXNxXuczgD5NqLr2BB/Jp+Y63y/Yh6iaeBmDWQ
ocs9PDFvITknXDYYDHzBYjUd3q7kR35XHNHMNb0U1/de9q9mNR5AuPmLj9xEjqpC
VGtBl+aZ37PCV1TTF+GhqPs0b461mTMRgP6ypDbG3SxOnokio5w=
=UEZb
-----END PGP SIGNATURE-----
Merge tag 'samsung-drivers-6.8' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into soc/drivers
Samsung SoC driver changes for v6.8
1. Add support for Google GS101 SoC to different drivers: clock
controller, serial and watchdog.
The clock driver changes depend on few bindings headers, which I put
in a topic branch with the bindings refactoring and GS101 support,
therefore this this pull request includes that bindings topic branch.
The rest of the bindings topic branch is not necessary here, however
keeping everything together makes it easier to share between
branches. The bindings topic branch is mostly refactoring all the
compatibles to add SoC-specific compatible followed by fallback.
2. Exynos ChipID: recognize ExynosAutov920.
* tag 'samsung-drivers-6.8' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux: (40 commits)
dt-bindings: clock: google,gs101: rename CMU_TOP gate defines
watchdog: s3c2410_wdt: Add support for Google gs101 SoC
watchdog: s3c2410_wdt: Update QUIRK macros to use BIT macro
watchdog: s3c2410_wdt: Add support for WTCON register DBGACK_MASK bit
tty: serial: samsung: Add gs101 compatible and common fifoszdt_serial_drv_data
clk: samsung: clk-gs101: Add cmu_top, cmu_misc and cmu_apm support
clk: samsung: clk-pll: Add support for pll_{0516,0517,518}
dt-bindings: clock: google,gs101: fix incorrect numbering and DGB suffix
dt-bindings: soc: samsung: usi: add google,gs101-usi compatible
dt-bindings: serial: samsung: Make samsung,uart-fifosize a required property
dt-bindings: serial: samsung: Add google-gs101-uart compatible
dt-bindings: watchdog: Document Google gs101 watchdog bindings
dt-bindings: samsung: exynos-sysreg: combine exynosautov920 with other enum
dt-bindings: soc: google: exynos-sysreg: add dedicated SYSREG compatibles to GS101
dt-bindings: clock: Add Google gs101 clock management unit bindings
dt-bindings: soc: samsung: exynos-pmu: Add gs101 compatible
dt-bindings: watchdog: samsung: add specific compatible for Tesla FSD
dt-bindings: samsung: exynos-pmu: add specific compatible for Tesla FSD
dt-bindings: serial: samsung: add specific compatible for Tesla FSD
dt-bindings: pwm: samsung: add specific compatible for Tesla FSD
...
Link: https://lore.kernel.org/r/20231220084722.22149-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
commit
ec5b7be617
|
|
@ -230,6 +230,12 @@ properties:
|
|||
- samsung,exynosautov9-sadk # Samsung Exynos Auto v9 SADK
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||||
- const: samsung,exynosautov9
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||||
|
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- description: Exynos Auto v920 based boards
|
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items:
|
||||
- enum:
|
||||
- samsung,exynosautov920-sadk # Samsung Exynos Auto v920 SADK
|
||||
- const: samsung,exynosautov920
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||||
|
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required:
|
||||
- compatible
|
||||
|
||||
|
|
|
|||
106
Documentation/devicetree/bindings/clock/google,gs101-clock.yaml
Normal file
106
Documentation/devicetree/bindings/clock/google,gs101-clock.yaml
Normal file
|
|
@ -0,0 +1,106 @@
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|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/google,gs101-clock.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Google GS101 SoC clock controller
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maintainers:
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- Peter Griffin <peter.griffin@linaro.org>
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description: |
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Google GS101 clock controller is comprised of several CMU units, generating
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clocks for different domains. Those CMU units are modeled as separate device
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tree nodes, and might depend on each other. The root clock in that clock tree
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is OSCCLK (24.576 MHz). That external clock must be defined as a fixed-rate
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clock in dts.
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CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and
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dividers; all other leaf clocks (other CMUs) are usually derived from CMU_TOP.
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|
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Each clock is assigned an identifier and client nodes can use this identifier
|
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to specify the clock which they consume. All clocks available for usage
|
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in clock consumer nodes are defined as preprocessor macros in
|
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'dt-bindings/clock/gs101.h' header.
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|
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properties:
|
||||
compatible:
|
||||
enum:
|
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- google,gs101-cmu-top
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- google,gs101-cmu-apm
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- google,gs101-cmu-misc
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|
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clocks:
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minItems: 1
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maxItems: 2
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|
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clock-names:
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minItems: 1
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maxItems: 2
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||||
|
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"#clock-cells":
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const: 1
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|
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reg:
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maxItems: 1
|
||||
|
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required:
|
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- compatible
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- "#clock-cells"
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- clocks
|
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- clock-names
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- reg
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|
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allOf:
|
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- if:
|
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properties:
|
||||
compatible:
|
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contains:
|
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enum:
|
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- google,gs101-cmu-top
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- google,gs101-cmu-apm
|
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then:
|
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properties:
|
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clocks:
|
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items:
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- description: External reference clock (24.576 MHz)
|
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clock-names:
|
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items:
|
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- const: oscclk
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|
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- if:
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properties:
|
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compatible:
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contains:
|
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const: google,gs101-cmu-misc
|
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|
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then:
|
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properties:
|
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clocks:
|
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items:
|
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- description: Misc bus clock (from CMU_TOP)
|
||||
- description: Misc sss clock (from CMU_TOP)
|
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|
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clock-names:
|
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items:
|
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- const: dout_cmu_misc_bus
|
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- const: dout_cmu_misc_sss
|
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|
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additionalProperties: false
|
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|
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examples:
|
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# Clock controller node for CMU_TOP
|
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- |
|
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#include <dt-bindings/clock/google,gs101.h>
|
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cmu_top: clock-controller@1e080000 {
|
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compatible = "google,gs101-cmu-top";
|
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reg = <0x1e080000 0x8000>;
|
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#clock-cells = <1>;
|
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clocks = <&ext_24_5m>;
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clock-names = "oscclk";
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};
|
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|
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...
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|
|
@ -40,6 +40,11 @@ properties:
|
|||
- rockchip,rk3288-mali
|
||||
- samsung,exynos5433-mali
|
||||
- const: arm,mali-t760
|
||||
- items:
|
||||
- enum:
|
||||
- samsung,exynos7-mali
|
||||
- const: samsung,exynos5433-mali
|
||||
- const: arm,mali-t760
|
||||
- items:
|
||||
- enum:
|
||||
- rockchip,rk3399-mali
|
||||
|
|
|
|||
|
|
@ -11,9 +11,21 @@ maintainers:
|
|||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- samsung,exynos4210-chipid
|
||||
- samsung,exynos850-chipid
|
||||
oneOf:
|
||||
- enum:
|
||||
- samsung,exynos4210-chipid
|
||||
- samsung,exynos850-chipid
|
||||
- items:
|
||||
- enum:
|
||||
- samsung,exynos5433-chipid
|
||||
- samsung,exynos7-chipid
|
||||
- const: samsung,exynos4210-chipid
|
||||
- items:
|
||||
- enum:
|
||||
- samsung,exynos7885-chipid
|
||||
- samsung,exynosautov9-chipid
|
||||
- samsung,exynosautov920-chipid
|
||||
- const: samsung,exynos850-chipid
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
|
|
|||
|
|
@ -25,7 +25,16 @@ properties:
|
|||
- samsung,exynos5250-hsi2c # Exynos5250 and Exynos5420
|
||||
- samsung,exynos5260-hsi2c # Exynos5260
|
||||
- samsung,exynos7-hsi2c # Exynos7
|
||||
- samsung,exynosautov9-hsi2c # ExynosAutoV9 and Exynos850
|
||||
- samsung,exynosautov9-hsi2c
|
||||
- items:
|
||||
- enum:
|
||||
- samsung,exynos5433-hsi2c
|
||||
- tesla,fsd-hsi2c
|
||||
- const: samsung,exynos7-hsi2c
|
||||
- items:
|
||||
- enum:
|
||||
- samsung,exynos850-hsi2c
|
||||
- const: samsung,exynosautov9-hsi2c
|
||||
- const: samsung,exynos5-hsi2c # Exynos5250 and Exynos5420
|
||||
deprecated: true
|
||||
|
||||
|
|
|
|||
|
|
@ -11,14 +11,20 @@ maintainers:
|
|||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- samsung,s3c2410-i2c
|
||||
- samsung,s3c2440-i2c
|
||||
# For s3c2440-like I2C used inside HDMIPHY block found on several SoCs:
|
||||
- samsung,s3c2440-hdmiphy-i2c
|
||||
# For s3c2440-like I2C used as a host to SATA PHY controller on an
|
||||
# internal bus:
|
||||
- samsung,exynos5-sata-phy-i2c
|
||||
oneOf:
|
||||
- enum:
|
||||
- samsung,s3c2410-i2c
|
||||
- samsung,s3c2440-i2c
|
||||
# For s3c2440-like I2C used inside HDMIPHY block found on several SoCs:
|
||||
- samsung,s3c2440-hdmiphy-i2c
|
||||
# For s3c2440-like I2C used as a host to SATA PHY controller on an
|
||||
# internal bus:
|
||||
- samsung,exynos5-sata-phy-i2c
|
||||
- items:
|
||||
- enum:
|
||||
- samsung,exynos7885-i2c
|
||||
- samsung,exynos850-i2c
|
||||
- const: samsung,s3c2440-i2c
|
||||
|
||||
'#address-cells':
|
||||
const: 1
|
||||
|
|
|
|||
|
|
@ -11,18 +11,23 @@ maintainers:
|
|||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- samsung,exynos-adc-v1 # Exynos5250
|
||||
- samsung,exynos-adc-v2
|
||||
- samsung,exynos3250-adc
|
||||
- samsung,exynos4212-adc # Exynos4212 and Exynos4412
|
||||
- samsung,exynos7-adc
|
||||
- samsung,s3c2410-adc
|
||||
- samsung,s3c2416-adc
|
||||
- samsung,s3c2440-adc
|
||||
- samsung,s3c2443-adc
|
||||
- samsung,s3c6410-adc
|
||||
- samsung,s5pv210-adc
|
||||
oneOf:
|
||||
- enum:
|
||||
- samsung,exynos-adc-v1 # Exynos5250
|
||||
- samsung,exynos-adc-v2
|
||||
- samsung,exynos3250-adc
|
||||
- samsung,exynos4212-adc # Exynos4212 and Exynos4412
|
||||
- samsung,exynos7-adc
|
||||
- samsung,s3c2410-adc
|
||||
- samsung,s3c2416-adc
|
||||
- samsung,s3c2440-adc
|
||||
- samsung,s3c2443-adc
|
||||
- samsung,s3c6410-adc
|
||||
- samsung,s5pv210-adc
|
||||
- items:
|
||||
- enum:
|
||||
- samsung,exynos5433-adc
|
||||
- const: samsung,exynos7-adc
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
|
|
|||
|
|
@ -85,7 +85,7 @@ examples:
|
|||
};
|
||||
|
||||
i2s@11440000 {
|
||||
compatible = "samsung,exynos7-i2s";
|
||||
compatible = "samsung,exynos5433-i2s", "samsung,exynos7-i2s";
|
||||
reg = <0x11440000 0x100>;
|
||||
dmas = <&adma 0>, <&adma 2>;
|
||||
dma-names = "tx", "rx";
|
||||
|
|
|
|||
|
|
@ -14,15 +14,22 @@ maintainers:
|
|||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- samsung,exynos4210-dw-mshc
|
||||
- samsung,exynos4412-dw-mshc
|
||||
- samsung,exynos5250-dw-mshc
|
||||
- samsung,exynos5420-dw-mshc
|
||||
- samsung,exynos5420-dw-mshc-smu
|
||||
- samsung,exynos7-dw-mshc
|
||||
- samsung,exynos7-dw-mshc-smu
|
||||
- axis,artpec8-dw-mshc
|
||||
oneOf:
|
||||
- enum:
|
||||
- axis,artpec8-dw-mshc
|
||||
- samsung,exynos4210-dw-mshc
|
||||
- samsung,exynos4412-dw-mshc
|
||||
- samsung,exynos5250-dw-mshc
|
||||
- samsung,exynos5420-dw-mshc
|
||||
- samsung,exynos5420-dw-mshc-smu
|
||||
- samsung,exynos7-dw-mshc
|
||||
- samsung,exynos7-dw-mshc-smu
|
||||
- items:
|
||||
- enum:
|
||||
- samsung,exynos5433-dw-mshc-smu
|
||||
- samsung,exynos7885-dw-mshc-smu
|
||||
- samsung,exynos850-dw-mshc-smu
|
||||
- const: samsung,exynos7-dw-mshc-smu
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
|
|
|||
|
|
@ -29,7 +29,11 @@ properties:
|
|||
- samsung,exynos4210-pwm # 32-bit, Exynos
|
||||
- items:
|
||||
- enum:
|
||||
- samsung,exynos5433-pwm
|
||||
- samsung,exynos7-pwm
|
||||
- samsung,exynosautov9-pwm
|
||||
- samsung,exynosautov920-pwm
|
||||
- tesla,fsd-pwm
|
||||
- const: samsung,exynos4210-pwm
|
||||
|
||||
reg:
|
||||
|
|
|
|||
|
|
@ -17,6 +17,11 @@ properties:
|
|||
- samsung,s3c2416-rtc
|
||||
- samsung,s3c2443-rtc
|
||||
- samsung,s3c6410-rtc
|
||||
- items:
|
||||
- enum:
|
||||
- samsung,exynos7-rtc
|
||||
- samsung,exynos850-rtc
|
||||
- const: samsung,s3c6410-rtc
|
||||
- const: samsung,exynos3250-rtc
|
||||
deprecated: true
|
||||
|
||||
|
|
|
|||
|
|
@ -18,17 +18,29 @@ description: |+
|
|||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- items:
|
||||
- const: samsung,exynosautov9-uart
|
||||
- const: samsung,exynos850-uart
|
||||
- enum:
|
||||
- apple,s5l-uart
|
||||
- axis,artpec8-uart
|
||||
- google,gs101-uart
|
||||
- samsung,s3c6400-uart
|
||||
- samsung,s5pv210-uart
|
||||
- samsung,exynos4210-uart
|
||||
- samsung,exynos5433-uart
|
||||
- samsung,exynos850-uart
|
||||
- items:
|
||||
- enum:
|
||||
- samsung,exynos7-uart
|
||||
- tesla,fsd-uart
|
||||
- const: samsung,exynos4210-uart
|
||||
- items:
|
||||
- enum:
|
||||
- samsung,exynos7885-uart
|
||||
- const: samsung,exynos5433-uart
|
||||
- items:
|
||||
- enum:
|
||||
- samsung,exynosautov9-uart
|
||||
- samsung,exynosautov920-uart
|
||||
- const: samsung,exynos850-uart
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
|
@ -122,6 +134,16 @@ allOf:
|
|||
- const: uart
|
||||
- const: clk_uart_baud0
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- google,gs101-uart
|
||||
then:
|
||||
required:
|
||||
- samsung,uart-fifosize
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
|
|
|
|||
|
|
@ -15,6 +15,7 @@ select:
|
|||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- google,gs101-pmu
|
||||
- samsung,exynos3250-pmu
|
||||
- samsung,exynos4210-pmu
|
||||
- samsung,exynos4212-pmu
|
||||
|
|
@ -35,6 +36,7 @@ properties:
|
|||
oneOf:
|
||||
- items:
|
||||
- enum:
|
||||
- google,gs101-pmu
|
||||
- samsung,exynos3250-pmu
|
||||
- samsung,exynos4210-pmu
|
||||
- samsung,exynos4212-pmu
|
||||
|
|
@ -48,6 +50,14 @@ properties:
|
|||
- samsung,exynos850-pmu
|
||||
- samsung-s5pv210-pmu
|
||||
- const: syscon
|
||||
- items:
|
||||
- enum:
|
||||
- samsung,exynos7885-pmu
|
||||
- samsung,exynosautov9-pmu
|
||||
- samsung,exynosautov920-pmu
|
||||
- tesla,fsd-pmu
|
||||
- const: samsung,exynos7-pmu
|
||||
- const: syscon
|
||||
- items:
|
||||
- enum:
|
||||
- samsung,exynos3250-pmu
|
||||
|
|
|
|||
|
|
@ -24,7 +24,10 @@ properties:
|
|||
compatible:
|
||||
oneOf:
|
||||
- items:
|
||||
- const: samsung,exynosautov9-usi
|
||||
- enum:
|
||||
- google,gs101-usi
|
||||
- samsung,exynosautov9-usi
|
||||
- samsung,exynosautov920-usi
|
||||
- const: samsung,exynos850-usi
|
||||
- enum:
|
||||
- samsung,exynos850-usi
|
||||
|
|
@ -155,7 +158,7 @@ examples:
|
|||
};
|
||||
|
||||
hsi2c_0: i2c@13820000 {
|
||||
compatible = "samsung,exynosautov9-hsi2c";
|
||||
compatible = "samsung,exynos850-hsi2c", "samsung,exynosautov9-hsi2c";
|
||||
reg = <0x13820000 0xc0>;
|
||||
interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
|
|
|
|||
|
|
@ -14,9 +14,14 @@ properties:
|
|||
oneOf:
|
||||
- items:
|
||||
- enum:
|
||||
- google,gs101-apm-sysreg
|
||||
- google,gs101-peric0-sysreg
|
||||
- google,gs101-peric1-sysreg
|
||||
- samsung,exynos3-sysreg
|
||||
- samsung,exynos4-sysreg
|
||||
- samsung,exynos5-sysreg
|
||||
- samsung,exynosautov920-peric0-sysreg
|
||||
- samsung,exynosautov920-peric1-sysreg
|
||||
- tesla,fsd-cam-sysreg
|
||||
- tesla,fsd-fsys0-sysreg
|
||||
- tesla,fsd-fsys1-sysreg
|
||||
|
|
|
|||
|
|
@ -44,13 +44,18 @@ properties:
|
|||
frequencies supported by Exynos7 I2S and 7.1 channel TDM support
|
||||
for playback and capture TDM (Time division multiplexing) to allow
|
||||
transfer of multiple channel audio data on single data line.
|
||||
enum:
|
||||
- samsung,s3c6410-i2s
|
||||
- samsung,s5pv210-i2s
|
||||
- samsung,exynos5420-i2s
|
||||
- samsung,exynos7-i2s
|
||||
- samsung,exynos7-i2s1
|
||||
- tesla,fsd-i2s
|
||||
oneOf:
|
||||
- enum:
|
||||
- samsung,s3c6410-i2s
|
||||
- samsung,s5pv210-i2s
|
||||
- samsung,exynos5420-i2s
|
||||
- samsung,exynos7-i2s
|
||||
- samsung,exynos7-i2s1
|
||||
- tesla,fsd-i2s
|
||||
- items:
|
||||
- enum:
|
||||
- samsung,exynos5433-i2s
|
||||
- const: samsung,exynos7-i2s
|
||||
|
||||
'#address-cells':
|
||||
const: 1
|
||||
|
|
|
|||
|
|
@ -16,14 +16,20 @@ description: |+
|
|||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- samsung,s3c2410-wdt # for S3C2410
|
||||
- samsung,s3c6410-wdt # for S3C6410, S5PV210 and Exynos4
|
||||
- samsung,exynos5250-wdt # for Exynos5250
|
||||
- samsung,exynos5420-wdt # for Exynos5420
|
||||
- samsung,exynos7-wdt # for Exynos7
|
||||
- samsung,exynos850-wdt # for Exynos850
|
||||
- samsung,exynosautov9-wdt # for Exynosautov9
|
||||
oneOf:
|
||||
- enum:
|
||||
- google,gs101-wdt # for Google gs101
|
||||
- samsung,s3c2410-wdt # for S3C2410
|
||||
- samsung,s3c6410-wdt # for S3C6410, S5PV210 and Exynos4
|
||||
- samsung,exynos5250-wdt # for Exynos5250
|
||||
- samsung,exynos5420-wdt # for Exynos5420
|
||||
- samsung,exynos7-wdt # for Exynos7
|
||||
- samsung,exynos850-wdt # for Exynos850
|
||||
- samsung,exynosautov9-wdt # for Exynosautov9
|
||||
- items:
|
||||
- enum:
|
||||
- tesla,fsd-wdt
|
||||
- const: samsung,exynos7-wdt
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
|
@ -42,13 +48,14 @@ properties:
|
|||
samsung,cluster-index:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description:
|
||||
Index of CPU cluster on which watchdog is running (in case of Exynos850)
|
||||
Index of CPU cluster on which watchdog is running (in case of Exynos850
|
||||
or Google gs101).
|
||||
|
||||
samsung,syscon-phandle:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
description:
|
||||
Phandle to the PMU system controller node (in case of Exynos5250,
|
||||
Exynos5420, Exynos7 and Exynos850).
|
||||
Exynos5420, Exynos7, Exynos850 and gs101).
|
||||
|
||||
required:
|
||||
- compatible
|
||||
|
|
@ -64,6 +71,7 @@ allOf:
|
|||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- google,gs101-wdt
|
||||
- samsung,exynos5250-wdt
|
||||
- samsung,exynos5420-wdt
|
||||
- samsung,exynos7-wdt
|
||||
|
|
@ -77,6 +85,7 @@ allOf:
|
|||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- google,gs101-wdt
|
||||
- samsung,exynos850-wdt
|
||||
- samsung,exynosautov9-wdt
|
||||
then:
|
||||
|
|
|
|||
|
|
@ -21,6 +21,7 @@ obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos7.o
|
|||
obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos7885.o
|
||||
obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos850.o
|
||||
obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynosautov9.o
|
||||
obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-gs101.o
|
||||
obj-$(CONFIG_S3C64XX_COMMON_CLK) += clk-s3c64xx.o
|
||||
obj-$(CONFIG_S5PV210_COMMON_CLK) += clk-s5pv210.o clk-s5pv210-audss.o
|
||||
obj-$(CONFIG_TESLA_FSD_COMMON_CLK) += clk-fsd.o
|
||||
|
|
|
|||
2518
drivers/clk/samsung/clk-gs101.c
Normal file
2518
drivers/clk/samsung/clk-gs101.c
Normal file
File diff suppressed because it is too large
Load Diff
|
|
@ -443,6 +443,9 @@ static unsigned long samsung_pll0822x_recalc_rate(struct clk_hw *hw,
|
|||
sdiv = (pll_con3 >> PLL0822X_SDIV_SHIFT) & PLL0822X_SDIV_MASK;
|
||||
|
||||
fvco *= mdiv;
|
||||
if (pll->type == pll_0516x)
|
||||
fvco *= 2;
|
||||
|
||||
do_div(fvco, (pdiv << sdiv));
|
||||
|
||||
return (unsigned long)fvco;
|
||||
|
|
@ -1316,6 +1319,9 @@ static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx,
|
|||
case pll_1417x:
|
||||
case pll_0818x:
|
||||
case pll_0822x:
|
||||
case pll_0516x:
|
||||
case pll_0517x:
|
||||
case pll_0518x:
|
||||
pll->enable_offs = PLL0822X_ENABLE_SHIFT;
|
||||
pll->lock_offs = PLL0822X_LOCK_STAT_SHIFT;
|
||||
if (!pll->rate_table)
|
||||
|
|
|
|||
|
|
@ -38,6 +38,9 @@ enum samsung_pll_type {
|
|||
pll_0822x,
|
||||
pll_0831x,
|
||||
pll_142xx,
|
||||
pll_0516x,
|
||||
pll_0517x,
|
||||
pll_0518x,
|
||||
};
|
||||
|
||||
#define PLL_RATE(_fin, _m, _p, _s, _k, _ks) \
|
||||
|
|
|
|||
|
|
@ -59,6 +59,7 @@ static const struct exynos_soc_id {
|
|||
{ "EXYNOS7885", 0xE7885000 },
|
||||
{ "EXYNOS850", 0xE3830000 },
|
||||
{ "EXYNOSAUTOV9", 0xAAA80000 },
|
||||
{ "EXYNOSAUTOV920", 0x0A920000 },
|
||||
};
|
||||
|
||||
static const char *product_id_to_soc_id(unsigned int product_id)
|
||||
|
|
|
|||
|
|
@ -2492,14 +2492,25 @@ static const struct s3c24xx_serial_drv_data exynos850_serial_drv_data = {
|
|||
.fifosize = { 256, 64, 64, 64 },
|
||||
};
|
||||
|
||||
/*
|
||||
* Common drv_data struct for platforms that specify samsung,uart-fifosize in
|
||||
* device tree.
|
||||
*/
|
||||
static const struct s3c24xx_serial_drv_data exynos_fifoszdt_serial_drv_data = {
|
||||
EXYNOS_COMMON_SERIAL_DRV_DATA(),
|
||||
.fifosize = { 0 },
|
||||
};
|
||||
|
||||
#define EXYNOS4210_SERIAL_DRV_DATA (&exynos4210_serial_drv_data)
|
||||
#define EXYNOS5433_SERIAL_DRV_DATA (&exynos5433_serial_drv_data)
|
||||
#define EXYNOS850_SERIAL_DRV_DATA (&exynos850_serial_drv_data)
|
||||
#define EXYNOS_FIFOSZDT_DRV_DATA (&exynos_fifoszdt_serial_drv_data)
|
||||
|
||||
#else
|
||||
#define EXYNOS4210_SERIAL_DRV_DATA NULL
|
||||
#define EXYNOS5433_SERIAL_DRV_DATA NULL
|
||||
#define EXYNOS850_SERIAL_DRV_DATA NULL
|
||||
#define EXYNOS_FIFOSZDT_DRV_DATA NULL
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ARCH_APPLE
|
||||
|
|
@ -2583,6 +2594,9 @@ static const struct platform_device_id s3c24xx_serial_driver_ids[] = {
|
|||
}, {
|
||||
.name = "artpec8-uart",
|
||||
.driver_data = (kernel_ulong_t)ARTPEC8_SERIAL_DRV_DATA,
|
||||
}, {
|
||||
.name = "gs101-uart",
|
||||
.driver_data = (kernel_ulong_t)EXYNOS_FIFOSZDT_DRV_DATA,
|
||||
},
|
||||
{ },
|
||||
};
|
||||
|
|
@ -2604,6 +2618,8 @@ static const struct of_device_id s3c24xx_uart_dt_match[] = {
|
|||
.data = EXYNOS850_SERIAL_DRV_DATA },
|
||||
{ .compatible = "axis,artpec8-uart",
|
||||
.data = ARTPEC8_SERIAL_DRV_DATA },
|
||||
{ .compatible = "google,gs101-uart",
|
||||
.data = EXYNOS_FIFOSZDT_DRV_DATA },
|
||||
{},
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, s3c24xx_uart_dt_match);
|
||||
|
|
|
|||
|
|
@ -9,6 +9,7 @@
|
|||
* (c) Copyright 1996 Alan Cox <alan@lxorguk.ukuu.org.uk>
|
||||
*/
|
||||
|
||||
#include <linux/bits.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/moduleparam.h>
|
||||
#include <linux/types.h>
|
||||
|
|
@ -34,9 +35,10 @@
|
|||
|
||||
#define S3C2410_WTCNT_MAXCNT 0xffff
|
||||
|
||||
#define S3C2410_WTCON_RSTEN (1 << 0)
|
||||
#define S3C2410_WTCON_INTEN (1 << 2)
|
||||
#define S3C2410_WTCON_ENABLE (1 << 5)
|
||||
#define S3C2410_WTCON_RSTEN BIT(0)
|
||||
#define S3C2410_WTCON_INTEN BIT(2)
|
||||
#define S3C2410_WTCON_ENABLE BIT(5)
|
||||
#define S3C2410_WTCON_DBGACK_MASK BIT(16)
|
||||
|
||||
#define S3C2410_WTCON_DIV16 (0 << 3)
|
||||
#define S3C2410_WTCON_DIV32 (1 << 3)
|
||||
|
|
@ -67,6 +69,13 @@
|
|||
#define EXYNOSAUTOV9_CLUSTER0_WDTRESET_BIT 25
|
||||
#define EXYNOSAUTOV9_CLUSTER1_WDTRESET_BIT 24
|
||||
|
||||
#define GS_CLUSTER0_NONCPU_OUT 0x1220
|
||||
#define GS_CLUSTER1_NONCPU_OUT 0x1420
|
||||
#define GS_CLUSTER0_NONCPU_INT_EN 0x1244
|
||||
#define GS_CLUSTER1_NONCPU_INT_EN 0x1444
|
||||
#define GS_CLUSTER2_NONCPU_INT_EN 0x1644
|
||||
#define GS_RST_STAT_REG_OFFSET 0x3B44
|
||||
|
||||
/**
|
||||
* DOC: Quirk flags for different Samsung watchdog IP-cores
|
||||
*
|
||||
|
|
@ -100,12 +109,17 @@
|
|||
* %QUIRK_HAS_PMU_CNT_EN: PMU block has some register (e.g. CLUSTERx_NONCPU_OUT)
|
||||
* with "watchdog counter enable" bit. That bit should be set to make watchdog
|
||||
* counter running.
|
||||
*
|
||||
* %QUIRK_HAS_DBGACK_BIT: WTCON register has DBGACK_MASK bit. Setting the
|
||||
* DBGACK_MASK bit disables the watchdog outputs when the SoC is in debug mode.
|
||||
* Debug mode is determined by the DBGACK CPU signal.
|
||||
*/
|
||||
#define QUIRK_HAS_WTCLRINT_REG (1 << 0)
|
||||
#define QUIRK_HAS_PMU_MASK_RESET (1 << 1)
|
||||
#define QUIRK_HAS_PMU_RST_STAT (1 << 2)
|
||||
#define QUIRK_HAS_PMU_AUTO_DISABLE (1 << 3)
|
||||
#define QUIRK_HAS_PMU_CNT_EN (1 << 4)
|
||||
#define QUIRK_HAS_WTCLRINT_REG BIT(0)
|
||||
#define QUIRK_HAS_PMU_MASK_RESET BIT(1)
|
||||
#define QUIRK_HAS_PMU_RST_STAT BIT(2)
|
||||
#define QUIRK_HAS_PMU_AUTO_DISABLE BIT(3)
|
||||
#define QUIRK_HAS_PMU_CNT_EN BIT(4)
|
||||
#define QUIRK_HAS_DBGACK_BIT BIT(5)
|
||||
|
||||
/* These quirks require that we have a PMU register map */
|
||||
#define QUIRKS_HAVE_PMUREG \
|
||||
|
|
@ -263,7 +277,35 @@ static const struct s3c2410_wdt_variant drv_data_exynosautov9_cl1 = {
|
|||
QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_CNT_EN,
|
||||
};
|
||||
|
||||
static const struct s3c2410_wdt_variant drv_data_gs101_cl0 = {
|
||||
.mask_reset_reg = GS_CLUSTER0_NONCPU_INT_EN,
|
||||
.mask_bit = 2,
|
||||
.mask_reset_inv = true,
|
||||
.rst_stat_reg = GS_RST_STAT_REG_OFFSET,
|
||||
.rst_stat_bit = 0,
|
||||
.cnt_en_reg = GS_CLUSTER0_NONCPU_OUT,
|
||||
.cnt_en_bit = 8,
|
||||
.quirks = QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_MASK_RESET |
|
||||
QUIRK_HAS_PMU_CNT_EN | QUIRK_HAS_WTCLRINT_REG |
|
||||
QUIRK_HAS_DBGACK_BIT,
|
||||
};
|
||||
|
||||
static const struct s3c2410_wdt_variant drv_data_gs101_cl1 = {
|
||||
.mask_reset_reg = GS_CLUSTER1_NONCPU_INT_EN,
|
||||
.mask_bit = 2,
|
||||
.mask_reset_inv = true,
|
||||
.rst_stat_reg = GS_RST_STAT_REG_OFFSET,
|
||||
.rst_stat_bit = 1,
|
||||
.cnt_en_reg = GS_CLUSTER1_NONCPU_OUT,
|
||||
.cnt_en_bit = 7,
|
||||
.quirks = QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_MASK_RESET |
|
||||
QUIRK_HAS_PMU_CNT_EN | QUIRK_HAS_WTCLRINT_REG |
|
||||
QUIRK_HAS_DBGACK_BIT,
|
||||
};
|
||||
|
||||
static const struct of_device_id s3c2410_wdt_match[] = {
|
||||
{ .compatible = "google,gs101-wdt",
|
||||
.data = &drv_data_gs101_cl0 },
|
||||
{ .compatible = "samsung,s3c2410-wdt",
|
||||
.data = &drv_data_s3c2410 },
|
||||
{ .compatible = "samsung,s3c6410-wdt",
|
||||
|
|
@ -375,6 +417,19 @@ static int s3c2410wdt_enable(struct s3c2410_wdt *wdt, bool en)
|
|||
return 0;
|
||||
}
|
||||
|
||||
/* Disable watchdog outputs if CPU is in debug mode */
|
||||
static void s3c2410wdt_mask_dbgack(struct s3c2410_wdt *wdt)
|
||||
{
|
||||
unsigned long wtcon;
|
||||
|
||||
if (!(wdt->drv_data->quirks & QUIRK_HAS_DBGACK_BIT))
|
||||
return;
|
||||
|
||||
wtcon = readl(wdt->reg_base + S3C2410_WTCON);
|
||||
wtcon |= S3C2410_WTCON_DBGACK_MASK;
|
||||
writel(wtcon, wdt->reg_base + S3C2410_WTCON);
|
||||
}
|
||||
|
||||
static int s3c2410wdt_keepalive(struct watchdog_device *wdd)
|
||||
{
|
||||
struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd);
|
||||
|
|
@ -587,7 +642,8 @@ s3c2410_get_wdt_drv_data(struct platform_device *pdev, struct s3c2410_wdt *wdt)
|
|||
#ifdef CONFIG_OF
|
||||
/* Choose Exynos850/ExynosAutov9 driver data w.r.t. cluster index */
|
||||
if (variant == &drv_data_exynos850_cl0 ||
|
||||
variant == &drv_data_exynosautov9_cl0) {
|
||||
variant == &drv_data_exynosautov9_cl0 ||
|
||||
variant == &drv_data_gs101_cl0) {
|
||||
u32 index;
|
||||
int err;
|
||||
|
||||
|
|
@ -600,9 +656,12 @@ s3c2410_get_wdt_drv_data(struct platform_device *pdev, struct s3c2410_wdt *wdt)
|
|||
case 0:
|
||||
break;
|
||||
case 1:
|
||||
variant = (variant == &drv_data_exynos850_cl0) ?
|
||||
&drv_data_exynos850_cl1 :
|
||||
&drv_data_exynosautov9_cl1;
|
||||
if (variant == &drv_data_exynos850_cl0)
|
||||
variant = &drv_data_exynos850_cl1;
|
||||
else if (variant == &drv_data_exynosautov9_cl0)
|
||||
variant = &drv_data_exynosautov9_cl1;
|
||||
else if (variant == &drv_data_gs101_cl0)
|
||||
variant = &drv_data_gs101_cl1;
|
||||
break;
|
||||
default:
|
||||
return dev_err_probe(dev, -EINVAL, "wrong cluster index: %u\n", index);
|
||||
|
|
@ -700,6 +759,8 @@ static int s3c2410wdt_probe(struct platform_device *pdev)
|
|||
wdt->wdt_device.bootstatus = s3c2410wdt_get_bootstatus(wdt);
|
||||
wdt->wdt_device.parent = dev;
|
||||
|
||||
s3c2410wdt_mask_dbgack(wdt);
|
||||
|
||||
/*
|
||||
* If "tmr_atboot" param is non-zero, start the watchdog right now. Also
|
||||
* set WDOG_HW_RUNNING bit, so that watchdog core can kick the watchdog.
|
||||
|
|
|
|||
392
include/dt-bindings/clock/google,gs101.h
Normal file
392
include/dt-bindings/clock/google,gs101.h
Normal file
|
|
@ -0,0 +1,392 @@
|
|||
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
|
||||
/*
|
||||
* Copyright (C) 2023 Linaro Ltd.
|
||||
* Author: Peter Griffin <peter.griffin@linaro.org>
|
||||
*
|
||||
* Device Tree binding constants for Google gs101 clock controller.
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_CLOCK_GOOGLE_GS101_H
|
||||
#define _DT_BINDINGS_CLOCK_GOOGLE_GS101_H
|
||||
|
||||
/* CMU_TOP PLL */
|
||||
#define CLK_FOUT_SHARED0_PLL 1
|
||||
#define CLK_FOUT_SHARED1_PLL 2
|
||||
#define CLK_FOUT_SHARED2_PLL 3
|
||||
#define CLK_FOUT_SHARED3_PLL 4
|
||||
#define CLK_FOUT_SPARE_PLL 5
|
||||
|
||||
/* CMU_TOP MUX */
|
||||
#define CLK_MOUT_PLL_SHARED0 6
|
||||
#define CLK_MOUT_PLL_SHARED1 7
|
||||
#define CLK_MOUT_PLL_SHARED2 8
|
||||
#define CLK_MOUT_PLL_SHARED3 9
|
||||
#define CLK_MOUT_PLL_SPARE 10
|
||||
#define CLK_MOUT_CMU_BO_BUS 11
|
||||
#define CLK_MOUT_CMU_BUS0_BUS 12
|
||||
#define CLK_MOUT_CMU_BUS1_BUS 13
|
||||
#define CLK_MOUT_CMU_BUS2_BUS 14
|
||||
#define CLK_MOUT_CMU_CIS_CLK0 15
|
||||
#define CLK_MOUT_CMU_CIS_CLK1 16
|
||||
#define CLK_MOUT_CMU_CIS_CLK2 17
|
||||
#define CLK_MOUT_CMU_CIS_CLK3 18
|
||||
#define CLK_MOUT_CMU_CIS_CLK4 19
|
||||
#define CLK_MOUT_CMU_CIS_CLK5 20
|
||||
#define CLK_MOUT_CMU_CIS_CLK6 21
|
||||
#define CLK_MOUT_CMU_CIS_CLK7 22
|
||||
#define CLK_MOUT_CMU_CMU_BOOST 23
|
||||
#define CLK_MOUT_CMU_BOOST_OPTION1 24
|
||||
#define CLK_MOUT_CMU_CORE_BUS 25
|
||||
#define CLK_MOUT_CMU_CPUCL0_DBG 26
|
||||
#define CLK_MOUT_CMU_CPUCL0_SWITCH 27
|
||||
#define CLK_MOUT_CMU_CPUCL1_SWITCH 28
|
||||
#define CLK_MOUT_CMU_CPUCL2_SWITCH 29
|
||||
#define CLK_MOUT_CMU_CSIS_BUS 30
|
||||
#define CLK_MOUT_CMU_DISP_BUS 31
|
||||
#define CLK_MOUT_CMU_DNS_BUS 32
|
||||
#define CLK_MOUT_CMU_DPU_BUS 33
|
||||
#define CLK_MOUT_CMU_EH_BUS 34
|
||||
#define CLK_MOUT_CMU_G2D_G2D 35
|
||||
#define CLK_MOUT_CMU_G2D_MSCL 36
|
||||
#define CLK_MOUT_CMU_G3AA_G3AA 37
|
||||
#define CLK_MOUT_CMU_G3D_BUSD 38
|
||||
#define CLK_MOUT_CMU_G3D_GLB 39
|
||||
#define CLK_MOUT_CMU_G3D_SWITCH 40
|
||||
#define CLK_MOUT_CMU_GDC_GDC0 41
|
||||
#define CLK_MOUT_CMU_GDC_GDC1 42
|
||||
#define CLK_MOUT_CMU_GDC_SCSC 43
|
||||
#define CLK_MOUT_CMU_HPM 44
|
||||
#define CLK_MOUT_CMU_HSI0_BUS 45
|
||||
#define CLK_MOUT_CMU_HSI0_DPGTC 46
|
||||
#define CLK_MOUT_CMU_HSI0_USB31DRD 47
|
||||
#define CLK_MOUT_CMU_HSI0_USBDPDBG 48
|
||||
#define CLK_MOUT_CMU_HSI1_BUS 49
|
||||
#define CLK_MOUT_CMU_HSI1_PCIE 50
|
||||
#define CLK_MOUT_CMU_HSI2_BUS 51
|
||||
#define CLK_MOUT_CMU_HSI2_MMC_CARD 52
|
||||
#define CLK_MOUT_CMU_HSI2_PCIE 53
|
||||
#define CLK_MOUT_CMU_HSI2_UFS_EMBD 54
|
||||
#define CLK_MOUT_CMU_IPP_BUS 55
|
||||
#define CLK_MOUT_CMU_ITP_BUS 56
|
||||
#define CLK_MOUT_CMU_MCSC_ITSC 57
|
||||
#define CLK_MOUT_CMU_MCSC_MCSC 58
|
||||
#define CLK_MOUT_CMU_MFC_MFC 59
|
||||
#define CLK_MOUT_CMU_MIF_BUSP 60
|
||||
#define CLK_MOUT_CMU_MIF_SWITCH 61
|
||||
#define CLK_MOUT_CMU_MISC_BUS 62
|
||||
#define CLK_MOUT_CMU_MISC_SSS 63
|
||||
#define CLK_MOUT_CMU_PDP_BUS 64
|
||||
#define CLK_MOUT_CMU_PDP_VRA 65
|
||||
#define CLK_MOUT_CMU_PERIC0_BUS 66
|
||||
#define CLK_MOUT_CMU_PERIC0_IP 67
|
||||
#define CLK_MOUT_CMU_PERIC1_BUS 68
|
||||
#define CLK_MOUT_CMU_PERIC1_IP 69
|
||||
#define CLK_MOUT_CMU_TNR_BUS 70
|
||||
#define CLK_MOUT_CMU_TOP_BOOST_OPTION1 71
|
||||
#define CLK_MOUT_CMU_TOP_CMUREF 72
|
||||
#define CLK_MOUT_CMU_TPU_BUS 73
|
||||
#define CLK_MOUT_CMU_TPU_TPU 74
|
||||
#define CLK_MOUT_CMU_TPU_TPUCTL 75
|
||||
#define CLK_MOUT_CMU_TPU_UART 76
|
||||
#define CLK_MOUT_CMU_CMUREF 77
|
||||
|
||||
/* CMU_TOP Dividers */
|
||||
#define CLK_DOUT_CMU_BO_BUS 78
|
||||
#define CLK_DOUT_CMU_BUS0_BUS 79
|
||||
#define CLK_DOUT_CMU_BUS1_BUS 80
|
||||
#define CLK_DOUT_CMU_BUS2_BUS 81
|
||||
#define CLK_DOUT_CMU_CIS_CLK0 82
|
||||
#define CLK_DOUT_CMU_CIS_CLK1 83
|
||||
#define CLK_DOUT_CMU_CIS_CLK2 84
|
||||
#define CLK_DOUT_CMU_CIS_CLK3 85
|
||||
#define CLK_DOUT_CMU_CIS_CLK4 86
|
||||
#define CLK_DOUT_CMU_CIS_CLK5 87
|
||||
#define CLK_DOUT_CMU_CIS_CLK6 88
|
||||
#define CLK_DOUT_CMU_CIS_CLK7 89
|
||||
#define CLK_DOUT_CMU_CORE_BUS 90
|
||||
#define CLK_DOUT_CMU_CPUCL0_DBG 91
|
||||
#define CLK_DOUT_CMU_CPUCL0_SWITCH 92
|
||||
#define CLK_DOUT_CMU_CPUCL1_SWITCH 93
|
||||
#define CLK_DOUT_CMU_CPUCL2_SWITCH 94
|
||||
#define CLK_DOUT_CMU_CSIS_BUS 95
|
||||
#define CLK_DOUT_CMU_DISP_BUS 96
|
||||
#define CLK_DOUT_CMU_DNS_BUS 97
|
||||
#define CLK_DOUT_CMU_DPU_BUS 98
|
||||
#define CLK_DOUT_CMU_EH_BUS 99
|
||||
#define CLK_DOUT_CMU_G2D_G2D 100
|
||||
#define CLK_DOUT_CMU_G2D_MSCL 101
|
||||
#define CLK_DOUT_CMU_G3AA_G3AA 102
|
||||
#define CLK_DOUT_CMU_G3D_BUSD 103
|
||||
#define CLK_DOUT_CMU_G3D_GLB 104
|
||||
#define CLK_DOUT_CMU_G3D_SWITCH 105
|
||||
#define CLK_DOUT_CMU_GDC_GDC0 106
|
||||
#define CLK_DOUT_CMU_GDC_GDC1 107
|
||||
#define CLK_DOUT_CMU_GDC_SCSC 108
|
||||
#define CLK_DOUT_CMU_CMU_HPM 109
|
||||
#define CLK_DOUT_CMU_HSI0_BUS 110
|
||||
#define CLK_DOUT_CMU_HSI0_DPGTC 111
|
||||
#define CLK_DOUT_CMU_HSI0_USB31DRD 112
|
||||
#define CLK_DOUT_CMU_HSI0_USBDPDBG 113
|
||||
#define CLK_DOUT_CMU_HSI1_BUS 114
|
||||
#define CLK_DOUT_CMU_HSI1_PCIE 115
|
||||
#define CLK_DOUT_CMU_HSI2_BUS 116
|
||||
#define CLK_DOUT_CMU_HSI2_MMC_CARD 117
|
||||
#define CLK_DOUT_CMU_HSI2_PCIE 118
|
||||
#define CLK_DOUT_CMU_HSI2_UFS_EMBD 119
|
||||
#define CLK_DOUT_CMU_IPP_BUS 120
|
||||
#define CLK_DOUT_CMU_ITP_BUS 121
|
||||
#define CLK_DOUT_CMU_MCSC_ITSC 122
|
||||
#define CLK_DOUT_CMU_MCSC_MCSC 123
|
||||
#define CLK_DOUT_CMU_MFC_MFC 124
|
||||
#define CLK_DOUT_CMU_MIF_BUSP 125
|
||||
#define CLK_DOUT_CMU_MISC_BUS 126
|
||||
#define CLK_DOUT_CMU_MISC_SSS 127
|
||||
#define CLK_DOUT_CMU_OTP 128
|
||||
#define CLK_DOUT_CMU_PDP_BUS 129
|
||||
#define CLK_DOUT_CMU_PDP_VRA 130
|
||||
#define CLK_DOUT_CMU_PERIC0_BUS 131
|
||||
#define CLK_DOUT_CMU_PERIC0_IP 132
|
||||
#define CLK_DOUT_CMU_PERIC1_BUS 133
|
||||
#define CLK_DOUT_CMU_PERIC1_IP 134
|
||||
#define CLK_DOUT_CMU_TNR_BUS 135
|
||||
#define CLK_DOUT_CMU_TPU_BUS 136
|
||||
#define CLK_DOUT_CMU_TPU_TPU 137
|
||||
#define CLK_DOUT_CMU_TPU_TPUCTL 138
|
||||
#define CLK_DOUT_CMU_TPU_UART 139
|
||||
#define CLK_DOUT_CMU_CMU_BOOST 140
|
||||
#define CLK_DOUT_CMU_CMU_CMUREF 141
|
||||
#define CLK_DOUT_CMU_SHARED0_DIV2 142
|
||||
#define CLK_DOUT_CMU_SHARED0_DIV3 143
|
||||
#define CLK_DOUT_CMU_SHARED0_DIV4 144
|
||||
#define CLK_DOUT_CMU_SHARED0_DIV5 145
|
||||
#define CLK_DOUT_CMU_SHARED1_DIV2 146
|
||||
#define CLK_DOUT_CMU_SHARED1_DIV3 147
|
||||
#define CLK_DOUT_CMU_SHARED1_DIV4 148
|
||||
#define CLK_DOUT_CMU_SHARED2_DIV2 149
|
||||
#define CLK_DOUT_CMU_SHARED3_DIV2 150
|
||||
|
||||
/* CMU_TOP Gates */
|
||||
#define CLK_GOUT_CMU_BUS0_BOOST 151
|
||||
#define CLK_GOUT_CMU_BUS1_BOOST 152
|
||||
#define CLK_GOUT_CMU_BUS2_BOOST 153
|
||||
#define CLK_GOUT_CMU_CORE_BOOST 154
|
||||
#define CLK_GOUT_CMU_CPUCL0_BOOST 155
|
||||
#define CLK_GOUT_CMU_CPUCL1_BOOST 156
|
||||
#define CLK_GOUT_CMU_CPUCL2_BOOST 157
|
||||
#define CLK_GOUT_CMU_MIF_BOOST 158
|
||||
#define CLK_GOUT_CMU_MIF_SWITCH 159
|
||||
#define CLK_GOUT_CMU_BO_BUS 160
|
||||
#define CLK_GOUT_CMU_BUS0_BUS 161
|
||||
#define CLK_GOUT_CMU_BUS1_BUS 162
|
||||
#define CLK_GOUT_CMU_BUS2_BUS 163
|
||||
#define CLK_GOUT_CMU_CIS_CLK0 164
|
||||
#define CLK_GOUT_CMU_CIS_CLK1 165
|
||||
#define CLK_GOUT_CMU_CIS_CLK2 166
|
||||
#define CLK_GOUT_CMU_CIS_CLK3 167
|
||||
#define CLK_GOUT_CMU_CIS_CLK4 168
|
||||
#define CLK_GOUT_CMU_CIS_CLK5 169
|
||||
#define CLK_GOUT_CMU_CIS_CLK6 170
|
||||
#define CLK_GOUT_CMU_CIS_CLK7 171
|
||||
#define CLK_GOUT_CMU_CMU_BOOST 172
|
||||
#define CLK_GOUT_CMU_CORE_BUS 173
|
||||
#define CLK_GOUT_CMU_CPUCL0_DBG 174
|
||||
#define CLK_GOUT_CMU_CPUCL0_SWITCH 175
|
||||
#define CLK_GOUT_CMU_CPUCL1_SWITCH 176
|
||||
#define CLK_GOUT_CMU_CPUCL2_SWITCH 177
|
||||
#define CLK_GOUT_CMU_CSIS_BUS 178
|
||||
#define CLK_GOUT_CMU_DISP_BUS 179
|
||||
#define CLK_GOUT_CMU_DNS_BUS 180
|
||||
#define CLK_GOUT_CMU_DPU_BUS 181
|
||||
#define CLK_GOUT_CMU_EH_BUS 182
|
||||
#define CLK_GOUT_CMU_G2D_G2D 183
|
||||
#define CLK_GOUT_CMU_G2D_MSCL 184
|
||||
#define CLK_GOUT_CMU_G3AA_G3AA 185
|
||||
#define CLK_GOUT_CMU_G3D_BUSD 186
|
||||
#define CLK_GOUT_CMU_G3D_GLB 187
|
||||
#define CLK_GOUT_CMU_G3D_SWITCH 188
|
||||
#define CLK_GOUT_CMU_GDC_GDC0 189
|
||||
#define CLK_GOUT_CMU_GDC_GDC1 190
|
||||
#define CLK_GOUT_CMU_GDC_SCSC 191
|
||||
#define CLK_GOUT_CMU_HPM 192
|
||||
#define CLK_GOUT_CMU_HSI0_BUS 193
|
||||
#define CLK_GOUT_CMU_HSI0_DPGTC 194
|
||||
#define CLK_GOUT_CMU_HSI0_USB31DRD 195
|
||||
#define CLK_GOUT_CMU_HSI0_USBDPDBG 196
|
||||
#define CLK_GOUT_CMU_HSI1_BUS 197
|
||||
#define CLK_GOUT_CMU_HSI1_PCIE 198
|
||||
#define CLK_GOUT_CMU_HSI2_BUS 199
|
||||
#define CLK_GOUT_CMU_HSI2_MMC_CARD 200
|
||||
#define CLK_GOUT_CMU_HSI2_PCIE 201
|
||||
#define CLK_GOUT_CMU_HSI2_UFS_EMBD 202
|
||||
#define CLK_GOUT_CMU_IPP_BUS 203
|
||||
#define CLK_GOUT_CMU_ITP_BUS 204
|
||||
#define CLK_GOUT_CMU_MCSC_ITSC 205
|
||||
#define CLK_GOUT_CMU_MCSC_MCSC 206
|
||||
#define CLK_GOUT_CMU_MFC_MFC 207
|
||||
#define CLK_GOUT_CMU_MIF_BUSP 208
|
||||
#define CLK_GOUT_CMU_MISC_BUS 209
|
||||
#define CLK_GOUT_CMU_MISC_SSS 210
|
||||
#define CLK_GOUT_CMU_PDP_BUS 211
|
||||
#define CLK_GOUT_CMU_PDP_VRA 212
|
||||
#define CLK_GOUT_CMU_G3AA 213
|
||||
#define CLK_GOUT_CMU_PERIC0_BUS 214
|
||||
#define CLK_GOUT_CMU_PERIC0_IP 215
|
||||
#define CLK_GOUT_CMU_PERIC1_BUS 216
|
||||
#define CLK_GOUT_CMU_PERIC1_IP 217
|
||||
#define CLK_GOUT_CMU_TNR_BUS 218
|
||||
#define CLK_GOUT_CMU_TOP_CMUREF 219
|
||||
#define CLK_GOUT_CMU_TPU_BUS 220
|
||||
#define CLK_GOUT_CMU_TPU_TPU 221
|
||||
#define CLK_GOUT_CMU_TPU_TPUCTL 222
|
||||
#define CLK_GOUT_CMU_TPU_UART 223
|
||||
|
||||
/* CMU_APM */
|
||||
#define CLK_MOUT_APM_FUNC 1
|
||||
#define CLK_MOUT_APM_FUNCSRC 2
|
||||
#define CLK_DOUT_APM_BOOST 3
|
||||
#define CLK_DOUT_APM_USI0_UART 4
|
||||
#define CLK_DOUT_APM_USI0_USI 5
|
||||
#define CLK_DOUT_APM_USI1_UART 6
|
||||
#define CLK_GOUT_APM_APM_CMU_APM_PCLK 7
|
||||
#define CLK_GOUT_BUS0_BOOST_OPTION1 8
|
||||
#define CLK_GOUT_CMU_BOOST_OPTION1 9
|
||||
#define CLK_GOUT_CORE_BOOST_OPTION1 10
|
||||
#define CLK_GOUT_APM_FUNC 11
|
||||
#define CLK_GOUT_APM_APBIF_GPIO_ALIVE_PCLK 12
|
||||
#define CLK_GOUT_APM_APBIF_GPIO_FAR_ALIVE_PCLK 13
|
||||
#define CLK_GOUT_APM_APBIF_PMU_ALIVE_PCLK 14
|
||||
#define CLK_GOUT_APM_APBIF_RTC_PCLK 15
|
||||
#define CLK_GOUT_APM_APBIF_TRTC_PCLK 16
|
||||
#define CLK_GOUT_APM_APM_USI0_UART_IPCLK 17
|
||||
#define CLK_GOUT_APM_APM_USI0_UART_PCLK 18
|
||||
#define CLK_GOUT_APM_APM_USI0_USI_IPCLK 19
|
||||
#define CLK_GOUT_APM_APM_USI0_USI_PCLK 20
|
||||
#define CLK_GOUT_APM_APM_USI1_UART_IPCLK 21
|
||||
#define CLK_GOUT_APM_APM_USI1_UART_PCLK 22
|
||||
#define CLK_GOUT_APM_D_TZPC_APM_PCLK 23
|
||||
#define CLK_GOUT_APM_GPC_APM_PCLK 24
|
||||
#define CLK_GOUT_APM_GREBEINTEGRATION_HCLK 25
|
||||
#define CLK_GOUT_APM_INTMEM_ACLK 26
|
||||
#define CLK_GOUT_APM_INTMEM_PCLK 27
|
||||
#define CLK_GOUT_APM_LHM_AXI_G_SWD_I_CLK 28
|
||||
#define CLK_GOUT_APM_LHM_AXI_P_AOCAPM_I_CLK 29
|
||||
#define CLK_GOUT_APM_LHM_AXI_P_APM_I_CLK 30
|
||||
#define CLK_GOUT_APM_LHS_AXI_D_APM_I_CLK 31
|
||||
#define CLK_GOUT_APM_LHS_AXI_G_DBGCORE_I_CLK 32
|
||||
#define CLK_GOUT_APM_LHS_AXI_G_SCAN2DRAM_I_CLK 33
|
||||
#define CLK_GOUT_APM_MAILBOX_APM_AOC_PCLK 34
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||||
#define CLK_GOUT_APM_MAILBOX_APM_AP_PCLK 35
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||||
#define CLK_GOUT_APM_MAILBOX_APM_GSA_PCLK 36
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||||
#define CLK_GOUT_APM_MAILBOX_APM_SWD_PCLK 37
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||||
#define CLK_GOUT_APM_MAILBOX_APM_TPU_PCLK 38
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||||
#define CLK_GOUT_APM_MAILBOX_AP_AOC_PCLK 39
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||||
#define CLK_GOUT_APM_MAILBOX_AP_DBGCORE_PCLK 40
|
||||
#define CLK_GOUT_APM_PMU_INTR_GEN_PCLK 41
|
||||
#define CLK_GOUT_APM_ROM_CRC32_HOST_ACLK 42
|
||||
#define CLK_GOUT_APM_ROM_CRC32_HOST_PCLK 43
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||||
#define CLK_GOUT_APM_CLK_APM_BUS_CLK 44
|
||||
#define CLK_GOUT_APM_CLK_APM_USI0_UART_CLK 45
|
||||
#define CLK_GOUT_APM_CLK_APM_USI0_USI_CLK 46
|
||||
#define CLK_GOUT_APM_CLK_APM_USI1_UART_CLK 47
|
||||
#define CLK_GOUT_APM_SPEEDY_APM_PCLK 48
|
||||
#define CLK_GOUT_APM_SPEEDY_SUB_APM_PCLK 49
|
||||
#define CLK_GOUT_APM_SSMT_D_APM_ACLK 50
|
||||
#define CLK_GOUT_APM_SSMT_D_APM_PCLK 51
|
||||
#define CLK_GOUT_APM_SSMT_G_DBGCORE_ACLK 52
|
||||
#define CLK_GOUT_APM_SSMT_G_DBGCORE_PCLK 53
|
||||
#define CLK_GOUT_APM_SS_DBGCORE_SS_DBGCORE_HCLK 54
|
||||
#define CLK_GOUT_APM_SYSMMU_D_APM_CLK_S2 55
|
||||
#define CLK_GOUT_APM_SYSREG_APM_PCLK 56
|
||||
#define CLK_GOUT_APM_UASC_APM_ACLK 57
|
||||
#define CLK_GOUT_APM_UASC_APM_PCLK 58
|
||||
#define CLK_GOUT_APM_UASC_DBGCORE_ACLK 59
|
||||
#define CLK_GOUT_APM_UASC_DBGCORE_PCLK 60
|
||||
#define CLK_GOUT_APM_UASC_G_SWD_ACLK 61
|
||||
#define CLK_GOUT_APM_UASC_G_SWD_PCLK 62
|
||||
#define CLK_GOUT_APM_UASC_P_AOCAPM_ACLK 63
|
||||
#define CLK_GOUT_APM_UASC_P_AOCAPM_PCLK 64
|
||||
#define CLK_GOUT_APM_UASC_P_APM_ACLK 65
|
||||
#define CLK_GOUT_APM_UASC_P_APM_PCLK 66
|
||||
#define CLK_GOUT_APM_WDT_APM_PCLK 67
|
||||
#define CLK_GOUT_APM_XIU_DP_APM_ACLK 68
|
||||
#define CLK_APM_PLL_DIV2_APM 69
|
||||
#define CLK_APM_PLL_DIV4_APM 70
|
||||
#define CLK_APM_PLL_DIV16_APM 71
|
||||
|
||||
/* CMU_MISC */
|
||||
#define CLK_MOUT_MISC_BUS_USER 1
|
||||
#define CLK_MOUT_MISC_SSS_USER 2
|
||||
#define CLK_MOUT_MISC_GIC 3
|
||||
#define CLK_DOUT_MISC_BUSP 4
|
||||
#define CLK_DOUT_MISC_GIC 5
|
||||
#define CLK_GOUT_MISC_MISC_CMU_MISC_PCLK 6
|
||||
#define CLK_GOUT_MISC_OTP_CON_BIRA_I_OSCCLK 7
|
||||
#define CLK_GOUT_MISC_OTP_CON_BISR_I_OSCCLK 8
|
||||
#define CLK_GOUT_MISC_OTP_CON_TOP_I_OSCCLK 9
|
||||
#define CLK_GOUT_MISC_CLK_MISC_OSCCLK_CLK 10
|
||||
#define CLK_GOUT_MISC_ADM_AHB_SSS_HCLKM 11
|
||||
#define CLK_GOUT_MISC_AD_APB_DIT_PCLKM 12
|
||||
#define CLK_GOUT_MISC_AD_APB_PUF_PCLKM 13
|
||||
#define CLK_GOUT_MISC_DIT_ICLKL2A 14
|
||||
#define CLK_GOUT_MISC_D_TZPC_MISC_PCLK 15
|
||||
#define CLK_GOUT_MISC_GIC_GICCLK 16
|
||||
#define CLK_GOUT_MISC_GPC_MISC_PCLK 17
|
||||
#define CLK_GOUT_MISC_LHM_AST_ICC_CPUGIC_I_CLK 18
|
||||
#define CLK_GOUT_MISC_LHM_AXI_D_SSS_I_CLK 19
|
||||
#define CLK_GOUT_MISC_LHM_AXI_P_GIC_I_CLK 20
|
||||
#define CLK_GOUT_MISC_LHM_AXI_P_MISC_I_CLK 21
|
||||
#define CLK_GOUT_MISC_LHS_ACEL_D_MISC_I_CLK 22
|
||||
#define CLK_GOUT_MISC_LHS_AST_IRI_GICCPU_I_CLK 23
|
||||
#define CLK_GOUT_MISC_LHS_AXI_D_SSS_I_CLK 24
|
||||
#define CLK_GOUT_MISC_MCT_PCLK 25
|
||||
#define CLK_GOUT_MISC_OTP_CON_BIRA_PCLK 26
|
||||
#define CLK_GOUT_MISC_OTP_CON_BISR_PCLK 27
|
||||
#define CLK_GOUT_MISC_OTP_CON_TOP_PCLK 28
|
||||
#define CLK_GOUT_MISC_PDMA_ACLK 29
|
||||
#define CLK_GOUT_MISC_PPMU_DMA_ACLK 30
|
||||
#define CLK_GOUT_MISC_PPMU_MISC_ACLK 31
|
||||
#define CLK_GOUT_MISC_PPMU_MISC_PCLK 32
|
||||
#define CLK_GOUT_MISC_PUF_I_CLK 33
|
||||
#define CLK_GOUT_MISC_QE_DIT_ACLK 34
|
||||
#define CLK_GOUT_MISC_QE_DIT_PCLK 35
|
||||
#define CLK_GOUT_MISC_QE_PDMA_ACLK 36
|
||||
#define CLK_GOUT_MISC_QE_PDMA_PCLK 37
|
||||
#define CLK_GOUT_MISC_QE_PPMU_DMA_ACLK 38
|
||||
#define CLK_GOUT_MISC_QE_PPMU_DMA_PCLK 39
|
||||
#define CLK_GOUT_MISC_QE_RTIC_ACLK 40
|
||||
#define CLK_GOUT_MISC_QE_RTIC_PCLK 41
|
||||
#define CLK_GOUT_MISC_QE_SPDMA_ACLK 42
|
||||
#define CLK_GOUT_MISC_QE_SPDMA_PCLK 43
|
||||
#define CLK_GOUT_MISC_QE_SSS_ACLK 44
|
||||
#define CLK_GOUT_MISC_QE_SSS_PCLK 45
|
||||
#define CLK_GOUT_MISC_CLK_MISC_BUSD_CLK 46
|
||||
#define CLK_GOUT_MISC_CLK_MISC_BUSP_CLK 47
|
||||
#define CLK_GOUT_MISC_CLK_MISC_GIC_CLK 48
|
||||
#define CLK_GOUT_MISC_CLK_MISC_SSS_CLK 49
|
||||
#define CLK_GOUT_MISC_RTIC_I_ACLK 50
|
||||
#define CLK_GOUT_MISC_RTIC_I_PCLK 51
|
||||
#define CLK_GOUT_MISC_SPDMA_ACLK 52
|
||||
#define CLK_GOUT_MISC_SSMT_DIT_ACLK 53
|
||||
#define CLK_GOUT_MISC_SSMT_DIT_PCLK 54
|
||||
#define CLK_GOUT_MISC_SSMT_PDMA_ACLK 55
|
||||
#define CLK_GOUT_MISC_SSMT_PDMA_PCLK 56
|
||||
#define CLK_GOUT_MISC_SSMT_PPMU_DMA_ACLK 57
|
||||
#define CLK_GOUT_MISC_SSMT_PPMU_DMA_PCLK 58
|
||||
#define CLK_GOUT_MISC_SSMT_RTIC_ACLK 59
|
||||
#define CLK_GOUT_MISC_SSMT_RTIC_PCLK 60
|
||||
#define CLK_GOUT_MISC_SSMT_SPDMA_ACLK 61
|
||||
#define CLK_GOUT_MISC_SSMT_SPDMA_PCLK 62
|
||||
#define CLK_GOUT_MISC_SSMT_SSS_ACLK 63
|
||||
#define CLK_GOUT_MISC_SSMT_SSS_PCLK 64
|
||||
#define CLK_GOUT_MISC_SSS_I_ACLK 65
|
||||
#define CLK_GOUT_MISC_SSS_I_PCLK 66
|
||||
#define CLK_GOUT_MISC_SYSMMU_MISC_CLK_S2 67
|
||||
#define CLK_GOUT_MISC_SYSMMU_SSS_CLK_S1 68
|
||||
#define CLK_GOUT_MISC_SYSREG_MISC_PCLK 69
|
||||
#define CLK_GOUT_MISC_TMU_SUB_PCLK 70
|
||||
#define CLK_GOUT_MISC_TMU_TOP_PCLK 71
|
||||
#define CLK_GOUT_MISC_WDT_CLUSTER0_PCLK 72
|
||||
#define CLK_GOUT_MISC_WDT_CLUSTER1_PCLK 73
|
||||
#define CLK_GOUT_MISC_XIU_D_MISC_ACLK 74
|
||||
|
||||
#endif /* _DT_BINDINGS_CLOCK_GOOGLE_GS101_H */
|
||||
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Reference in New Issue
Block a user