From 4be756fd983a0d91c258196b3206e9131e63d62d Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 8 Nov 2023 11:43:27 +0100 Subject: [PATCH 01/40] dt-bindings: hwinfo: samsung,exynos-chipid: add specific compatibles for existing SoC Samsung Exynos SoC reuses several devices from older designs, thus historically we kept the old (block's) compatible only. This works fine and there is no bug here, however guidelines expressed in Documentation/devicetree/bindings/writing-bindings.rst state that: 1. Compatibles should be specific. 2. We should add new compatibles in case of bugs or features. Add compatibles specific to each SoC in front of all old-SoC-like compatibles. Reviewed-by: Alim Akhtar Acked-by: Rob Herring Link: https://lore.kernel.org/r/20231108104343.24192-2-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski --- .../bindings/hwinfo/samsung,exynos-chipid.yaml | 17 ++++++++++++++--- 1 file changed, 14 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/hwinfo/samsung,exynos-chipid.yaml b/Documentation/devicetree/bindings/hwinfo/samsung,exynos-chipid.yaml index 95cbdcb56efe..45f3d468db7c 100644 --- a/Documentation/devicetree/bindings/hwinfo/samsung,exynos-chipid.yaml +++ b/Documentation/devicetree/bindings/hwinfo/samsung,exynos-chipid.yaml @@ -11,9 +11,20 @@ maintainers: properties: compatible: - enum: - - samsung,exynos4210-chipid - - samsung,exynos850-chipid + oneOf: + - enum: + - samsung,exynos4210-chipid + - samsung,exynos850-chipid + - items: + - enum: + - samsung,exynos5433-chipid + - samsung,exynos7-chipid + - const: samsung,exynos4210-chipid + - items: + - enum: + - samsung,exynos7885-chipid + - samsung,exynosautov9-chipid + - const: samsung,exynos850-chipid reg: maxItems: 1 From 9da80ed69eb150617e8c72aeb7fdb9bfc7b97fba Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 8 Nov 2023 11:43:28 +0100 Subject: [PATCH 02/40] dt-bindings: i2c: exynos5: add specific compatibles for existing SoC Samsung Exynos SoC reuses several devices from older designs, thus historically we kept the old (block's) compatible only. This works fine and there is no bug here, however guidelines expressed in Documentation/devicetree/bindings/writing-bindings.rst state that: 1. Compatibles should be specific. 2. We should add new compatibles in case of bugs or features. Add compatibles specific to each SoC in front of all old-SoC-like compatibles. Acked-by: Rob Herring Acked-by: Wolfram Sang Link: https://lore.kernel.org/r/20231108104343.24192-3-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/i2c/i2c-exynos5.yaml | 10 +++++++++- .../devicetree/bindings/soc/samsung/exynos-usi.yaml | 2 +- 2 files changed, 10 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/i2c/i2c-exynos5.yaml b/Documentation/devicetree/bindings/i2c/i2c-exynos5.yaml index 3e52a0db6c41..c1f5d2cb7709 100644 --- a/Documentation/devicetree/bindings/i2c/i2c-exynos5.yaml +++ b/Documentation/devicetree/bindings/i2c/i2c-exynos5.yaml @@ -25,7 +25,15 @@ properties: - samsung,exynos5250-hsi2c # Exynos5250 and Exynos5420 - samsung,exynos5260-hsi2c # Exynos5260 - samsung,exynos7-hsi2c # Exynos7 - - samsung,exynosautov9-hsi2c # ExynosAutoV9 and Exynos850 + - samsung,exynosautov9-hsi2c + - items: + - enum: + - samsung,exynos5433-hsi2c + - const: samsung,exynos7-hsi2c + - items: + - enum: + - samsung,exynos850-hsi2c + - const: samsung,exynosautov9-hsi2c - const: samsung,exynos5-hsi2c # Exynos5250 and Exynos5420 deprecated: true diff --git a/Documentation/devicetree/bindings/soc/samsung/exynos-usi.yaml b/Documentation/devicetree/bindings/soc/samsung/exynos-usi.yaml index a6836904a4f8..5b7ab69546c4 100644 --- a/Documentation/devicetree/bindings/soc/samsung/exynos-usi.yaml +++ b/Documentation/devicetree/bindings/soc/samsung/exynos-usi.yaml @@ -155,7 +155,7 @@ examples: }; hsi2c_0: i2c@13820000 { - compatible = "samsung,exynosautov9-hsi2c"; + compatible = "samsung,exynos850-hsi2c", "samsung,exynosautov9-hsi2c"; reg = <0x13820000 0xc0>; interrupts = ; #address-cells = <1>; From c45860f6ee9b52b2e2f9b9255d93b9875e416cb0 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 8 Nov 2023 11:43:29 +0100 Subject: [PATCH 03/40] dt-bindings: i2c: samsung,s3c2410-i2c: add specific compatibles for existing SoC Samsung Exynos SoC reuses several devices from older designs, thus historically we kept the old (block's) compatible only. This works fine and there is no bug here, however guidelines expressed in Documentation/devicetree/bindings/writing-bindings.rst state that: 1. Compatibles should be specific. 2. We should add new compatibles in case of bugs or features. Add compatibles specific to each SoC in front of all old-SoC-like compatibles. Reviewed-by: Alim Akhtar Acked-by: Rob Herring Reviewed-by: Linus Walleij Acked-by: Wolfram Sang Link: https://lore.kernel.org/r/20231108104343.24192-4-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski --- .../bindings/i2c/samsung,s3c2410-i2c.yaml | 22 ++++++++++++------- 1 file changed, 14 insertions(+), 8 deletions(-) diff --git a/Documentation/devicetree/bindings/i2c/samsung,s3c2410-i2c.yaml b/Documentation/devicetree/bindings/i2c/samsung,s3c2410-i2c.yaml index b204e35e4f8d..1303502cf265 100644 --- a/Documentation/devicetree/bindings/i2c/samsung,s3c2410-i2c.yaml +++ b/Documentation/devicetree/bindings/i2c/samsung,s3c2410-i2c.yaml @@ -11,14 +11,20 @@ maintainers: properties: compatible: - enum: - - samsung,s3c2410-i2c - - samsung,s3c2440-i2c - # For s3c2440-like I2C used inside HDMIPHY block found on several SoCs: - - samsung,s3c2440-hdmiphy-i2c - # For s3c2440-like I2C used as a host to SATA PHY controller on an - # internal bus: - - samsung,exynos5-sata-phy-i2c + oneOf: + - enum: + - samsung,s3c2410-i2c + - samsung,s3c2440-i2c + # For s3c2440-like I2C used inside HDMIPHY block found on several SoCs: + - samsung,s3c2440-hdmiphy-i2c + # For s3c2440-like I2C used as a host to SATA PHY controller on an + # internal bus: + - samsung,exynos5-sata-phy-i2c + - items: + - enum: + - samsung,exynos7885-i2c + - samsung,exynos850-i2c + - const: samsung,s3c2440-i2c '#address-cells': const: 1 From 5a17f863c042beef7835688fe7a9667083530df2 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 8 Nov 2023 11:43:30 +0100 Subject: [PATCH 04/40] dt-bindings: mmc: samsung,exynos-dw-mshc: add specific compatibles for existing SoC Samsung Exynos SoC reuses several devices from older designs, thus historically we kept the old (block's) compatible only. This works fine and there is no bug here, however guidelines expressed in Documentation/devicetree/bindings/writing-bindings.rst state that: 1. Compatibles should be specific. 2. We should add new compatibles in case of bugs or features. Add compatibles specific to each SoC in front of all old-SoC-like compatibles. While re-indenting the first enum, put also axis,artpec8-dw-mshc in alphabetical order. Reviewed-by: Alim Akhtar Acked-by: Rob Herring Acked-by: Ulf Hansson Link: https://lore.kernel.org/r/20231108104343.24192-5-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski --- .../bindings/mmc/samsung,exynos-dw-mshc.yaml | 25 ++++++++++++------- 1 file changed, 16 insertions(+), 9 deletions(-) diff --git a/Documentation/devicetree/bindings/mmc/samsung,exynos-dw-mshc.yaml b/Documentation/devicetree/bindings/mmc/samsung,exynos-dw-mshc.yaml index 6ee78a38bd74..5fe65795f796 100644 --- a/Documentation/devicetree/bindings/mmc/samsung,exynos-dw-mshc.yaml +++ b/Documentation/devicetree/bindings/mmc/samsung,exynos-dw-mshc.yaml @@ -14,15 +14,22 @@ maintainers: properties: compatible: - enum: - - samsung,exynos4210-dw-mshc - - samsung,exynos4412-dw-mshc - - samsung,exynos5250-dw-mshc - - samsung,exynos5420-dw-mshc - - samsung,exynos5420-dw-mshc-smu - - samsung,exynos7-dw-mshc - - samsung,exynos7-dw-mshc-smu - - axis,artpec8-dw-mshc + oneOf: + - enum: + - axis,artpec8-dw-mshc + - samsung,exynos4210-dw-mshc + - samsung,exynos4412-dw-mshc + - samsung,exynos5250-dw-mshc + - samsung,exynos5420-dw-mshc + - samsung,exynos5420-dw-mshc-smu + - samsung,exynos7-dw-mshc + - samsung,exynos7-dw-mshc-smu + - items: + - enum: + - samsung,exynos5433-dw-mshc-smu + - samsung,exynos7885-dw-mshc-smu + - samsung,exynos850-dw-mshc-smu + - const: samsung,exynos7-dw-mshc-smu reg: maxItems: 1 From 1d2c16e1ab98db04af2d1215d8dddcf5c09f57c4 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 8 Nov 2023 11:43:32 +0100 Subject: [PATCH 05/40] dt-bindings: rtc: s3c-rtc: add specific compatibles for existing SoC Samsung Exynos SoC reuses several devices from older designs, thus historically we kept the old (block's) compatible only. This works fine and there is no bug here, however guidelines expressed in Documentation/devicetree/bindings/writing-bindings.rst state that: 1. Compatibles should be specific. 2. We should add new compatibles in case of bugs or features. Add compatibles specific to each SoC in front of all old-SoC-like compatibles. Reviewed-by: Alim Akhtar Acked-by: Rob Herring Acked-by: Alexandre Belloni Link: https://lore.kernel.org/r/20231108104343.24192-7-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/rtc/s3c-rtc.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/rtc/s3c-rtc.yaml b/Documentation/devicetree/bindings/rtc/s3c-rtc.yaml index d51b236939bf..bf4e11d6dffb 100644 --- a/Documentation/devicetree/bindings/rtc/s3c-rtc.yaml +++ b/Documentation/devicetree/bindings/rtc/s3c-rtc.yaml @@ -17,6 +17,11 @@ properties: - samsung,s3c2416-rtc - samsung,s3c2443-rtc - samsung,s3c6410-rtc + - items: + - enum: + - samsung,exynos7-rtc + - samsung,exynos850-rtc + - const: samsung,s3c6410-rtc - const: samsung,exynos3250-rtc deprecated: true From 5436459961da39dd4025a52e65c39e589011667c Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 8 Nov 2023 11:43:33 +0100 Subject: [PATCH 06/40] dt-bindings: serial: samsung: add specific compatibles for existing SoC Samsung Exynos SoC reuses several devices from older designs, thus historically we kept the old (block's) compatible only. This works fine and there is no bug here, however guidelines expressed in Documentation/devicetree/bindings/writing-bindings.rst state that: 1. Compatibles should be specific. 2. We should add new compatibles in case of bugs or features. Add compatibles specific to each SoC in front of all old-SoC-like compatibles. Re-shuffle also the entries in compatibles, so the one-compatible-enum is the first. Reviewed-by: Alim Akhtar Acked-by: Rob Herring Link: https://lore.kernel.org/r/20231108104343.24192-8-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski --- .../devicetree/bindings/serial/samsung_uart.yaml | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/serial/samsung_uart.yaml b/Documentation/devicetree/bindings/serial/samsung_uart.yaml index ac60ab1e35e3..0d0215b23ab7 100644 --- a/Documentation/devicetree/bindings/serial/samsung_uart.yaml +++ b/Documentation/devicetree/bindings/serial/samsung_uart.yaml @@ -18,9 +18,6 @@ description: |+ properties: compatible: oneOf: - - items: - - const: samsung,exynosautov9-uart - - const: samsung,exynos850-uart - enum: - apple,s5l-uart - axis,artpec8-uart @@ -29,6 +26,17 @@ properties: - samsung,exynos4210-uart - samsung,exynos5433-uart - samsung,exynos850-uart + - items: + - enum: + - samsung,exynos7-uart + - const: samsung,exynos4210-uart + - items: + - enum: + - samsung,exynos7885-uart + - const: samsung,exynos5433-uart + - items: + - const: samsung,exynosautov9-uart + - const: samsung,exynos850-uart reg: maxItems: 1 From 25737c24cb06c040a342072f93a42799a28432dc Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 8 Nov 2023 11:43:34 +0100 Subject: [PATCH 07/40] dt-bindings: samsung: exynos-pmu: add specific compatibles for existing SoC Samsung Exynos SoC reuses several devices from older designs, thus historically we kept the old (block's) compatible only. This works fine and there is no bug here, however guidelines expressed in Documentation/devicetree/bindings/writing-bindings.rst state that: 1. Compatibles should be specific. 2. We should add new compatibles in case of bugs or features. Add compatibles specific to each SoC in front of all old-SoC-like compatibles. Reviewed-by: Alim Akhtar Acked-by: Rob Herring Link: https://lore.kernel.org/r/20231108104343.24192-9-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski --- .../devicetree/bindings/soc/samsung/exynos-pmu.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml b/Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml index e1d716df5dfa..6492e92586d9 100644 --- a/Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml +++ b/Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml @@ -48,6 +48,12 @@ properties: - samsung,exynos850-pmu - samsung-s5pv210-pmu - const: syscon + - items: + - enum: + - samsung,exynos7885-pmu + - samsung,exynosautov9-pmu + - const: samsung,exynos7-pmu + - const: syscon - items: - enum: - samsung,exynos3250-pmu From 416231a9e38331c870da3bc84f3535e3d67cfb92 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 8 Nov 2023 11:43:35 +0100 Subject: [PATCH 08/40] dt-bindings: gpu: arm,mali-midgard: add specific compatibles for existing Exynos SoC Samsung Exynos SoC reuses several devices from older designs, thus historically we kept the old (block's) compatible only. This works fine and there is no bug here, however guidelines expressed in Documentation/devicetree/bindings/writing-bindings.rst state that: 1. Compatibles should be specific. 2. We should add new compatibles in case of bugs or features. Add compatibles specific to each SoC in front of all old-SoC-like compatibles. Reviewed-by: Alim Akhtar Acked-by: Rob Herring Link: https://lore.kernel.org/r/20231108104343.24192-10-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/gpu/arm,mali-midgard.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-midgard.yaml b/Documentation/devicetree/bindings/gpu/arm,mali-midgard.yaml index ca02baba5526..0801da33a385 100644 --- a/Documentation/devicetree/bindings/gpu/arm,mali-midgard.yaml +++ b/Documentation/devicetree/bindings/gpu/arm,mali-midgard.yaml @@ -40,6 +40,11 @@ properties: - rockchip,rk3288-mali - samsung,exynos5433-mali - const: arm,mali-t760 + - items: + - enum: + - samsung,exynos7-mali + - const: samsung,exynos5433-mali + - const: arm,mali-t760 - items: - enum: - rockchip,rk3399-mali From b709ff4da1beaab1c92df91c9023aad7388b84c4 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 8 Nov 2023 11:43:36 +0100 Subject: [PATCH 09/40] dt-bindings: iio: samsung,exynos-adc: add specific compatibles for existing SoC Samsung Exynos SoC reuses several devices from older designs, thus historically we kept the old (block's) compatible only. This works fine and there is no bug here, however guidelines expressed in Documentation/devicetree/bindings/writing-bindings.rst state that: 1. Compatibles should be specific. 2. We should add new compatibles in case of bugs or features. Add compatibles specific to each SoC in front of all old-SoC-like compatibles. Reviewed-by: Alim Akhtar Acked-by: Rob Herring Link: https://lore.kernel.org/r/20231108104343.24192-11-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski --- .../bindings/iio/adc/samsung,exynos-adc.yaml | 29 +++++++++++-------- 1 file changed, 17 insertions(+), 12 deletions(-) diff --git a/Documentation/devicetree/bindings/iio/adc/samsung,exynos-adc.yaml b/Documentation/devicetree/bindings/iio/adc/samsung,exynos-adc.yaml index 582d0a03b814..4e40f6bed5db 100644 --- a/Documentation/devicetree/bindings/iio/adc/samsung,exynos-adc.yaml +++ b/Documentation/devicetree/bindings/iio/adc/samsung,exynos-adc.yaml @@ -11,18 +11,23 @@ maintainers: properties: compatible: - enum: - - samsung,exynos-adc-v1 # Exynos5250 - - samsung,exynos-adc-v2 - - samsung,exynos3250-adc - - samsung,exynos4212-adc # Exynos4212 and Exynos4412 - - samsung,exynos7-adc - - samsung,s3c2410-adc - - samsung,s3c2416-adc - - samsung,s3c2440-adc - - samsung,s3c2443-adc - - samsung,s3c6410-adc - - samsung,s5pv210-adc + oneOf: + - enum: + - samsung,exynos-adc-v1 # Exynos5250 + - samsung,exynos-adc-v2 + - samsung,exynos3250-adc + - samsung,exynos4212-adc # Exynos4212 and Exynos4412 + - samsung,exynos7-adc + - samsung,s3c2410-adc + - samsung,s3c2416-adc + - samsung,s3c2440-adc + - samsung,s3c2443-adc + - samsung,s3c6410-adc + - samsung,s5pv210-adc + - items: + - enum: + - samsung,exynos5433-adc + - const: samsung,exynos7-adc reg: maxItems: 1 From cb931ee571be5eacd50628e108e81c065c9cb5f6 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 8 Nov 2023 11:43:37 +0100 Subject: [PATCH 10/40] ASoC: dt-bindings: samsung-i2s: add specific compatibles for existing SoC Samsung Exynos SoC reuses several devices from older designs, thus historically we kept the old (block's) compatible only. This works fine and there is no bug here, however guidelines expressed in Documentation/devicetree/bindings/writing-bindings.rst state that: 1. Compatibles should be specific. 2. We should add new compatibles in case of bugs or features. Add compatibles specific to each SoC in front of all old-SoC-like compatibles. Reviewed-by: Alim Akhtar Acked-by: Rob Herring Acked-by: Lee Jones Acked-by: Mark Brown Link: https://lore.kernel.org/r/20231108104343.24192-12-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski --- .../mfd/samsung,exynos5433-lpass.yaml | 2 +- .../bindings/sound/samsung-i2s.yaml | 19 ++++++++++++------- 2 files changed, 13 insertions(+), 8 deletions(-) diff --git a/Documentation/devicetree/bindings/mfd/samsung,exynos5433-lpass.yaml b/Documentation/devicetree/bindings/mfd/samsung,exynos5433-lpass.yaml index b97b06848729..f154103f32cc 100644 --- a/Documentation/devicetree/bindings/mfd/samsung,exynos5433-lpass.yaml +++ b/Documentation/devicetree/bindings/mfd/samsung,exynos5433-lpass.yaml @@ -85,7 +85,7 @@ examples: }; i2s@11440000 { - compatible = "samsung,exynos7-i2s"; + compatible = "samsung,exynos5433-i2s", "samsung,exynos7-i2s"; reg = <0x11440000 0x100>; dmas = <&adma 0>, <&adma 2>; dma-names = "tx", "rx"; diff --git a/Documentation/devicetree/bindings/sound/samsung-i2s.yaml b/Documentation/devicetree/bindings/sound/samsung-i2s.yaml index 30b3b6e9824b..f45f73b5056d 100644 --- a/Documentation/devicetree/bindings/sound/samsung-i2s.yaml +++ b/Documentation/devicetree/bindings/sound/samsung-i2s.yaml @@ -44,13 +44,18 @@ properties: frequencies supported by Exynos7 I2S and 7.1 channel TDM support for playback and capture TDM (Time division multiplexing) to allow transfer of multiple channel audio data on single data line. - enum: - - samsung,s3c6410-i2s - - samsung,s5pv210-i2s - - samsung,exynos5420-i2s - - samsung,exynos7-i2s - - samsung,exynos7-i2s1 - - tesla,fsd-i2s + oneOf: + - enum: + - samsung,s3c6410-i2s + - samsung,s5pv210-i2s + - samsung,exynos5420-i2s + - samsung,exynos7-i2s + - samsung,exynos7-i2s1 + - tesla,fsd-i2s + - items: + - enum: + - samsung,exynos5433-i2s + - const: samsung,exynos7-i2s '#address-cells': const: 1 From 622018516aa581d25e86a0c8a7d3a6d749d35d0e Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 8 Nov 2023 11:43:38 +0100 Subject: [PATCH 11/40] dt-bindings: pwm: samsung: add specific compatibles for existing SoC MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Samsung Exynos SoC reuses several devices from older designs, thus historically we kept the old (block's) compatible only. This works fine and there is no bug here, however guidelines expressed in Documentation/devicetree/bindings/writing-bindings.rst state that: 1. Compatibles should be specific. 2. We should add new compatibles in case of bugs or features. Add compatibles specific to each SoC in front of all old-SoC-like compatibles. Reviewed-by: Alim Akhtar Acked-by: Rob Herring Acked-by: Uwe Kleine-König Link: https://lore.kernel.org/r/20231108104343.24192-13-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/pwm/pwm-samsung.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/pwm/pwm-samsung.yaml b/Documentation/devicetree/bindings/pwm/pwm-samsung.yaml index 2162f661ed5a..89a3875cb50a 100644 --- a/Documentation/devicetree/bindings/pwm/pwm-samsung.yaml +++ b/Documentation/devicetree/bindings/pwm/pwm-samsung.yaml @@ -29,6 +29,8 @@ properties: - samsung,exynos4210-pwm # 32-bit, Exynos - items: - enum: + - samsung,exynos5433-pwm + - samsung,exynos7-pwm - samsung,exynosautov9-pwm - const: samsung,exynos4210-pwm From beea67c7c2ef161c6ee7ef4e39d842fc0be3995c Mon Sep 17 00:00:00 2001 From: Jaewon Kim Date: Wed, 15 Nov 2023 18:56:05 +0900 Subject: [PATCH 12/40] soc: samsung: exynos-chipid: add exynosautov920 SoC support Add EXYNOSAUTOV920 information to soc_ids tables. This SoC product id is "0x0A920000". Signed-off-by: Jaewon Kim Link: https://lore.kernel.org/r/20231115095609.39883-10-jaewon02.kim@samsung.com Signed-off-by: Krzysztof Kozlowski --- drivers/soc/samsung/exynos-chipid.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/soc/samsung/exynos-chipid.c b/drivers/soc/samsung/exynos-chipid.c index 3fd0f2b84dd3..b1118d37779e 100644 --- a/drivers/soc/samsung/exynos-chipid.c +++ b/drivers/soc/samsung/exynos-chipid.c @@ -59,6 +59,7 @@ static const struct exynos_soc_id { { "EXYNOS7885", 0xE7885000 }, { "EXYNOS850", 0xE3830000 }, { "EXYNOSAUTOV9", 0xAAA80000 }, + { "EXYNOSAUTOV920", 0x0A920000 }, }; static const char *product_id_to_soc_id(unsigned int product_id) From 20862a23260a3ab76ea5b425f93967d0683b28a2 Mon Sep 17 00:00:00 2001 From: Jaewon Kim Date: Wed, 15 Nov 2023 18:55:57 +0900 Subject: [PATCH 13/40] dt-bindings: samsung: exynos-sysreg: add exynosautov920 sysreg Add compatible for ExynosAutov920 sysreg controllers. Signed-off-by: Jaewon Kim Link: https://lore.kernel.org/r/20231115095609.39883-2-jaewon02.kim@samsung.com Signed-off-by: Krzysztof Kozlowski --- .../bindings/soc/samsung/samsung,exynos-sysreg.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/soc/samsung/samsung,exynos-sysreg.yaml b/Documentation/devicetree/bindings/soc/samsung/samsung,exynos-sysreg.yaml index 163e912e9cad..2de4301a467d 100644 --- a/Documentation/devicetree/bindings/soc/samsung/samsung,exynos-sysreg.yaml +++ b/Documentation/devicetree/bindings/soc/samsung/samsung,exynos-sysreg.yaml @@ -50,6 +50,11 @@ properties: - samsung,exynosautov9-peric1-sysreg - const: samsung,exynosautov9-sysreg - const: syscon + - items: + - enum: + - samsung,exynosautov920-peric0-sysreg + - samsung,exynosautov920-peric1-sysreg + - const: syscon reg: maxItems: 1 From 705672285530cd513b5549f96f92b2a9fcd63017 Mon Sep 17 00:00:00 2001 From: Jaewon Kim Date: Wed, 15 Nov 2023 18:55:58 +0900 Subject: [PATCH 14/40] dt-bindings: samsung: exynos-pmu: add exynosautov920 compatible Add samsung,exynosautov920-pmu compatible for representing pmu of ExynosAutov920 SoC. Signed-off-by: Jaewon Kim Link: https://lore.kernel.org/r/20231115095609.39883-3-jaewon02.kim@samsung.com Signed-off-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml b/Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml index 6492e92586d9..28e2cb50d85e 100644 --- a/Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml +++ b/Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml @@ -52,6 +52,7 @@ properties: - enum: - samsung,exynos7885-pmu - samsung,exynosautov9-pmu + - samsung,exynosautov920-pmu - const: samsung,exynos7-pmu - const: syscon - items: From 7a5e832d05025a3679d0fcd60584e6e946a3e358 Mon Sep 17 00:00:00 2001 From: Jaewon Kim Date: Wed, 15 Nov 2023 18:55:59 +0900 Subject: [PATCH 15/40] dt-bindings: samsung: usi: add exynosautov920-usi compatible Add samsung,exynosautov920-usi dedicated compatible for representing USI of ExynosAutoV920 SoC. Signed-off-by: Jaewon Kim Link: https://lore.kernel.org/r/20231115095609.39883-4-jaewon02.kim@samsung.com Signed-off-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/soc/samsung/exynos-usi.yaml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/soc/samsung/exynos-usi.yaml b/Documentation/devicetree/bindings/soc/samsung/exynos-usi.yaml index 5b7ab69546c4..61be1f2ddbe7 100644 --- a/Documentation/devicetree/bindings/soc/samsung/exynos-usi.yaml +++ b/Documentation/devicetree/bindings/soc/samsung/exynos-usi.yaml @@ -24,7 +24,9 @@ properties: compatible: oneOf: - items: - - const: samsung,exynosautov9-usi + - enum: + - samsung,exynosautov9-usi + - samsung,exynosautov920-usi - const: samsung,exynos850-usi - enum: - samsung,exynos850-usi From 9433b8d8d35bd0b17d6e0df76ec135dd2fe63e7c Mon Sep 17 00:00:00 2001 From: Jaewon Kim Date: Wed, 15 Nov 2023 18:56:00 +0900 Subject: [PATCH 16/40] dt-bindings: serial: samsung: add exynosautov920-uart compatible Add samsung,exynosautov9-uart dedicated compatible for representing uart of ExynosAutov920 SoC. Signed-off-by: Jaewon Kim Link: https://lore.kernel.org/r/20231115095609.39883-5-jaewon02.kim@samsung.com Signed-off-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/serial/samsung_uart.yaml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/serial/samsung_uart.yaml b/Documentation/devicetree/bindings/serial/samsung_uart.yaml index 0d0215b23ab7..e32c1b462836 100644 --- a/Documentation/devicetree/bindings/serial/samsung_uart.yaml +++ b/Documentation/devicetree/bindings/serial/samsung_uart.yaml @@ -35,7 +35,9 @@ properties: - samsung,exynos7885-uart - const: samsung,exynos5433-uart - items: - - const: samsung,exynosautov9-uart + - enum: + - samsung,exynosautov9-uart + - samsung,exynosautov920-uart - const: samsung,exynos850-uart reg: From d2d9e80a0ba6b1f507c14d6d8e2b833a474744d3 Mon Sep 17 00:00:00 2001 From: Jaewon Kim Date: Wed, 15 Nov 2023 18:56:01 +0900 Subject: [PATCH 17/40] dt-bindings: pwm: samsung: add exynosautov920 compatible MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add samsung,exynosautov920-pwm compatible string to binding document. Signed-off-by: Jaewon Kim Acked-by: Uwe Kleine-König Link: https://lore.kernel.org/r/20231115095609.39883-6-jaewon02.kim@samsung.com Signed-off-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/pwm/pwm-samsung.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/pwm/pwm-samsung.yaml b/Documentation/devicetree/bindings/pwm/pwm-samsung.yaml index 89a3875cb50a..16de6434693b 100644 --- a/Documentation/devicetree/bindings/pwm/pwm-samsung.yaml +++ b/Documentation/devicetree/bindings/pwm/pwm-samsung.yaml @@ -32,6 +32,7 @@ properties: - samsung,exynos5433-pwm - samsung,exynos7-pwm - samsung,exynosautov9-pwm + - samsung,exynosautov920-pwm - const: samsung,exynos4210-pwm reg: From 8bd05d4a86d5e1cec35dc7b8d1a5c0d925ecde1e Mon Sep 17 00:00:00 2001 From: Jaewon Kim Date: Wed, 15 Nov 2023 18:56:03 +0900 Subject: [PATCH 18/40] dt-bindings: arm: samsung: Document exynosautov920 SADK board binding Add binding for the ExynosAutov920 SADK(Samsung Automotive Development Kit) board. Signed-off-by: Jaewon Kim Link: https://lore.kernel.org/r/20231115095609.39883-8-jaewon02.kim@samsung.com Signed-off-by: Krzysztof Kozlowski --- .../devicetree/bindings/arm/samsung/samsung-boards.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml index e3ffd8159ab6..01dcbd8aa703 100644 --- a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml +++ b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml @@ -230,6 +230,12 @@ properties: - samsung,exynosautov9-sadk # Samsung Exynos Auto v9 SADK - const: samsung,exynosautov9 + - description: Exynos Auto v920 based boards + items: + - enum: + - samsung,exynosautov920-sadk # Samsung Exynos Auto v920 SADK + - const: samsung,exynosautov920 + required: - compatible From 92b022550ae55527b4ce8f8cae7863857c7b795a Mon Sep 17 00:00:00 2001 From: Jaewon Kim Date: Wed, 15 Nov 2023 18:56:04 +0900 Subject: [PATCH 19/40] dt-bindings: hwinfo: samsung,exynos-chipid: add exynosautov920 compatible Add "samsung,exynosautov920-chipid" compatible string to binding document. Signed-off-by: Jaewon Kim Link: https://lore.kernel.org/r/20231115095609.39883-9-jaewon02.kim@samsung.com Signed-off-by: Krzysztof Kozlowski --- .../devicetree/bindings/hwinfo/samsung,exynos-chipid.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/hwinfo/samsung,exynos-chipid.yaml b/Documentation/devicetree/bindings/hwinfo/samsung,exynos-chipid.yaml index 45f3d468db7c..780ccb5ee9b4 100644 --- a/Documentation/devicetree/bindings/hwinfo/samsung,exynos-chipid.yaml +++ b/Documentation/devicetree/bindings/hwinfo/samsung,exynos-chipid.yaml @@ -24,6 +24,7 @@ properties: - enum: - samsung,exynos7885-chipid - samsung,exynosautov9-chipid + - samsung,exynosautov920-chipid - const: samsung,exynos850-chipid reg: From 7677fdbc036b93a882f660ca2484a6807e72f0be Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 5 Dec 2023 10:22:24 +0100 Subject: [PATCH 20/40] dt-bindings: i2c: exynos5: add specific compatible for Tesla FSD Tesla FSD is a derivative of Samsung Exynos SoC, thus just like the others it reuses several devices from older designs. Historically we kept the old (block's) compatible only. This works fine and there is no bug here, however guidelines expressed in Documentation/devicetree/bindings/writing-bindings.rst state that: 1. Compatibles should be specific. 2. We should add new compatibles in case of bugs or features. Add Tesla FSD compatible specific to be used with an existing fallback. Acked-by: Rob Herring Acked-by: Conor Dooley Link: https://lore.kernel.org/r/20231205092229.19135-2-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/i2c/i2c-exynos5.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/i2c/i2c-exynos5.yaml b/Documentation/devicetree/bindings/i2c/i2c-exynos5.yaml index c1f5d2cb7709..df9c57bca2a8 100644 --- a/Documentation/devicetree/bindings/i2c/i2c-exynos5.yaml +++ b/Documentation/devicetree/bindings/i2c/i2c-exynos5.yaml @@ -29,6 +29,7 @@ properties: - items: - enum: - samsung,exynos5433-hsi2c + - tesla,fsd-hsi2c - const: samsung,exynos7-hsi2c - items: - enum: From edb32ec3cea79b518e6af841ecb01c839818f562 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 5 Dec 2023 10:22:25 +0100 Subject: [PATCH 21/40] dt-bindings: pwm: samsung: add specific compatible for Tesla FSD MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Tesla FSD is a derivative of Samsung Exynos SoC, thus just like the others it reuses several devices from older designs. Historically we kept the old (block's) compatible only. This works fine and there is no bug here, however guidelines expressed in Documentation/devicetree/bindings/writing-bindings.rst state that: 1. Compatibles should be specific. 2. We should add new compatibles in case of bugs or features. Add Tesla FSD compatible specific to be used with an existing fallback. Acked-by: Rob Herring Acked-by: Uwe Kleine-König Acked-by: Conor Dooley Link: https://lore.kernel.org/r/20231205092229.19135-3-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/pwm/pwm-samsung.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/pwm/pwm-samsung.yaml b/Documentation/devicetree/bindings/pwm/pwm-samsung.yaml index 16de6434693b..17a2b927af33 100644 --- a/Documentation/devicetree/bindings/pwm/pwm-samsung.yaml +++ b/Documentation/devicetree/bindings/pwm/pwm-samsung.yaml @@ -33,6 +33,7 @@ properties: - samsung,exynos7-pwm - samsung,exynosautov9-pwm - samsung,exynosautov920-pwm + - tesla,fsd-pwm - const: samsung,exynos4210-pwm reg: From 921f4f1db7f5bf6798349db8a4382c032f144b98 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 5 Dec 2023 10:22:26 +0100 Subject: [PATCH 22/40] dt-bindings: serial: samsung: add specific compatible for Tesla FSD Tesla FSD is a derivative of Samsung Exynos SoC, thus just like the others it reuses several devices from older designs. Historically we kept the old (block's) compatible only. This works fine and there is no bug here, however guidelines expressed in Documentation/devicetree/bindings/writing-bindings.rst state that: 1. Compatibles should be specific. 2. We should add new compatibles in case of bugs or features. Add Tesla FSD compatible specific to be used with an existing fallback. Acked-by: Rob Herring Acked-by: Conor Dooley Link: https://lore.kernel.org/r/20231205092229.19135-4-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/serial/samsung_uart.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/serial/samsung_uart.yaml b/Documentation/devicetree/bindings/serial/samsung_uart.yaml index e32c1b462836..4b6fc82c2edf 100644 --- a/Documentation/devicetree/bindings/serial/samsung_uart.yaml +++ b/Documentation/devicetree/bindings/serial/samsung_uart.yaml @@ -29,6 +29,7 @@ properties: - items: - enum: - samsung,exynos7-uart + - tesla,fsd-uart - const: samsung,exynos4210-uart - items: - enum: From 54772f1d61cd99ea1ed0febd4187bf24ef63bccd Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 5 Dec 2023 10:22:27 +0100 Subject: [PATCH 23/40] dt-bindings: samsung: exynos-pmu: add specific compatible for Tesla FSD Tesla FSD is a derivative of Samsung Exynos SoC, thus just like the others it reuses several devices from older designs. Historically we kept the old (block's) compatible only. This works fine and there is no bug here, however guidelines expressed in Documentation/devicetree/bindings/writing-bindings.rst state that: 1. Compatibles should be specific. 2. We should add new compatibles in case of bugs or features. Add Tesla FSD compatible specific to be used with an existing fallback. Acked-by: Rob Herring Acked-by: Conor Dooley Link: https://lore.kernel.org/r/20231205092229.19135-5-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml b/Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml index 28e2cb50d85e..65f77442ff23 100644 --- a/Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml +++ b/Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml @@ -53,6 +53,7 @@ properties: - samsung,exynos7885-pmu - samsung,exynosautov9-pmu - samsung,exynosautov920-pmu + - tesla,fsd-pmu - const: samsung,exynos7-pmu - const: syscon - items: From bf1e24c5330af06b2f7f1a166a1011d8d48e8651 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 5 Dec 2023 10:22:28 +0100 Subject: [PATCH 24/40] dt-bindings: watchdog: samsung: add specific compatible for Tesla FSD Tesla FSD is a derivative of Samsung Exynos SoC, thus just like the others it reuses several devices from older designs. Historically we kept the old (block's) compatible only. This works fine and there is no bug here, however guidelines expressed in Documentation/devicetree/bindings/writing-bindings.rst state that: 1. Compatibles should be specific. 2. We should add new compatibles in case of bugs or features. Add Tesla FSD compatible specific to be used with an existing fallback. Acked-by: Rob Herring Acked-by: Conor Dooley Link: https://lore.kernel.org/r/20231205092229.19135-6-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski --- .../bindings/watchdog/samsung-wdt.yaml | 21 ++++++++++++------- 1 file changed, 13 insertions(+), 8 deletions(-) diff --git a/Documentation/devicetree/bindings/watchdog/samsung-wdt.yaml b/Documentation/devicetree/bindings/watchdog/samsung-wdt.yaml index 8fb6656ba0c2..ea2d206b05ab 100644 --- a/Documentation/devicetree/bindings/watchdog/samsung-wdt.yaml +++ b/Documentation/devicetree/bindings/watchdog/samsung-wdt.yaml @@ -16,14 +16,19 @@ description: |+ properties: compatible: - enum: - - samsung,s3c2410-wdt # for S3C2410 - - samsung,s3c6410-wdt # for S3C6410, S5PV210 and Exynos4 - - samsung,exynos5250-wdt # for Exynos5250 - - samsung,exynos5420-wdt # for Exynos5420 - - samsung,exynos7-wdt # for Exynos7 - - samsung,exynos850-wdt # for Exynos850 - - samsung,exynosautov9-wdt # for Exynosautov9 + oneOf: + - enum: + - samsung,s3c2410-wdt # for S3C2410 + - samsung,s3c6410-wdt # for S3C6410, S5PV210 and Exynos4 + - samsung,exynos5250-wdt # for Exynos5250 + - samsung,exynos5420-wdt # for Exynos5420 + - samsung,exynos7-wdt # for Exynos7 + - samsung,exynos850-wdt # for Exynos850 + - samsung,exynosautov9-wdt # for Exynosautov9 + - items: + - enum: + - tesla,fsd-wdt + - const: samsung,exynos7-wdt reg: maxItems: 1 From fdd78ff04ccc96f628c2f93e0d48ab0a74bf34ef Mon Sep 17 00:00:00 2001 From: Peter Griffin Date: Sat, 9 Dec 2023 23:30:47 +0000 Subject: [PATCH 25/40] dt-bindings: soc: samsung: exynos-pmu: Add gs101 compatible Add gs101-pmu compatible to the bindings documentation. Reviewed-by: Sam Protsenko Signed-off-by: Peter Griffin Link: https://lore.kernel.org/r/20231209233106.147416-2-peter.griffin@linaro.org Signed-off-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml b/Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml index 65f77442ff23..15fcd8f1d8bc 100644 --- a/Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml +++ b/Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml @@ -15,6 +15,7 @@ select: compatible: contains: enum: + - google,gs101-pmu - samsung,exynos3250-pmu - samsung,exynos4210-pmu - samsung,exynos4212-pmu @@ -35,6 +36,7 @@ properties: oneOf: - items: - enum: + - google,gs101-pmu - samsung,exynos3250-pmu - samsung,exynos4210-pmu - samsung,exynos4212-pmu From 0a910f1606384a5886a045e36b1fc80a7fa6706b Mon Sep 17 00:00:00 2001 From: Peter Griffin Date: Sat, 9 Dec 2023 23:30:48 +0000 Subject: [PATCH 26/40] dt-bindings: clock: Add Google gs101 clock management unit bindings Provide dt-schema documentation for Google gs101 SoC clock controller. Currently this adds support for cmu_top, cmu_misc and cmu_apm. Reviewed-by: Sam Protsenko Signed-off-by: Peter Griffin Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20231209233106.147416-3-peter.griffin@linaro.org Signed-off-by: Krzysztof Kozlowski --- .../bindings/clock/google,gs101-clock.yaml | 106 +++++ include/dt-bindings/clock/google,gs101.h | 392 ++++++++++++++++++ 2 files changed, 498 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/google,gs101-clock.yaml create mode 100644 include/dt-bindings/clock/google,gs101.h diff --git a/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml b/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml new file mode 100644 index 000000000000..3eebc03a309b --- /dev/null +++ b/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml @@ -0,0 +1,106 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/google,gs101-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Google GS101 SoC clock controller + +maintainers: + - Peter Griffin + +description: | + Google GS101 clock controller is comprised of several CMU units, generating + clocks for different domains. Those CMU units are modeled as separate device + tree nodes, and might depend on each other. The root clock in that clock tree + is OSCCLK (24.576 MHz). That external clock must be defined as a fixed-rate + clock in dts. + + CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and + dividers; all other leaf clocks (other CMUs) are usually derived from CMU_TOP. + + Each clock is assigned an identifier and client nodes can use this identifier + to specify the clock which they consume. All clocks available for usage + in clock consumer nodes are defined as preprocessor macros in + 'dt-bindings/clock/gs101.h' header. + +properties: + compatible: + enum: + - google,gs101-cmu-top + - google,gs101-cmu-apm + - google,gs101-cmu-misc + + clocks: + minItems: 1 + maxItems: 2 + + clock-names: + minItems: 1 + maxItems: 2 + + "#clock-cells": + const: 1 + + reg: + maxItems: 1 + +required: + - compatible + - "#clock-cells" + - clocks + - clock-names + - reg + +allOf: + - if: + properties: + compatible: + contains: + enum: + - google,gs101-cmu-top + - google,gs101-cmu-apm + then: + properties: + clocks: + items: + - description: External reference clock (24.576 MHz) + + clock-names: + items: + - const: oscclk + + - if: + properties: + compatible: + contains: + const: google,gs101-cmu-misc + + then: + properties: + clocks: + items: + - description: Misc bus clock (from CMU_TOP) + - description: Misc sss clock (from CMU_TOP) + + clock-names: + items: + - const: dout_cmu_misc_bus + - const: dout_cmu_misc_sss + +additionalProperties: false + +examples: + # Clock controller node for CMU_TOP + - | + #include + + cmu_top: clock-controller@1e080000 { + compatible = "google,gs101-cmu-top"; + reg = <0x1e080000 0x8000>; + #clock-cells = <1>; + clocks = <&ext_24_5m>; + clock-names = "oscclk"; + }; + +... diff --git a/include/dt-bindings/clock/google,gs101.h b/include/dt-bindings/clock/google,gs101.h new file mode 100644 index 000000000000..5d2c2d907a7b --- /dev/null +++ b/include/dt-bindings/clock/google,gs101.h @@ -0,0 +1,392 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (C) 2023 Linaro Ltd. + * Author: Peter Griffin + * + * Device Tree binding constants for Google gs101 clock controller. + */ + +#ifndef _DT_BINDINGS_CLOCK_GOOGLE_GS101_H +#define _DT_BINDINGS_CLOCK_GOOGLE_GS101_H + +/* CMU_TOP PLL */ +#define CLK_FOUT_SHARED0_PLL 1 +#define CLK_FOUT_SHARED1_PLL 2 +#define CLK_FOUT_SHARED2_PLL 3 +#define CLK_FOUT_SHARED3_PLL 4 +#define CLK_FOUT_SPARE_PLL 5 + +/* CMU_TOP MUX */ +#define CLK_MOUT_PLL_SHARED0 6 +#define CLK_MOUT_PLL_SHARED1 7 +#define CLK_MOUT_PLL_SHARED2 8 +#define CLK_MOUT_PLL_SHARED3 9 +#define CLK_MOUT_PLL_SPARE 10 +#define CLK_MOUT_CMU_BO_BUS 11 +#define CLK_MOUT_CMU_BUS0_BUS 12 +#define CLK_MOUT_CMU_BUS1_BUS 13 +#define CLK_MOUT_CMU_BUS2_BUS 14 +#define CLK_MOUT_CMU_CIS_CLK0 15 +#define CLK_MOUT_CMU_CIS_CLK1 16 +#define CLK_MOUT_CMU_CIS_CLK2 17 +#define CLK_MOUT_CMU_CIS_CLK3 18 +#define CLK_MOUT_CMU_CIS_CLK4 19 +#define CLK_MOUT_CMU_CIS_CLK5 20 +#define CLK_MOUT_CMU_CIS_CLK6 21 +#define CLK_MOUT_CMU_CIS_CLK7 22 +#define CLK_MOUT_CMU_CMU_BOOST 23 +#define CLK_MOUT_CMU_BOOST_OPTION1 24 +#define CLK_MOUT_CMU_CORE_BUS 25 +#define CLK_MOUT_CMU_CPUCL0_DBG 26 +#define CLK_MOUT_CMU_CPUCL0_SWITCH 27 +#define CLK_MOUT_CMU_CPUCL1_SWITCH 28 +#define CLK_MOUT_CMU_CPUCL2_SWITCH 29 +#define CLK_MOUT_CMU_CSIS_BUS 30 +#define CLK_MOUT_CMU_DISP_BUS 31 +#define CLK_MOUT_CMU_DNS_BUS 32 +#define CLK_MOUT_CMU_DPU_BUS 33 +#define CLK_MOUT_CMU_EH_BUS 34 +#define CLK_MOUT_CMU_G2D_G2D 35 +#define CLK_MOUT_CMU_G2D_MSCL 36 +#define CLK_MOUT_CMU_G3AA_G3AA 37 +#define CLK_MOUT_CMU_G3D_BUSD 38 +#define CLK_MOUT_CMU_G3D_GLB 39 +#define CLK_MOUT_CMU_G3D_SWITCH 40 +#define CLK_MOUT_CMU_GDC_GDC0 41 +#define CLK_MOUT_CMU_GDC_GDC1 42 +#define CLK_MOUT_CMU_GDC_SCSC 43 +#define CLK_MOUT_CMU_HPM 44 +#define CLK_MOUT_CMU_HSI0_BUS 45 +#define CLK_MOUT_CMU_HSI0_DPGTC 46 +#define CLK_MOUT_CMU_HSI0_USB31DRD 47 +#define CLK_MOUT_CMU_HSI0_USBDPDGB 48 +#define CLK_MOUT_CMU_HSI1_BUS 49 +#define CLK_MOUT_CMU_HSI1_PCIE 50 +#define CLK_MOUT_CMU_HSI2_BUS 51 +#define CLK_MOUT_CMU_HSI2_MMC_CARD 52 +#define CLK_MOUT_CMU_HSI2_PCIE 53 +#define CLK_MOUT_CMU_HSI2_UFS_EMBD 54 +#define CLK_MOUT_CMU_IPP_BUS 55 +#define CLK_MOUT_CMU_ITP_BUS 56 +#define CLK_MOUT_CMU_MCSC_ITSC 57 +#define CLK_MOUT_CMU_MCSC_MCSC 58 +#define CLK_MOUT_CMU_MFC_MFC 59 +#define CLK_MOUT_CMU_MIF_BUSP 60 +#define CLK_MOUT_CMU_MIF_SWITCH 61 +#define CLK_MOUT_CMU_MISC_BUS 62 +#define CLK_MOUT_CMU_MISC_SSS 63 +#define CLK_MOUT_CMU_PDP_BUS 64 +#define CLK_MOUT_CMU_PDP_VRA 65 +#define CLK_MOUT_CMU_PERIC0_BUS 66 +#define CLK_MOUT_CMU_PERIC0_IP 67 +#define CLK_MOUT_CMU_PERIC1_BUS 68 +#define CLK_MOUT_CMU_PERIC1_IP 69 +#define CLK_MOUT_CMU_TNR_BUS 70 +#define CLK_MOUT_CMU_TOP_BOOST_OPTION1 71 +#define CLK_MOUT_CMU_TOP_CMUREF 72 +#define CLK_MOUT_CMU_TPU_BUS 73 +#define CLK_MOUT_CMU_TPU_TPU 74 +#define CLK_MOUT_CMU_TPU_TPUCTL 75 +#define CLK_MOUT_CMU_TPU_UART 76 +#define CLK_MOUT_CMU_CMUREF 77 + +/* CMU_TOP Dividers */ +#define CLK_DOUT_CMU_BO_BUS 78 +#define CLK_DOUT_CMU_BUS0_BUS 79 +#define CLK_DOUT_CMU_BUS1_BUS 80 +#define CLK_DOUT_CMU_BUS2_BUS 81 +#define CLK_DOUT_CMU_CIS_CLK0 82 +#define CLK_DOUT_CMU_CIS_CLK1 83 +#define CLK_DOUT_CMU_CIS_CLK2 84 +#define CLK_DOUT_CMU_CIS_CLK3 85 +#define CLK_DOUT_CMU_CIS_CLK4 86 +#define CLK_DOUT_CMU_CIS_CLK5 87 +#define CLK_DOUT_CMU_CIS_CLK6 88 +#define CLK_DOUT_CMU_CIS_CLK7 89 +#define CLK_DOUT_CMU_CORE_BUS 90 +#define CLK_DOUT_CMU_CPUCL0_DBG 91 +#define CLK_DOUT_CMU_CPUCL0_SWITCH 92 +#define CLK_DOUT_CMU_CPUCL1_SWITCH 93 +#define CLK_DOUT_CMU_CPUCL2_SWITCH 94 +#define CLK_DOUT_CMU_CSIS_BUS 95 +#define CLK_DOUT_CMU_DISP_BUS 96 +#define CLK_DOUT_CMU_DNS_BUS 97 +#define CLK_DOUT_CMU_DPU_BUS 98 +#define CLK_DOUT_CMU_EH_BUS 99 +#define CLK_DOUT_CMU_G2D_G2D 100 +#define CLK_DOUT_CMU_G2D_MSCL 101 +#define CLK_DOUT_CMU_G3AA_G3AA 102 +#define CLK_DOUT_CMU_G3D_BUSD 103 +#define CLK_DOUT_CMU_G3D_GLB 104 +#define CLK_DOUT_CMU_G3D_SWITCH 105 +#define CLK_DOUT_CMU_GDC_GDC0 106 +#define CLK_DOUT_CMU_GDC_GDC1 107 +#define CLK_DOUT_CMU_GDC_SCSC 108 +#define CLK_DOUT_CMU_CMU_HPM 109 +#define CLK_DOUT_CMU_HSI0_BUS 110 +#define CLK_DOUT_CMU_HSI0_DPGTC 111 +#define CLK_DOUT_CMU_HSI0_USB31DRD 112 +#define CLK_DOUT_CMU_HSI0_USBDPDBG 113 +#define CLK_DOUT_CMU_HSI1_BUS 114 +#define CLK_DOUT_CMU_HSI1_PCIE 115 +#define CLK_DOUT_CMU_HSI2_BUS 116 +#define CLK_DOUT_CMU_HSI2_MMC_CARD 117 +#define CLK_DOUT_CMU_HSI2_PCIE 118 +#define CLK_DOUT_CMU_HSI2_UFS_EMBD 119 +#define CLK_DOUT_CMU_IPP_BUS 120 +#define CLK_DOUT_CMU_ITP_BUS 121 +#define CLK_DOUT_CMU_MCSC_ITSC 122 +#define CLK_DOUT_CMU_MCSC_MCSC 123 +#define CLK_DOUT_CMU_MFC_MFC 124 +#define CLK_DOUT_CMU_MIF_BUSP 125 +#define CLK_DOUT_CMU_MISC_BUS 126 +#define CLK_DOUT_CMU_MISC_SSS 127 +#define CLK_DOUT_CMU_OTP 128 +#define CLK_DOUT_CMU_PDP_BUS 129 +#define CLK_DOUT_CMU_PDP_VRA 130 +#define CLK_DOUT_CMU_PERIC0_BUS 131 +#define CLK_DOUT_CMU_PERIC0_IP 132 +#define CLK_DOUT_CMU_PERIC1_BUS 133 +#define CLK_DOUT_CMU_PERIC1_IP 134 +#define CLK_DOUT_CMU_TNR_BUS 135 +#define CLK_DOUT_CMU_TPU_BUS 136 +#define CLK_DOUT_CMU_TPU_TPU 137 +#define CLK_DOUT_CMU_TPU_TPUCTL 138 +#define CLK_DOUT_CMU_TPU_UART 139 +#define CLK_DOUT_CMU_CMU_BOOST 140 +#define CLK_DOUT_CMU_CMU_CMUREF 141 +#define CLK_DOUT_CMU_SHARED0_DIV2 142 +#define CLK_DOUT_CMU_SHARED0_DIV3 143 +#define CLK_DOUT_CMU_SHARED0_DIV4 144 +#define CLK_DOUT_CMU_SHARED0_DIV5 145 +#define CLK_DOUT_CMU_SHARED1_DIV2 146 +#define CLK_DOUT_CMU_SHARED1_DIV3 147 +#define CLK_DOUT_CMU_SHARED1_DIV4 148 +#define CLK_DOUT_CMU_SHARED2_DIV2 149 +#define CLK_DOUT_CMU_SHARED3_DIV2 150 + +/* CMU_TOP Gates */ +#define CLK_GOUT_BUS0_BOOST 151 +#define CLK_GOUT_BUS1_BOOST 152 +#define CLK_GOUT_BUS2_BOOST 153 +#define CLK_GOUT_CORE_BOOST 154 +#define CLK_GOUT_CPUCL0_BOOST 155 +#define CLK_GOUT_CPUCL1_BOOST 156 +#define CLK_GOUT_CPUCL2_BOOST 157 +#define CLK_GOUT_MIF_BOOST 158 +#define CLK_GOUT_MIF_SWITCH 159 +#define CLK_GOUT_BO_BUS 160 +#define CLK_GOUT_BUS0_BUS 161 +#define CLK_GOUT_BUS1_BUS 162 +#define CLK_GOUT_BUS2_BUS 163 +#define CLK_GOUT_CIS_CLK0 164 +#define CLK_GOUT_CIS_CLK1 165 +#define CLK_GOUT_CIS_CLK2 167 +#define CLK_GOUT_CIS_CLK3 168 +#define CLK_GOUT_CIS_CLK4 169 +#define CLK_GOUT_CIS_CLK5 170 +#define CLK_GOUT_CIS_CLK6 171 +#define CLK_GOUT_CIS_CLK7 172 +#define CLK_GOUT_CMU_BOOST 173 +#define CLK_GOUT_CORE_BUS 174 +#define CLK_GOUT_CPUCL0_DBG 175 +#define CLK_GOUT_CPUCL0_SWITCH 176 +#define CLK_GOUT_CPUCL1_SWITCH 177 +#define CLK_GOUT_CPUCL2_SWITCH 178 +#define CLK_GOUT_CSIS_BUS 179 +#define CLK_GOUT_DISP_BUS 180 +#define CLK_GOUT_DNS_BUS 181 +#define CLK_GOUT_DPU_BUS 182 +#define CLK_GOUT_EH_BUS 183 +#define CLK_GOUT_G2D_G2D 184 +#define CLK_GOUT_G2D_MSCL 185 +#define CLK_GOUT_G3AA_G3AA 186 +#define CLK_GOUT_G3D_BUSD 187 +#define CLK_GOUT_G3D_GLB 188 +#define CLK_GOUT_G3D_SWITCH 189 +#define CLK_GOUT_GDC_GDC0 190 +#define CLK_GOUT_GDC_GDC1 191 +#define CLK_GOUT_GDC_SCSC 192 +#define CLK_GOUT_CMU_HPM 193 +#define CLK_GOUT_HSI0_BUS 194 +#define CLK_GOUT_HSI0_DPGTC 195 +#define CLK_GOUT_HSI0_USB31DRD 196 +#define CLK_GOUT_HSI0_USBDPDGB 197 +#define CLK_GOUT_HSI1_BUS 198 +#define CLK_GOUT_HSI1_PCIE 199 +#define CLK_GOUT_HSI2_BUS 200 +#define CLK_GOUT_HSI2_MMC_CARD 201 +#define CLK_GOUT_HSI2_PCIE 202 +#define CLK_GOUT_HSI2_UFS_EMBD 203 +#define CLK_GOUT_IPP_BUS 204 +#define CLK_GOUT_ITP_BUS 205 +#define CLK_GOUT_MCSC_ITSC 206 +#define CLK_GOUT_MCSC_MCSC 207 +#define CLK_GOUT_MFC_MFC 208 +#define CLK_GOUT_MIF_BUSP 209 +#define CLK_GOUT_MISC_BUS 210 +#define CLK_GOUT_MISC_SSS 211 +#define CLK_GOUT_PDP_BUS 212 +#define CLK_GOUT_PDP_VRA 213 +#define CLK_GOUT_G3AA 214 +#define CLK_GOUT_PERIC0_BUS 215 +#define CLK_GOUT_PERIC0_IP 216 +#define CLK_GOUT_PERIC1_BUS 217 +#define CLK_GOUT_PERIC1_IP 218 +#define CLK_GOUT_TNR_BUS 219 +#define CLK_GOUT_TOP_CMUREF 220 +#define CLK_GOUT_TPU_BUS 221 +#define CLK_GOUT_TPU_TPU 222 +#define CLK_GOUT_TPU_TPUCTL 223 +#define CLK_GOUT_TPU_UART 224 + +/* CMU_APM */ +#define CLK_MOUT_APM_FUNC 1 +#define CLK_MOUT_APM_FUNCSRC 2 +#define CLK_DOUT_APM_BOOST 3 +#define CLK_DOUT_APM_USI0_UART 4 +#define CLK_DOUT_APM_USI0_USI 5 +#define CLK_DOUT_APM_USI1_UART 6 +#define CLK_GOUT_APM_APM_CMU_APM_PCLK 7 +#define CLK_GOUT_BUS0_BOOST_OPTION1 8 +#define CLK_GOUT_CMU_BOOST_OPTION1 9 +#define CLK_GOUT_CORE_BOOST_OPTION1 10 +#define CLK_GOUT_APM_FUNC 11 +#define CLK_GOUT_APM_APBIF_GPIO_ALIVE_PCLK 12 +#define CLK_GOUT_APM_APBIF_GPIO_FAR_ALIVE_PCLK 13 +#define CLK_GOUT_APM_APBIF_PMU_ALIVE_PCLK 14 +#define CLK_GOUT_APM_APBIF_RTC_PCLK 15 +#define CLK_GOUT_APM_APBIF_TRTC_PCLK 16 +#define CLK_GOUT_APM_APM_USI0_UART_IPCLK 17 +#define CLK_GOUT_APM_APM_USI0_UART_PCLK 18 +#define CLK_GOUT_APM_APM_USI0_USI_IPCLK 19 +#define CLK_GOUT_APM_APM_USI0_USI_PCLK 20 +#define CLK_GOUT_APM_APM_USI1_UART_IPCLK 21 +#define CLK_GOUT_APM_APM_USI1_UART_PCLK 22 +#define CLK_GOUT_APM_D_TZPC_APM_PCLK 23 +#define CLK_GOUT_APM_GPC_APM_PCLK 24 +#define CLK_GOUT_APM_GREBEINTEGRATION_HCLK 25 +#define CLK_GOUT_APM_INTMEM_ACLK 26 +#define CLK_GOUT_APM_INTMEM_PCLK 27 +#define CLK_GOUT_APM_LHM_AXI_G_SWD_I_CLK 28 +#define CLK_GOUT_APM_LHM_AXI_P_AOCAPM_I_CLK 29 +#define CLK_GOUT_APM_LHM_AXI_P_APM_I_CLK 30 +#define CLK_GOUT_APM_LHS_AXI_D_APM_I_CLK 31 +#define CLK_GOUT_APM_LHS_AXI_G_DBGCORE_I_CLK 32 +#define CLK_GOUT_APM_LHS_AXI_G_SCAN2DRAM_I_CLK 33 +#define CLK_GOUT_APM_MAILBOX_APM_AOC_PCLK 34 +#define CLK_GOUT_APM_MAILBOX_APM_AP_PCLK 35 +#define CLK_GOUT_APM_MAILBOX_APM_GSA_PCLK 36 +#define CLK_GOUT_APM_MAILBOX_APM_SWD_PCLK 37 +#define CLK_GOUT_APM_MAILBOX_APM_TPU_PCLK 38 +#define CLK_GOUT_APM_MAILBOX_AP_AOC_PCLK 39 +#define CLK_GOUT_APM_MAILBOX_AP_DBGCORE_PCLK 40 +#define CLK_GOUT_APM_PMU_INTR_GEN_PCLK 41 +#define CLK_GOUT_APM_ROM_CRC32_HOST_ACLK 42 +#define CLK_GOUT_APM_ROM_CRC32_HOST_PCLK 43 +#define CLK_GOUT_APM_CLK_APM_BUS_CLK 44 +#define CLK_GOUT_APM_CLK_APM_USI0_UART_CLK 45 +#define CLK_GOUT_APM_CLK_APM_USI0_USI_CLK 46 +#define CLK_GOUT_APM_CLK_APM_USI1_UART_CLK 47 +#define CLK_GOUT_APM_SPEEDY_APM_PCLK 48 +#define CLK_GOUT_APM_SPEEDY_SUB_APM_PCLK 49 +#define CLK_GOUT_APM_SSMT_D_APM_ACLK 50 +#define CLK_GOUT_APM_SSMT_D_APM_PCLK 51 +#define CLK_GOUT_APM_SSMT_G_DBGCORE_ACLK 52 +#define CLK_GOUT_APM_SSMT_G_DBGCORE_PCLK 53 +#define CLK_GOUT_APM_SS_DBGCORE_SS_DBGCORE_HCLK 54 +#define CLK_GOUT_APM_SYSMMU_D_APM_CLK_S2 55 +#define CLK_GOUT_APM_SYSREG_APM_PCLK 56 +#define CLK_GOUT_APM_UASC_APM_ACLK 57 +#define CLK_GOUT_APM_UASC_APM_PCLK 58 +#define CLK_GOUT_APM_UASC_DBGCORE_ACLK 59 +#define CLK_GOUT_APM_UASC_DBGCORE_PCLK 60 +#define CLK_GOUT_APM_UASC_G_SWD_ACLK 61 +#define CLK_GOUT_APM_UASC_G_SWD_PCLK 62 +#define CLK_GOUT_APM_UASC_P_AOCAPM_ACLK 63 +#define CLK_GOUT_APM_UASC_P_AOCAPM_PCLK 64 +#define CLK_GOUT_APM_UASC_P_APM_ACLK 65 +#define CLK_GOUT_APM_UASC_P_APM_PCLK 66 +#define CLK_GOUT_APM_WDT_APM_PCLK 67 +#define CLK_GOUT_APM_XIU_DP_APM_ACLK 68 +#define CLK_APM_PLL_DIV2_APM 69 +#define CLK_APM_PLL_DIV4_APM 70 +#define CLK_APM_PLL_DIV16_APM 71 + +/* CMU_MISC */ +#define CLK_MOUT_MISC_BUS_USER 1 +#define CLK_MOUT_MISC_SSS_USER 2 +#define CLK_MOUT_MISC_GIC 3 +#define CLK_DOUT_MISC_BUSP 4 +#define CLK_DOUT_MISC_GIC 5 +#define CLK_GOUT_MISC_MISC_CMU_MISC_PCLK 6 +#define CLK_GOUT_MISC_OTP_CON_BIRA_I_OSCCLK 7 +#define CLK_GOUT_MISC_OTP_CON_BISR_I_OSCCLK 8 +#define CLK_GOUT_MISC_OTP_CON_TOP_I_OSCCLK 9 +#define CLK_GOUT_MISC_CLK_MISC_OSCCLK_CLK 10 +#define CLK_GOUT_MISC_ADM_AHB_SSS_HCLKM 11 +#define CLK_GOUT_MISC_AD_APB_DIT_PCLKM 12 +#define CLK_GOUT_MISC_AD_APB_PUF_PCLKM 13 +#define CLK_GOUT_MISC_DIT_ICLKL2A 14 +#define CLK_GOUT_MISC_D_TZPC_MISC_PCLK 15 +#define CLK_GOUT_MISC_GIC_GICCLK 16 +#define CLK_GOUT_MISC_GPC_MISC_PCLK 17 +#define CLK_GOUT_MISC_LHM_AST_ICC_CPUGIC_I_CLK 18 +#define CLK_GOUT_MISC_LHM_AXI_D_SSS_I_CLK 19 +#define CLK_GOUT_MISC_LHM_AXI_P_GIC_I_CLK 20 +#define CLK_GOUT_MISC_LHM_AXI_P_MISC_I_CLK 21 +#define CLK_GOUT_MISC_LHS_ACEL_D_MISC_I_CLK 22 +#define CLK_GOUT_MISC_LHS_AST_IRI_GICCPU_I_CLK 23 +#define CLK_GOUT_MISC_LHS_AXI_D_SSS_I_CLK 24 +#define CLK_GOUT_MISC_MCT_PCLK 25 +#define CLK_GOUT_MISC_OTP_CON_BIRA_PCLK 26 +#define CLK_GOUT_MISC_OTP_CON_BISR_PCLK 27 +#define CLK_GOUT_MISC_OTP_CON_TOP_PCLK 28 +#define CLK_GOUT_MISC_PDMA_ACLK 29 +#define CLK_GOUT_MISC_PPMU_DMA_ACLK 30 +#define CLK_GOUT_MISC_PPMU_MISC_ACLK 31 +#define CLK_GOUT_MISC_PPMU_MISC_PCLK 32 +#define CLK_GOUT_MISC_PUF_I_CLK 33 +#define CLK_GOUT_MISC_QE_DIT_ACLK 34 +#define CLK_GOUT_MISC_QE_DIT_PCLK 35 +#define CLK_GOUT_MISC_QE_PDMA_ACLK 36 +#define CLK_GOUT_MISC_QE_PDMA_PCLK 37 +#define CLK_GOUT_MISC_QE_PPMU_DMA_ACLK 38 +#define CLK_GOUT_MISC_QE_PPMU_DMA_PCLK 39 +#define CLK_GOUT_MISC_QE_RTIC_ACLK 40 +#define CLK_GOUT_MISC_QE_RTIC_PCLK 41 +#define CLK_GOUT_MISC_QE_SPDMA_ACLK 42 +#define CLK_GOUT_MISC_QE_SPDMA_PCLK 43 +#define CLK_GOUT_MISC_QE_SSS_ACLK 44 +#define CLK_GOUT_MISC_QE_SSS_PCLK 45 +#define CLK_GOUT_MISC_CLK_MISC_BUSD_CLK 46 +#define CLK_GOUT_MISC_CLK_MISC_BUSP_CLK 47 +#define CLK_GOUT_MISC_CLK_MISC_GIC_CLK 48 +#define CLK_GOUT_MISC_CLK_MISC_SSS_CLK 49 +#define CLK_GOUT_MISC_RTIC_I_ACLK 50 +#define CLK_GOUT_MISC_RTIC_I_PCLK 51 +#define CLK_GOUT_MISC_SPDMA_ACLK 52 +#define CLK_GOUT_MISC_SSMT_DIT_ACLK 53 +#define CLK_GOUT_MISC_SSMT_DIT_PCLK 54 +#define CLK_GOUT_MISC_SSMT_PDMA_ACLK 55 +#define CLK_GOUT_MISC_SSMT_PDMA_PCLK 56 +#define CLK_GOUT_MISC_SSMT_PPMU_DMA_ACLK 57 +#define CLK_GOUT_MISC_SSMT_PPMU_DMA_PCLK 58 +#define CLK_GOUT_MISC_SSMT_RTIC_ACLK 59 +#define CLK_GOUT_MISC_SSMT_RTIC_PCLK 60 +#define CLK_GOUT_MISC_SSMT_SPDMA_ACLK 61 +#define CLK_GOUT_MISC_SSMT_SPDMA_PCLK 62 +#define CLK_GOUT_MISC_SSMT_SSS_ACLK 63 +#define CLK_GOUT_MISC_SSMT_SSS_PCLK 64 +#define CLK_GOUT_MISC_SSS_I_ACLK 65 +#define CLK_GOUT_MISC_SSS_I_PCLK 66 +#define CLK_GOUT_MISC_SYSMMU_MISC_CLK_S2 67 +#define CLK_GOUT_MISC_SYSMMU_SSS_CLK_S1 68 +#define CLK_GOUT_MISC_SYSREG_MISC_PCLK 69 +#define CLK_GOUT_MISC_TMU_SUB_PCLK 70 +#define CLK_GOUT_MISC_TMU_TOP_PCLK 71 +#define CLK_GOUT_MISC_WDT_CLUSTER0_PCLK 72 +#define CLK_GOUT_MISC_WDT_CLUSTER1_PCLK 73 +#define CLK_GOUT_MISC_XIU_D_MISC_ACLK 74 + +#endif /* _DT_BINDINGS_CLOCK_GOOGLE_GS101_H */ From d9232785858eafde8553932f96fb7e25c2191ed2 Mon Sep 17 00:00:00 2001 From: Peter Griffin Date: Sat, 9 Dec 2023 23:30:49 +0000 Subject: [PATCH 27/40] dt-bindings: soc: google: exynos-sysreg: add dedicated SYSREG compatibles to GS101 GS101 has three different SYSREG controllers, add dedicated compatibles for them to the documentation. Reviewed-by: Sam Protsenko Signed-off-by: Peter Griffin Link: https://lore.kernel.org/r/20231209233106.147416-4-peter.griffin@linaro.org [krzysztof: move Google entries to existing enum] Signed-off-by: Krzysztof Kozlowski --- .../devicetree/bindings/soc/samsung/samsung,exynos-sysreg.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/soc/samsung/samsung,exynos-sysreg.yaml b/Documentation/devicetree/bindings/soc/samsung/samsung,exynos-sysreg.yaml index 2de4301a467d..925f787e1ea1 100644 --- a/Documentation/devicetree/bindings/soc/samsung/samsung,exynos-sysreg.yaml +++ b/Documentation/devicetree/bindings/soc/samsung/samsung,exynos-sysreg.yaml @@ -14,6 +14,9 @@ properties: oneOf: - items: - enum: + - google,gs101-apm-sysreg + - google,gs101-peric0-sysreg + - google,gs101-peric1-sysreg - samsung,exynos3-sysreg - samsung,exynos4-sysreg - samsung,exynos5-sysreg From e4f027756dff6a4e2abc640f276f91219559a3c9 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 10 Dec 2023 14:48:34 +0100 Subject: [PATCH 28/40] dt-bindings: samsung: exynos-sysreg: combine exynosautov920 with other enum No need to create a new enum every time we bring-up new SoC. Reviewed-by: Sam Protsenko Reviewed-by: Jaewon Kim Link: https://lore.kernel.org/r/20231210134834.43943-1-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski --- .../bindings/soc/samsung/samsung,exynos-sysreg.yaml | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/soc/samsung/samsung,exynos-sysreg.yaml b/Documentation/devicetree/bindings/soc/samsung/samsung,exynos-sysreg.yaml index 925f787e1ea1..1794e3799f21 100644 --- a/Documentation/devicetree/bindings/soc/samsung/samsung,exynos-sysreg.yaml +++ b/Documentation/devicetree/bindings/soc/samsung/samsung,exynos-sysreg.yaml @@ -20,6 +20,8 @@ properties: - samsung,exynos3-sysreg - samsung,exynos4-sysreg - samsung,exynos5-sysreg + - samsung,exynosautov920-peric0-sysreg + - samsung,exynosautov920-peric1-sysreg - tesla,fsd-cam-sysreg - tesla,fsd-fsys0-sysreg - tesla,fsd-fsys1-sysreg @@ -53,11 +55,6 @@ properties: - samsung,exynosautov9-peric1-sysreg - const: samsung,exynosautov9-sysreg - const: syscon - - items: - - enum: - - samsung,exynosautov920-peric0-sysreg - - samsung,exynosautov920-peric1-sysreg - - const: syscon reg: maxItems: 1 From 81306efd22fff7eecf4e62919283dd27111f0173 Mon Sep 17 00:00:00 2001 From: Peter Griffin Date: Mon, 11 Dec 2023 16:23:16 +0000 Subject: [PATCH 29/40] dt-bindings: watchdog: Document Google gs101 watchdog bindings Add the "google,gs101-wdt" compatible to the dt-schema documentation. gs101 SoC has two CPU clusters and each cluster has its own dedicated watchdog timer (similar to exynos850 and exynosautov9 SoCs). These WDT instances are controlled using different bits in PMU registers. Reviewed-by: Sam Protsenko Signed-off-by: Peter Griffin Link: https://lore.kernel.org/r/20231211162331.435900-2-peter.griffin@linaro.org Signed-off-by: Krzysztof Kozlowski --- .../devicetree/bindings/watchdog/samsung-wdt.yaml | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/watchdog/samsung-wdt.yaml b/Documentation/devicetree/bindings/watchdog/samsung-wdt.yaml index ea2d206b05ab..77a5ddd0426e 100644 --- a/Documentation/devicetree/bindings/watchdog/samsung-wdt.yaml +++ b/Documentation/devicetree/bindings/watchdog/samsung-wdt.yaml @@ -18,6 +18,7 @@ properties: compatible: oneOf: - enum: + - google,gs101-wdt # for Google gs101 - samsung,s3c2410-wdt # for S3C2410 - samsung,s3c6410-wdt # for S3C6410, S5PV210 and Exynos4 - samsung,exynos5250-wdt # for Exynos5250 @@ -47,13 +48,14 @@ properties: samsung,cluster-index: $ref: /schemas/types.yaml#/definitions/uint32 description: - Index of CPU cluster on which watchdog is running (in case of Exynos850) + Index of CPU cluster on which watchdog is running (in case of Exynos850 + or Google gs101). samsung,syscon-phandle: $ref: /schemas/types.yaml#/definitions/phandle description: Phandle to the PMU system controller node (in case of Exynos5250, - Exynos5420, Exynos7 and Exynos850). + Exynos5420, Exynos7, Exynos850 and gs101). required: - compatible @@ -69,6 +71,7 @@ allOf: compatible: contains: enum: + - google,gs101-wdt - samsung,exynos5250-wdt - samsung,exynos5420-wdt - samsung,exynos7-wdt @@ -82,6 +85,7 @@ allOf: compatible: contains: enum: + - google,gs101-wdt - samsung,exynos850-wdt - samsung,exynosautov9-wdt then: From bad3bc0a23b74e7b353978b6f58eed6c0f3b51a0 Mon Sep 17 00:00:00 2001 From: Peter Griffin Date: Mon, 11 Dec 2023 16:23:18 +0000 Subject: [PATCH 30/40] dt-bindings: serial: samsung: Add google-gs101-uart compatible Add dedicated google-gs101-uart compatible to the dt-schema for representing uart of the Google Tensor gs101 SoC. Reviewed-by: Sam Protsenko Signed-off-by: Peter Griffin Link: https://lore.kernel.org/r/20231211162331.435900-4-peter.griffin@linaro.org Signed-off-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/serial/samsung_uart.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/serial/samsung_uart.yaml b/Documentation/devicetree/bindings/serial/samsung_uart.yaml index 4b6fc82c2edf..6af274d2f185 100644 --- a/Documentation/devicetree/bindings/serial/samsung_uart.yaml +++ b/Documentation/devicetree/bindings/serial/samsung_uart.yaml @@ -21,6 +21,7 @@ properties: - enum: - apple,s5l-uart - axis,artpec8-uart + - google,gs101-uart - samsung,s3c6400-uart - samsung,s5pv210-uart - samsung,exynos4210-uart From 2072496129b7d7448f969b6334b4fd2e876a642d Mon Sep 17 00:00:00 2001 From: Peter Griffin Date: Mon, 11 Dec 2023 16:23:19 +0000 Subject: [PATCH 31/40] dt-bindings: serial: samsung: Make samsung,uart-fifosize a required property Specifying samsung,uart-fifosize in both DT and driver static data is error prone and relies on driver probe order and dt aliases to be correct. Additionally on many Exynos platforms these are (USI) universal serial interfaces which can be uart, spi or i2c, so it can change per board. For google,gs101-uart make samsung,uart-fifosize a required property. For this platform fifosize now *only* comes from DT. Reviewed-by: Sam Protsenko Signed-off-by: Peter Griffin Link: https://lore.kernel.org/r/20231211162331.435900-5-peter.griffin@linaro.org Signed-off-by: Krzysztof Kozlowski --- .../devicetree/bindings/serial/samsung_uart.yaml | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/Documentation/devicetree/bindings/serial/samsung_uart.yaml b/Documentation/devicetree/bindings/serial/samsung_uart.yaml index 6af274d2f185..133259ed3a34 100644 --- a/Documentation/devicetree/bindings/serial/samsung_uart.yaml +++ b/Documentation/devicetree/bindings/serial/samsung_uart.yaml @@ -134,6 +134,16 @@ allOf: - const: uart - const: clk_uart_baud0 + - if: + properties: + compatible: + contains: + enum: + - google,gs101-uart + then: + required: + - samsung,uart-fifosize + unevaluatedProperties: false examples: From d793f7c471fb1cc9b5cf5aee5484f4231ef48dc8 Mon Sep 17 00:00:00 2001 From: Tudor Ambarus Date: Mon, 11 Dec 2023 16:23:20 +0000 Subject: [PATCH 32/40] dt-bindings: soc: samsung: usi: add google,gs101-usi compatible Add google,gs101-usi dedicated compatible for representing USI of Google GS101 SoC. Reviewed-by: Sam Protsenko Signed-off-by: Tudor Ambarus Signed-off-by: Peter Griffin Link: https://lore.kernel.org/r/20231211162331.435900-6-peter.griffin@linaro.org Signed-off-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/soc/samsung/exynos-usi.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/soc/samsung/exynos-usi.yaml b/Documentation/devicetree/bindings/soc/samsung/exynos-usi.yaml index 61be1f2ddbe7..8b478d6cdc30 100644 --- a/Documentation/devicetree/bindings/soc/samsung/exynos-usi.yaml +++ b/Documentation/devicetree/bindings/soc/samsung/exynos-usi.yaml @@ -25,6 +25,7 @@ properties: oneOf: - items: - enum: + - google,gs101-usi - samsung,exynosautov9-usi - samsung,exynosautov920-usi - const: samsung,exynos850-usi From 5b02a863ba502482f25ae3a1bfa259838793785b Mon Sep 17 00:00:00 2001 From: Peter Griffin Date: Mon, 11 Dec 2023 16:23:21 +0000 Subject: [PATCH 33/40] dt-bindings: clock: google,gs101: fix incorrect numbering and DGB suffix MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit 166 was skipped by mistake and two clocks: * CLK_MOUT_CMU_HSI0_USBDPDGB * CLK_GOUT_HSI0_USBDPDGB Have an incorrect DGB ending instead of DBG. This is an ABI break, but as the patch was only applied yesterday this header has never been in an actual release so it seems better to fix this early than ignore it. Fixes: 0a910f160638 ("dt-bindings: clock: Add Google gs101 clock management unit bindings") Signed-off-by: Peter Griffin Reviewed-by: Chanwoo Choi Reviewed-by: Sam Protsenko Reviewed-by: André Draszik Link: https://lore.kernel.org/r/20231211162331.435900-7-peter.griffin@linaro.org Signed-off-by: Krzysztof Kozlowski --- include/dt-bindings/clock/google,gs101.h | 118 +++++++++++------------ 1 file changed, 59 insertions(+), 59 deletions(-) diff --git a/include/dt-bindings/clock/google,gs101.h b/include/dt-bindings/clock/google,gs101.h index 5d2c2d907a7b..9761c0b24e66 100644 --- a/include/dt-bindings/clock/google,gs101.h +++ b/include/dt-bindings/clock/google,gs101.h @@ -59,7 +59,7 @@ #define CLK_MOUT_CMU_HSI0_BUS 45 #define CLK_MOUT_CMU_HSI0_DPGTC 46 #define CLK_MOUT_CMU_HSI0_USB31DRD 47 -#define CLK_MOUT_CMU_HSI0_USBDPDGB 48 +#define CLK_MOUT_CMU_HSI0_USBDPDBG 48 #define CLK_MOUT_CMU_HSI1_BUS 49 #define CLK_MOUT_CMU_HSI1_PCIE 50 #define CLK_MOUT_CMU_HSI2_BUS 51 @@ -181,64 +181,64 @@ #define CLK_GOUT_BUS2_BUS 163 #define CLK_GOUT_CIS_CLK0 164 #define CLK_GOUT_CIS_CLK1 165 -#define CLK_GOUT_CIS_CLK2 167 -#define CLK_GOUT_CIS_CLK3 168 -#define CLK_GOUT_CIS_CLK4 169 -#define CLK_GOUT_CIS_CLK5 170 -#define CLK_GOUT_CIS_CLK6 171 -#define CLK_GOUT_CIS_CLK7 172 -#define CLK_GOUT_CMU_BOOST 173 -#define CLK_GOUT_CORE_BUS 174 -#define CLK_GOUT_CPUCL0_DBG 175 -#define CLK_GOUT_CPUCL0_SWITCH 176 -#define CLK_GOUT_CPUCL1_SWITCH 177 -#define CLK_GOUT_CPUCL2_SWITCH 178 -#define CLK_GOUT_CSIS_BUS 179 -#define CLK_GOUT_DISP_BUS 180 -#define CLK_GOUT_DNS_BUS 181 -#define CLK_GOUT_DPU_BUS 182 -#define CLK_GOUT_EH_BUS 183 -#define CLK_GOUT_G2D_G2D 184 -#define CLK_GOUT_G2D_MSCL 185 -#define CLK_GOUT_G3AA_G3AA 186 -#define CLK_GOUT_G3D_BUSD 187 -#define CLK_GOUT_G3D_GLB 188 -#define CLK_GOUT_G3D_SWITCH 189 -#define CLK_GOUT_GDC_GDC0 190 -#define CLK_GOUT_GDC_GDC1 191 -#define CLK_GOUT_GDC_SCSC 192 -#define CLK_GOUT_CMU_HPM 193 -#define CLK_GOUT_HSI0_BUS 194 -#define CLK_GOUT_HSI0_DPGTC 195 -#define CLK_GOUT_HSI0_USB31DRD 196 -#define CLK_GOUT_HSI0_USBDPDGB 197 -#define CLK_GOUT_HSI1_BUS 198 -#define CLK_GOUT_HSI1_PCIE 199 -#define CLK_GOUT_HSI2_BUS 200 -#define CLK_GOUT_HSI2_MMC_CARD 201 -#define CLK_GOUT_HSI2_PCIE 202 -#define CLK_GOUT_HSI2_UFS_EMBD 203 -#define CLK_GOUT_IPP_BUS 204 -#define CLK_GOUT_ITP_BUS 205 -#define CLK_GOUT_MCSC_ITSC 206 -#define CLK_GOUT_MCSC_MCSC 207 -#define CLK_GOUT_MFC_MFC 208 -#define CLK_GOUT_MIF_BUSP 209 -#define CLK_GOUT_MISC_BUS 210 -#define CLK_GOUT_MISC_SSS 211 -#define CLK_GOUT_PDP_BUS 212 -#define CLK_GOUT_PDP_VRA 213 -#define CLK_GOUT_G3AA 214 -#define CLK_GOUT_PERIC0_BUS 215 -#define CLK_GOUT_PERIC0_IP 216 -#define CLK_GOUT_PERIC1_BUS 217 -#define CLK_GOUT_PERIC1_IP 218 -#define CLK_GOUT_TNR_BUS 219 -#define CLK_GOUT_TOP_CMUREF 220 -#define CLK_GOUT_TPU_BUS 221 -#define CLK_GOUT_TPU_TPU 222 -#define CLK_GOUT_TPU_TPUCTL 223 -#define CLK_GOUT_TPU_UART 224 +#define CLK_GOUT_CIS_CLK2 166 +#define CLK_GOUT_CIS_CLK3 167 +#define CLK_GOUT_CIS_CLK4 168 +#define CLK_GOUT_CIS_CLK5 169 +#define CLK_GOUT_CIS_CLK6 170 +#define CLK_GOUT_CIS_CLK7 171 +#define CLK_GOUT_CMU_BOOST 172 +#define CLK_GOUT_CORE_BUS 173 +#define CLK_GOUT_CPUCL0_DBG 174 +#define CLK_GOUT_CPUCL0_SWITCH 175 +#define CLK_GOUT_CPUCL1_SWITCH 176 +#define CLK_GOUT_CPUCL2_SWITCH 177 +#define CLK_GOUT_CSIS_BUS 178 +#define CLK_GOUT_DISP_BUS 179 +#define CLK_GOUT_DNS_BUS 180 +#define CLK_GOUT_DPU_BUS 181 +#define CLK_GOUT_EH_BUS 182 +#define CLK_GOUT_G2D_G2D 183 +#define CLK_GOUT_G2D_MSCL 184 +#define CLK_GOUT_G3AA_G3AA 185 +#define CLK_GOUT_G3D_BUSD 186 +#define CLK_GOUT_G3D_GLB 187 +#define CLK_GOUT_G3D_SWITCH 188 +#define CLK_GOUT_GDC_GDC0 189 +#define CLK_GOUT_GDC_GDC1 190 +#define CLK_GOUT_GDC_SCSC 191 +#define CLK_GOUT_CMU_HPM 192 +#define CLK_GOUT_HSI0_BUS 193 +#define CLK_GOUT_HSI0_DPGTC 194 +#define CLK_GOUT_HSI0_USB31DRD 195 +#define CLK_GOUT_HSI0_USBDPDBG 196 +#define CLK_GOUT_HSI1_BUS 197 +#define CLK_GOUT_HSI1_PCIE 198 +#define CLK_GOUT_HSI2_BUS 199 +#define CLK_GOUT_HSI2_MMC_CARD 200 +#define CLK_GOUT_HSI2_PCIE 201 +#define CLK_GOUT_HSI2_UFS_EMBD 202 +#define CLK_GOUT_IPP_BUS 203 +#define CLK_GOUT_ITP_BUS 204 +#define CLK_GOUT_MCSC_ITSC 205 +#define CLK_GOUT_MCSC_MCSC 206 +#define CLK_GOUT_MFC_MFC 207 +#define CLK_GOUT_MIF_BUSP 208 +#define CLK_GOUT_MISC_BUS 209 +#define CLK_GOUT_MISC_SSS 210 +#define CLK_GOUT_PDP_BUS 211 +#define CLK_GOUT_PDP_VRA 212 +#define CLK_GOUT_G3AA 213 +#define CLK_GOUT_PERIC0_BUS 214 +#define CLK_GOUT_PERIC0_IP 215 +#define CLK_GOUT_PERIC1_BUS 216 +#define CLK_GOUT_PERIC1_IP 217 +#define CLK_GOUT_TNR_BUS 218 +#define CLK_GOUT_TOP_CMUREF 219 +#define CLK_GOUT_TPU_BUS 220 +#define CLK_GOUT_TPU_TPU 221 +#define CLK_GOUT_TPU_TPUCTL 222 +#define CLK_GOUT_TPU_UART 223 /* CMU_APM */ #define CLK_MOUT_APM_FUNC 1 From 13ff3bdafdd569e62e59330de18aae25ec15c97b Mon Sep 17 00:00:00 2001 From: Peter Griffin Date: Mon, 11 Dec 2023 16:23:22 +0000 Subject: [PATCH 34/40] clk: samsung: clk-pll: Add support for pll_{0516,0517,518} These plls are found in the Tensor gs101 SoC found in the Pixel 6. pll0516x: Integer PLL with high frequency pll0517x: Integer PLL with middle frequency pll0518x: Integer PLL with low frequency PLL0516x FOUT = (MDIV * 2 * FIN)/PDIV * 2^SDIV) PLL0517x and PLL0518x FOUT = (MDIV * FIN)/PDIV*2^SDIV) The PLLs are similar enough to pll_0822x that the same code can handle both. The main difference is the change in the fout formula for the high frequency 0516 pll. Locktime for 516,517 & 518 is 150 the same as the pll_0822x lock factor. MDIV, SDIV PDIV masks and bit shifts are also the same as 0822x. When defining the PLL the "con" parameter should be set to CON3 register, like this PLL(pll_0517x, CLK_FOUT_SHARED0_PLL, "fout_shared0_pll", "oscclk", PLL_LOCKTIME_PLL_SHARED0, PLL_CON3_PLL_SHARED0, NULL), Acked-by: Chanwoo Choi Tested-by: Will McVicker Reviewed-by: Sam Protsenko Signed-off-by: Peter Griffin Link: https://lore.kernel.org/r/20231211162331.435900-8-peter.griffin@linaro.org Signed-off-by: Krzysztof Kozlowski --- drivers/clk/samsung/clk-pll.c | 6 ++++++ drivers/clk/samsung/clk-pll.h | 3 +++ 2 files changed, 9 insertions(+) diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c index 74934c6182ce..4bbdf5e91650 100644 --- a/drivers/clk/samsung/clk-pll.c +++ b/drivers/clk/samsung/clk-pll.c @@ -443,6 +443,9 @@ static unsigned long samsung_pll0822x_recalc_rate(struct clk_hw *hw, sdiv = (pll_con3 >> PLL0822X_SDIV_SHIFT) & PLL0822X_SDIV_MASK; fvco *= mdiv; + if (pll->type == pll_0516x) + fvco *= 2; + do_div(fvco, (pdiv << sdiv)); return (unsigned long)fvco; @@ -1316,6 +1319,9 @@ static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx, case pll_1417x: case pll_0818x: case pll_0822x: + case pll_0516x: + case pll_0517x: + case pll_0518x: pll->enable_offs = PLL0822X_ENABLE_SHIFT; pll->lock_offs = PLL0822X_LOCK_STAT_SHIFT; if (!pll->rate_table) diff --git a/drivers/clk/samsung/clk-pll.h b/drivers/clk/samsung/clk-pll.h index 0725d485c6ee..ffd3d52c0dec 100644 --- a/drivers/clk/samsung/clk-pll.h +++ b/drivers/clk/samsung/clk-pll.h @@ -38,6 +38,9 @@ enum samsung_pll_type { pll_0822x, pll_0831x, pll_142xx, + pll_0516x, + pll_0517x, + pll_0518x, }; #define PLL_RATE(_fin, _m, _p, _s, _k, _ks) \ From 2c597bb7d66a55f2af2fff9bf4629dd07b3b9a1e Mon Sep 17 00:00:00 2001 From: Peter Griffin Date: Mon, 11 Dec 2023 16:23:23 +0000 Subject: [PATCH 35/40] clk: samsung: clk-gs101: Add cmu_top, cmu_misc and cmu_apm support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit cmu_top is the top level clock management unit which contains PLLs, muxes, dividers and gates that feed the other clock management units. cmu_misc clocks IPs such as Watchdog and cmu_apm clocks ips part of the APM module. Reviewed-by: Sam Protsenko Reviewed-by: André Draszik Acked-by: Chanwoo Choi Tested-by: Will McVicker Signed-off-by: Peter Griffin Link: https://lore.kernel.org/r/20231211162331.435900-9-peter.griffin@linaro.org [krzysztof: drop not needed linux/of_device.h include] Signed-off-by: Krzysztof Kozlowski --- drivers/clk/samsung/Makefile | 1 + drivers/clk/samsung/clk-gs101.c | 2511 +++++++++++++++++++++++++++++++ 2 files changed, 2512 insertions(+) create mode 100644 drivers/clk/samsung/clk-gs101.c diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile index ebbeacabe88f..3056944a5a54 100644 --- a/drivers/clk/samsung/Makefile +++ b/drivers/clk/samsung/Makefile @@ -21,6 +21,7 @@ obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos7.o obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos7885.o obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos850.o obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynosautov9.o +obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-gs101.o obj-$(CONFIG_S3C64XX_COMMON_CLK) += clk-s3c64xx.o obj-$(CONFIG_S5PV210_COMMON_CLK) += clk-s5pv210.o clk-s5pv210-audss.o obj-$(CONFIG_TESLA_FSD_COMMON_CLK) += clk-fsd.o diff --git a/drivers/clk/samsung/clk-gs101.c b/drivers/clk/samsung/clk-gs101.c new file mode 100644 index 000000000000..a3dda97f5eb9 --- /dev/null +++ b/drivers/clk/samsung/clk-gs101.c @@ -0,0 +1,2511 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2023 Linaro Ltd. + * Author: Peter Griffin + * + * Common Clock Framework support for GS101. + */ + +#include +#include +#include +#include + +#include + +#include "clk.h" +#include "clk-exynos-arm64.h" + +/* NOTE: Must be equal to the last clock ID increased by one */ +#define CLKS_NR_TOP (CLK_GOUT_TPU_UART + 1) +#define CLKS_NR_APM (CLK_APM_PLL_DIV16_APM + 1) +#define CLKS_NR_MISC (CLK_GOUT_MISC_XIU_D_MISC_ACLK + 1) + +/* ---- CMU_TOP ------------------------------------------------------------- */ + +/* Register Offset definitions for CMU_TOP (0x1e080000) */ + +#define PLL_LOCKTIME_PLL_SHARED0 0x0000 +#define PLL_LOCKTIME_PLL_SHARED1 0x0004 +#define PLL_LOCKTIME_PLL_SHARED2 0x0008 +#define PLL_LOCKTIME_PLL_SHARED3 0x000c +#define PLL_LOCKTIME_PLL_SPARE 0x0010 +#define PLL_CON0_PLL_SHARED0 0x0100 +#define PLL_CON1_PLL_SHARED0 0x0104 +#define PLL_CON2_PLL_SHARED0 0x0108 +#define PLL_CON3_PLL_SHARED0 0x010c +#define PLL_CON4_PLL_SHARED0 0x0110 +#define PLL_CON0_PLL_SHARED1 0x0140 +#define PLL_CON1_PLL_SHARED1 0x0144 +#define PLL_CON2_PLL_SHARED1 0x0148 +#define PLL_CON3_PLL_SHARED1 0x014c +#define PLL_CON4_PLL_SHARED1 0x0150 +#define PLL_CON0_PLL_SHARED2 0x0180 +#define PLL_CON1_PLL_SHARED2 0x0184 +#define PLL_CON2_PLL_SHARED2 0x0188 +#define PLL_CON3_PLL_SHARED2 0x018c +#define PLL_CON4_PLL_SHARED2 0x0190 +#define PLL_CON0_PLL_SHARED3 0x01c0 +#define PLL_CON1_PLL_SHARED3 0x01c4 +#define PLL_CON2_PLL_SHARED3 0x01c8 +#define PLL_CON3_PLL_SHARED3 0x01cc +#define PLL_CON4_PLL_SHARED3 0x01d0 +#define PLL_CON0_PLL_SPARE 0x0200 +#define PLL_CON1_PLL_SPARE 0x0204 +#define PLL_CON2_PLL_SPARE 0x0208 +#define PLL_CON3_PLL_SPARE 0x020c +#define PLL_CON4_PLL_SPARE 0x0210 +#define CMU_CMU_TOP_CONTROLLER_OPTION 0x0800 +#define CLKOUT_CON_BLK_CMU_CMU_TOP_CLKOUT0 0x0810 +#define CMU_HCHGEN_CLKMUX_CMU_BOOST 0x0840 +#define CMU_HCHGEN_CLKMUX_TOP_BOOST 0x0844 +#define CMU_HCHGEN_CLKMUX 0x0850 +#define POWER_FAIL_DETECT_PLL 0x0864 +#define EARLY_WAKEUP_FORCED_0_ENABLE 0x0870 +#define EARLY_WAKEUP_FORCED_1_ENABLE 0x0874 +#define EARLY_WAKEUP_APM_CTRL 0x0878 +#define EARLY_WAKEUP_CLUSTER0_CTRL 0x087c +#define EARLY_WAKEUP_DPU_CTRL 0x0880 +#define EARLY_WAKEUP_CSIS_CTRL 0x0884 +#define EARLY_WAKEUP_APM_DEST 0x0890 +#define EARLY_WAKEUP_CLUSTER0_DEST 0x0894 +#define EARLY_WAKEUP_DPU_DEST 0x0898 +#define EARLY_WAKEUP_CSIS_DEST 0x089c +#define EARLY_WAKEUP_SW_TRIG_APM 0x08c0 +#define EARLY_WAKEUP_SW_TRIG_APM_SET 0x08c4 +#define EARLY_WAKEUP_SW_TRIG_APM_CLEAR 0x08c8 +#define EARLY_WAKEUP_SW_TRIG_CLUSTER0 0x08d0 +#define EARLY_WAKEUP_SW_TRIG_CLUSTER0_SET 0x08d4 +#define EARLY_WAKEUP_SW_TRIG_CLUSTER0_CLEAR 0x08d8 +#define EARLY_WAKEUP_SW_TRIG_DPU 0x08e0 +#define EARLY_WAKEUP_SW_TRIG_DPU_SET 0x08e4 +#define EARLY_WAKEUP_SW_TRIG_DPU_CLEAR 0x08e8 +#define EARLY_WAKEUP_SW_TRIG_CSIS 0x08f0 +#define EARLY_WAKEUP_SW_TRIG_CSIS_SET 0x08f4 +#define EARLY_WAKEUP_SW_TRIG_CSIS_CLEAR 0x08f8 +#define CLK_CON_MUX_MUX_CLKCMU_BO_BUS 0x1000 +#define CLK_CON_MUX_MUX_CLKCMU_BUS0_BUS 0x1004 +#define CLK_CON_MUX_MUX_CLKCMU_BUS1_BUS 0x1008 +#define CLK_CON_MUX_MUX_CLKCMU_BUS2_BUS 0x100c +#define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0 0x1010 +#define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1 0x1014 +#define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2 0x1018 +#define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3 0x101c +#define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK4 0x1020 +#define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK5 0x1024 +#define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK6 0x1028 +#define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK7 0x102c +#define CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST 0x1030 +#define CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_OPTION1 0x1034 +#define CLK_CON_MUX_MUX_CLKCMU_CORE_BUS 0x1038 +#define CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG 0x103c +#define CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH 0x1040 +#define CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH 0x1044 +#define CLK_CON_MUX_MUX_CLKCMU_CPUCL2_SWITCH 0x1048 +#define CLK_CON_MUX_MUX_CLKCMU_CSIS_BUS 0x104c +#define CLK_CON_MUX_MUX_CLKCMU_DISP_BUS 0x1050 +#define CLK_CON_MUX_MUX_CLKCMU_DNS_BUS 0x1054 +#define CLK_CON_MUX_MUX_CLKCMU_DPU_BUS 0x1058 +#define CLK_CON_MUX_MUX_CLKCMU_EH_BUS 0x105c +#define CLK_CON_MUX_MUX_CLKCMU_G2D_G2D 0x1060 +#define CLK_CON_MUX_MUX_CLKCMU_G2D_MSCL 0x1064 +#define CLK_CON_MUX_MUX_CLKCMU_G3AA_G3AA 0x1068 +#define CLK_CON_MUX_MUX_CLKCMU_G3D_BUSD 0x106c +#define CLK_CON_MUX_MUX_CLKCMU_G3D_GLB 0x1070 +#define CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH 0x1074 +#define CLK_CON_MUX_MUX_CLKCMU_GDC_GDC0 0x1078 +#define CLK_CON_MUX_MUX_CLKCMU_GDC_GDC1 0x107c +#define CLK_CON_MUX_MUX_CLKCMU_GDC_SCSC 0x1080 +#define CLK_CON_MUX_MUX_CLKCMU_HPM 0x1084 +#define CLK_CON_MUX_MUX_CLKCMU_HSI0_BUS 0x1088 +#define CLK_CON_MUX_MUX_CLKCMU_HSI0_DPGTC 0x108c +#define CLK_CON_MUX_MUX_CLKCMU_HSI0_USB31DRD 0x1090 +#define CLK_CON_MUX_MUX_CLKCMU_HSI0_USBDPDBG 0x1094 +#define CLK_CON_MUX_MUX_CLKCMU_HSI1_BUS 0x1098 +#define CLK_CON_MUX_MUX_CLKCMU_HSI1_PCIE 0x109c +#define CLK_CON_MUX_MUX_CLKCMU_HSI2_BUS 0x10a0 +#define CLK_CON_MUX_MUX_CLKCMU_HSI2_MMC_CARD 0x10a4 +#define CLK_CON_MUX_MUX_CLKCMU_HSI2_PCIE 0x10a8 +#define CLK_CON_MUX_MUX_CLKCMU_HSI2_UFS_EMBD 0x10ac +#define CLK_CON_MUX_MUX_CLKCMU_IPP_BUS 0x10b0 +#define CLK_CON_MUX_MUX_CLKCMU_ITP_BUS 0x10b4 +#define CLK_CON_MUX_MUX_CLKCMU_MCSC_ITSC 0x10b8 +#define CLK_CON_MUX_MUX_CLKCMU_MCSC_MCSC 0x10bc +#define CLK_CON_MUX_MUX_CLKCMU_MFC_MFC 0x10c0 +#define CLK_CON_MUX_MUX_CLKCMU_MIF_BUSP 0x10c4 +#define CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH 0x10c8 +#define CLK_CON_MUX_MUX_CLKCMU_MISC_BUS 0x10cc +#define CLK_CON_MUX_MUX_CLKCMU_MISC_SSS 0x10d0 +#define CLK_CON_MUX_MUX_CLKCMU_PDP_BUS 0x10d4 +#define CLK_CON_MUX_MUX_CLKCMU_PDP_VRA 0x10d8 +#define CLK_CON_MUX_MUX_CLKCMU_PERIC0_BUS 0x10dc +#define CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP 0x10e0 +#define CLK_CON_MUX_MUX_CLKCMU_PERIC1_BUS 0x10e4 +#define CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP 0x10e8 +#define CLK_CON_MUX_MUX_CLKCMU_TNR_BUS 0x10ec +#define CLK_CON_MUX_MUX_CLKCMU_TOP_BOOST_OPTION1 0x10f0 +#define CLK_CON_MUX_MUX_CLKCMU_TOP_CMUREF 0x10f4 +#define CLK_CON_MUX_MUX_CLKCMU_TPU_BUS 0x10f8 +#define CLK_CON_MUX_MUX_CLKCMU_TPU_TPU 0x10fc +#define CLK_CON_MUX_MUX_CLKCMU_TPU_TPUCTL 0x1100 +#define CLK_CON_MUX_MUX_CLKCMU_TPU_UART 0x1104 +#define CLK_CON_MUX_MUX_CMU_CMUREF 0x1108 +#define CLK_CON_DIV_CLKCMU_BO_BUS 0x1800 +#define CLK_CON_DIV_CLKCMU_BUS0_BUS 0x1804 +#define CLK_CON_DIV_CLKCMU_BUS1_BUS 0x1808 +#define CLK_CON_DIV_CLKCMU_BUS2_BUS 0x180c +#define CLK_CON_DIV_CLKCMU_CIS_CLK0 0x1810 +#define CLK_CON_DIV_CLKCMU_CIS_CLK1 0x1814 +#define CLK_CON_DIV_CLKCMU_CIS_CLK2 0x1818 +#define CLK_CON_DIV_CLKCMU_CIS_CLK3 0x181c +#define CLK_CON_DIV_CLKCMU_CIS_CLK4 0x1820 +#define CLK_CON_DIV_CLKCMU_CIS_CLK5 0x1824 +#define CLK_CON_DIV_CLKCMU_CIS_CLK6 0x1828 +#define CLK_CON_DIV_CLKCMU_CIS_CLK7 0x182c +#define CLK_CON_DIV_CLKCMU_CORE_BUS 0x1830 +#define CLK_CON_DIV_CLKCMU_CPUCL0_DBG 0x1834 +#define CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH 0x1838 +#define CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH 0x183c +#define CLK_CON_DIV_CLKCMU_CPUCL2_SWITCH 0x1840 +#define CLK_CON_DIV_CLKCMU_CSIS_BUS 0x1844 +#define CLK_CON_DIV_CLKCMU_DISP_BUS 0x1848 +#define CLK_CON_DIV_CLKCMU_DNS_BUS 0x184c +#define CLK_CON_DIV_CLKCMU_DPU_BUS 0x1850 +#define CLK_CON_DIV_CLKCMU_EH_BUS 0x1854 +#define CLK_CON_DIV_CLKCMU_G2D_G2D 0x1858 +#define CLK_CON_DIV_CLKCMU_G2D_MSCL 0x185c +#define CLK_CON_DIV_CLKCMU_G3AA_G3AA 0x1860 +#define CLK_CON_DIV_CLKCMU_G3D_BUSD 0x1864 +#define CLK_CON_DIV_CLKCMU_G3D_GLB 0x1868 +#define CLK_CON_DIV_CLKCMU_G3D_SWITCH 0x186c +#define CLK_CON_DIV_CLKCMU_GDC_GDC0 0x1870 +#define CLK_CON_DIV_CLKCMU_GDC_GDC1 0x1874 +#define CLK_CON_DIV_CLKCMU_GDC_SCSC 0x1878 +#define CLK_CON_DIV_CLKCMU_HPM 0x187c +#define CLK_CON_DIV_CLKCMU_HSI0_BUS 0x1880 +#define CLK_CON_DIV_CLKCMU_HSI0_DPGTC 0x1884 +#define CLK_CON_DIV_CLKCMU_HSI0_USB31DRD 0x1888 +#define CLK_CON_DIV_CLKCMU_HSI0_USBDPDBG 0x188c +#define CLK_CON_DIV_CLKCMU_HSI1_BUS 0x1890 +#define CLK_CON_DIV_CLKCMU_HSI1_PCIE 0x1894 +#define CLK_CON_DIV_CLKCMU_HSI2_BUS 0x1898 +#define CLK_CON_DIV_CLKCMU_HSI2_MMC_CARD 0x189c +#define CLK_CON_DIV_CLKCMU_HSI2_PCIE 0x18a0 +#define CLK_CON_DIV_CLKCMU_HSI2_UFS_EMBD 0x18a4 +#define CLK_CON_DIV_CLKCMU_IPP_BUS 0x18a8 +#define CLK_CON_DIV_CLKCMU_ITP_BUS 0x18ac +#define CLK_CON_DIV_CLKCMU_MCSC_ITSC 0x18b0 +#define CLK_CON_DIV_CLKCMU_MCSC_MCSC 0x18b4 +#define CLK_CON_DIV_CLKCMU_MFC_MFC 0x18b8 +#define CLK_CON_DIV_CLKCMU_MIF_BUSP 0x18bc +#define CLK_CON_DIV_CLKCMU_MISC_BUS 0x18c0 +#define CLK_CON_DIV_CLKCMU_MISC_SSS 0x18c4 +#define CLK_CON_DIV_CLKCMU_OTP 0x18c8 +#define CLK_CON_DIV_CLKCMU_PDP_BUS 0x18cc +#define CLK_CON_DIV_CLKCMU_PDP_VRA 0x18d0 +#define CLK_CON_DIV_CLKCMU_PERIC0_BUS 0x18d4 +#define CLK_CON_DIV_CLKCMU_PERIC0_IP 0x18d8 +#define CLK_CON_DIV_CLKCMU_PERIC1_BUS 0x18dc +#define CLK_CON_DIV_CLKCMU_PERIC1_IP 0x18e0 +#define CLK_CON_DIV_CLKCMU_TNR_BUS 0x18e4 +#define CLK_CON_DIV_CLKCMU_TPU_BUS 0x18e8 +#define CLK_CON_DIV_CLKCMU_TPU_TPU 0x18ec +#define CLK_CON_DIV_CLKCMU_TPU_TPUCTL 0x18f0 +#define CLK_CON_DIV_CLKCMU_TPU_UART 0x18f4 +#define CLK_CON_DIV_DIV_CLKCMU_CMU_BOOST 0x18f8 +#define CLK_CON_DIV_DIV_CLK_CMU_CMUREF 0x18fc +#define CLK_CON_DIV_PLL_SHARED0_DIV2 0x1900 +#define CLK_CON_DIV_PLL_SHARED0_DIV3 0x1904 +#define CLK_CON_DIV_PLL_SHARED0_DIV4 0x1908 +#define CLK_CON_DIV_PLL_SHARED0_DIV5 0x190c +#define CLK_CON_DIV_PLL_SHARED1_DIV2 0x1910 +#define CLK_CON_DIV_PLL_SHARED1_DIV3 0x1914 +#define CLK_CON_DIV_PLL_SHARED1_DIV4 0x1918 +#define CLK_CON_DIV_PLL_SHARED2_DIV2 0x191c +#define CLK_CON_DIV_PLL_SHARED3_DIV2 0x1920 +#define CLK_CON_GAT_CLKCMU_BUS0_BOOST 0x2000 +#define CLK_CON_GAT_CLKCMU_BUS1_BOOST 0x2004 +#define CLK_CON_GAT_CLKCMU_BUS2_BOOST 0x2008 +#define CLK_CON_GAT_CLKCMU_CORE_BOOST 0x200c +#define CLK_CON_GAT_CLKCMU_CPUCL0_BOOST 0x2010 +#define CLK_CON_GAT_CLKCMU_CPUCL1_BOOST 0x2014 +#define CLK_CON_GAT_CLKCMU_CPUCL2_BOOST 0x2018 +#define CLK_CON_GAT_CLKCMU_MIF_BOOST 0x201c +#define CLK_CON_GAT_CLKCMU_MIF_SWITCH 0x2020 +#define CLK_CON_GAT_GATE_CLKCMU_BO_BUS 0x2024 +#define CLK_CON_GAT_GATE_CLKCMU_BUS0_BUS 0x2028 +#define CLK_CON_GAT_GATE_CLKCMU_BUS1_BUS 0x202c +#define CLK_CON_GAT_GATE_CLKCMU_BUS2_BUS 0x2030 +#define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0 0x2034 +#define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1 0x2038 +#define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2 0x203c +#define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3 0x2040 +#define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK4 0x2044 +#define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK5 0x2048 +#define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK6 0x204c +#define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK7 0x2050 +#define CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST 0x2054 +#define CLK_CON_GAT_GATE_CLKCMU_CORE_BUS 0x2058 +#define CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_BUS 0x205c +#define CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH 0x2060 +#define CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH 0x2064 +#define CLK_CON_GAT_GATE_CLKCMU_CPUCL2_SWITCH 0x2068 +#define CLK_CON_GAT_GATE_CLKCMU_CSIS_BUS 0x206c +#define CLK_CON_GAT_GATE_CLKCMU_DISP_BUS 0x2070 +#define CLK_CON_GAT_GATE_CLKCMU_DNS_BUS 0x2074 +#define CLK_CON_GAT_GATE_CLKCMU_DPU_BUS 0x2078 +#define CLK_CON_GAT_GATE_CLKCMU_EH_BUS 0x207c +#define CLK_CON_GAT_GATE_CLKCMU_G2D_G2D 0x2080 +#define CLK_CON_GAT_GATE_CLKCMU_G2D_MSCL 0x2084 +#define CLK_CON_GAT_GATE_CLKCMU_G3AA_G3AA 0x2088 +#define CLK_CON_GAT_GATE_CLKCMU_G3D_BUSD 0x208c +#define CLK_CON_GAT_GATE_CLKCMU_G3D_GLB 0x2090 +#define CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH 0x2094 +#define CLK_CON_GAT_GATE_CLKCMU_GDC_GDC0 0x2098 +#define CLK_CON_GAT_GATE_CLKCMU_GDC_GDC1 0x209c +#define CLK_CON_GAT_GATE_CLKCMU_GDC_SCSC 0x20a0 +#define CLK_CON_GAT_GATE_CLKCMU_HPM 0x20a4 +#define CLK_CON_GAT_GATE_CLKCMU_HSI0_BUS 0x20a8 +#define CLK_CON_GAT_GATE_CLKCMU_HSI0_DPGTC 0x20ac +#define CLK_CON_GAT_GATE_CLKCMU_HSI0_USB31DRD 0x20b0 +#define CLK_CON_GAT_GATE_CLKCMU_HSI0_USBDPDBG 0x20b4 +#define CLK_CON_GAT_GATE_CLKCMU_HSI1_BUS 0x20b8 +#define CLK_CON_GAT_GATE_CLKCMU_HSI1_PCIE 0x20bc +#define CLK_CON_GAT_GATE_CLKCMU_HSI2_BUS 0x20c0 +#define CLK_CON_GAT_GATE_CLKCMU_HSI2_MMCCARD 0x20c4 +#define CLK_CON_GAT_GATE_CLKCMU_HSI2_PCIE 0x20c8 +#define CLK_CON_GAT_GATE_CLKCMU_HSI2_UFS_EMBD 0x20cc +#define CLK_CON_GAT_GATE_CLKCMU_IPP_BUS 0x20d0 +#define CLK_CON_GAT_GATE_CLKCMU_ITP_BUS 0x20d4 +#define CLK_CON_GAT_GATE_CLKCMU_MCSC_ITSC 0x20d8 +#define CLK_CON_GAT_GATE_CLKCMU_MCSC_MCSC 0x20dc +#define CLK_CON_GAT_GATE_CLKCMU_MFC_MFC 0x20e0 +#define CLK_CON_GAT_GATE_CLKCMU_MIF_BUSP 0x20e4 +#define CLK_CON_GAT_GATE_CLKCMU_MISC_BUS 0x20e8 +#define CLK_CON_GAT_GATE_CLKCMU_MISC_SSS 0x20ec +#define CLK_CON_GAT_GATE_CLKCMU_PDP_BUS 0x20f0 +#define CLK_CON_GAT_GATE_CLKCMU_PDP_VRA 0x20f4 +#define CLK_CON_GAT_GATE_CLKCMU_PERIC0_BUS 0x20f8 +#define CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP 0x20fc +#define CLK_CON_GAT_GATE_CLKCMU_PERIC1_BUS 0x2100 +#define CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP 0x2104 +#define CLK_CON_GAT_GATE_CLKCMU_TNR_BUS 0x2108 +#define CLK_CON_GAT_GATE_CLKCMU_TOP_CMUREF 0x210c +#define CLK_CON_GAT_GATE_CLKCMU_TPU_BUS 0x2110 +#define CLK_CON_GAT_GATE_CLKCMU_TPU_TPU 0x2114 +#define CLK_CON_GAT_GATE_CLKCMU_TPU_TPUCTL 0x2118 +#define CLK_CON_GAT_GATE_CLKCMU_TPU_UART 0x211c +#define DMYQCH_CON_CMU_TOP_CMUREF_QCH 0x3000 +#define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK0 0x3004 +#define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK1 0x3008 +#define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK2 0x300c +#define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK3 0x3010 +#define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK4 0x3014 +#define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK5 0x3018 +#define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK6 0x301c +#define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK7 0x3020 +#define DMYQCH_CON_OTP_QCH 0x3024 +#define QUEUE_CTRL_REG_BLK_CMU_CMU_TOP 0x3c00 +#define QUEUE_ENTRY0_BLK_CMU_CMU_TOP 0x3c10 +#define QUEUE_ENTRY1_BLK_CMU_CMU_TOP 0x3c14 +#define QUEUE_ENTRY2_BLK_CMU_CMU_TOP 0x3c18 +#define QUEUE_ENTRY3_BLK_CMU_CMU_TOP 0x3c1c +#define QUEUE_ENTRY4_BLK_CMU_CMU_TOP 0x3c20 +#define QUEUE_ENTRY5_BLK_CMU_CMU_TOP 0x3c24 +#define QUEUE_ENTRY6_BLK_CMU_CMU_TOP 0x3c28 +#define QUEUE_ENTRY7_BLK_CMU_CMU_TOP 0x3c2c +#define MIFMIRROR_QUEUE_CTRL_REG 0x3e00 +#define MIFMIRROR_QUEUE_ENTRY0 0x3e10 +#define MIFMIRROR_QUEUE_ENTRY1 0x3e14 +#define MIFMIRROR_QUEUE_ENTRY2 0x3e18 +#define MIFMIRROR_QUEUE_ENTRY3 0x3e1c +#define MIFMIRROR_QUEUE_ENTRY4 0x3e20 +#define MIFMIRROR_QUEUE_ENTRY5 0x3e24 +#define MIFMIRROR_QUEUE_ENTRY6 0x3e28 +#define MIFMIRROR_QUEUE_ENTRY7 0x3e2c +#define MIFMIRROR_QUEUE_BUSY 0x3e30 +#define GENERALIO_ACD_CHANNEL_0 0x3f00 +#define GENERALIO_ACD_CHANNEL_1 0x3f04 +#define GENERALIO_ACD_CHANNEL_2 0x3f08 +#define GENERALIO_ACD_CHANNEL_3 0x3f0c +#define GENERALIO_ACD_MASK 0x3f14 + +static const unsigned long cmu_top_clk_regs[] __initconst = { + PLL_LOCKTIME_PLL_SHARED0, + PLL_LOCKTIME_PLL_SHARED1, + PLL_LOCKTIME_PLL_SHARED2, + PLL_LOCKTIME_PLL_SHARED3, + PLL_LOCKTIME_PLL_SPARE, + PLL_CON0_PLL_SHARED0, + PLL_CON1_PLL_SHARED0, + PLL_CON2_PLL_SHARED0, + PLL_CON3_PLL_SHARED0, + PLL_CON4_PLL_SHARED0, + PLL_CON0_PLL_SHARED1, + PLL_CON1_PLL_SHARED1, + PLL_CON2_PLL_SHARED1, + PLL_CON3_PLL_SHARED1, + PLL_CON4_PLL_SHARED1, + PLL_CON0_PLL_SHARED2, + PLL_CON1_PLL_SHARED2, + PLL_CON2_PLL_SHARED2, + PLL_CON3_PLL_SHARED2, + PLL_CON4_PLL_SHARED2, + PLL_CON0_PLL_SHARED3, + PLL_CON1_PLL_SHARED3, + PLL_CON2_PLL_SHARED3, + PLL_CON3_PLL_SHARED3, + PLL_CON4_PLL_SHARED3, + PLL_CON0_PLL_SPARE, + PLL_CON1_PLL_SPARE, + PLL_CON2_PLL_SPARE, + PLL_CON3_PLL_SPARE, + PLL_CON4_PLL_SPARE, + CMU_CMU_TOP_CONTROLLER_OPTION, + CLKOUT_CON_BLK_CMU_CMU_TOP_CLKOUT0, + CMU_HCHGEN_CLKMUX_CMU_BOOST, + CMU_HCHGEN_CLKMUX_TOP_BOOST, + CMU_HCHGEN_CLKMUX, + POWER_FAIL_DETECT_PLL, + EARLY_WAKEUP_FORCED_0_ENABLE, + EARLY_WAKEUP_FORCED_1_ENABLE, + EARLY_WAKEUP_APM_CTRL, + EARLY_WAKEUP_CLUSTER0_CTRL, + EARLY_WAKEUP_DPU_CTRL, + EARLY_WAKEUP_CSIS_CTRL, + EARLY_WAKEUP_APM_DEST, + EARLY_WAKEUP_CLUSTER0_DEST, + EARLY_WAKEUP_DPU_DEST, + EARLY_WAKEUP_CSIS_DEST, + EARLY_WAKEUP_SW_TRIG_APM, + EARLY_WAKEUP_SW_TRIG_APM_SET, + EARLY_WAKEUP_SW_TRIG_APM_CLEAR, + EARLY_WAKEUP_SW_TRIG_CLUSTER0, + EARLY_WAKEUP_SW_TRIG_CLUSTER0_SET, + EARLY_WAKEUP_SW_TRIG_CLUSTER0_CLEAR, + EARLY_WAKEUP_SW_TRIG_DPU, + EARLY_WAKEUP_SW_TRIG_DPU_SET, + EARLY_WAKEUP_SW_TRIG_DPU_CLEAR, + EARLY_WAKEUP_SW_TRIG_CSIS, + EARLY_WAKEUP_SW_TRIG_CSIS_SET, + EARLY_WAKEUP_SW_TRIG_CSIS_CLEAR, + CLK_CON_MUX_MUX_CLKCMU_BO_BUS, + CLK_CON_MUX_MUX_CLKCMU_BUS0_BUS, + CLK_CON_MUX_MUX_CLKCMU_BUS1_BUS, + CLK_CON_MUX_MUX_CLKCMU_BUS2_BUS, + CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0, + CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1, + CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2, + CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3, + CLK_CON_MUX_MUX_CLKCMU_CIS_CLK4, + CLK_CON_MUX_MUX_CLKCMU_CIS_CLK5, + CLK_CON_MUX_MUX_CLKCMU_CIS_CLK6, + CLK_CON_MUX_MUX_CLKCMU_CIS_CLK7, + CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST, + CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_OPTION1, + CLK_CON_MUX_MUX_CLKCMU_CORE_BUS, + CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG, + CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH, + CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH, + CLK_CON_MUX_MUX_CLKCMU_CPUCL2_SWITCH, + CLK_CON_MUX_MUX_CLKCMU_CSIS_BUS, + CLK_CON_MUX_MUX_CLKCMU_DISP_BUS, + CLK_CON_MUX_MUX_CLKCMU_DNS_BUS, + CLK_CON_MUX_MUX_CLKCMU_DPU_BUS, + CLK_CON_MUX_MUX_CLKCMU_EH_BUS, + CLK_CON_MUX_MUX_CLKCMU_G2D_G2D, + CLK_CON_MUX_MUX_CLKCMU_G2D_MSCL, + CLK_CON_MUX_MUX_CLKCMU_G3AA_G3AA, + CLK_CON_MUX_MUX_CLKCMU_G3D_BUSD, + CLK_CON_MUX_MUX_CLKCMU_G3D_GLB, + CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH, + CLK_CON_MUX_MUX_CLKCMU_GDC_GDC0, + CLK_CON_MUX_MUX_CLKCMU_GDC_GDC1, + CLK_CON_MUX_MUX_CLKCMU_GDC_SCSC, + CLK_CON_MUX_MUX_CLKCMU_HPM, + CLK_CON_MUX_MUX_CLKCMU_HSI0_BUS, + CLK_CON_MUX_MUX_CLKCMU_HSI0_DPGTC, + CLK_CON_MUX_MUX_CLKCMU_HSI0_USB31DRD, + CLK_CON_MUX_MUX_CLKCMU_HSI0_USBDPDBG, + CLK_CON_MUX_MUX_CLKCMU_HSI1_BUS, + CLK_CON_MUX_MUX_CLKCMU_HSI1_PCIE, + CLK_CON_MUX_MUX_CLKCMU_HSI2_BUS, + CLK_CON_MUX_MUX_CLKCMU_HSI2_MMC_CARD, + CLK_CON_MUX_MUX_CLKCMU_HSI2_PCIE, + CLK_CON_MUX_MUX_CLKCMU_HSI2_UFS_EMBD, + CLK_CON_MUX_MUX_CLKCMU_IPP_BUS, + CLK_CON_MUX_MUX_CLKCMU_ITP_BUS, + CLK_CON_MUX_MUX_CLKCMU_MCSC_ITSC, + CLK_CON_MUX_MUX_CLKCMU_MCSC_MCSC, + CLK_CON_MUX_MUX_CLKCMU_MFC_MFC, + CLK_CON_MUX_MUX_CLKCMU_MIF_BUSP, + CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH, + CLK_CON_MUX_MUX_CLKCMU_MISC_BUS, + CLK_CON_MUX_MUX_CLKCMU_MISC_SSS, + CLK_CON_MUX_MUX_CLKCMU_PDP_BUS, + CLK_CON_MUX_MUX_CLKCMU_PDP_VRA, + CLK_CON_MUX_MUX_CLKCMU_PERIC0_BUS, + CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP, + CLK_CON_MUX_MUX_CLKCMU_PERIC1_BUS, + CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP, + CLK_CON_MUX_MUX_CLKCMU_TNR_BUS, + CLK_CON_MUX_MUX_CLKCMU_TOP_BOOST_OPTION1, + CLK_CON_MUX_MUX_CLKCMU_TOP_CMUREF, + CLK_CON_MUX_MUX_CLKCMU_TPU_BUS, + CLK_CON_MUX_MUX_CLKCMU_TPU_TPU, + CLK_CON_MUX_MUX_CLKCMU_TPU_TPUCTL, + CLK_CON_MUX_MUX_CLKCMU_TPU_UART, + CLK_CON_MUX_MUX_CMU_CMUREF, + CLK_CON_DIV_CLKCMU_BO_BUS, + CLK_CON_DIV_CLKCMU_BUS0_BUS, + CLK_CON_DIV_CLKCMU_BUS1_BUS, + CLK_CON_DIV_CLKCMU_BUS2_BUS, + CLK_CON_DIV_CLKCMU_CIS_CLK0, + CLK_CON_DIV_CLKCMU_CIS_CLK1, + CLK_CON_DIV_CLKCMU_CIS_CLK2, + CLK_CON_DIV_CLKCMU_CIS_CLK3, + CLK_CON_DIV_CLKCMU_CIS_CLK4, + CLK_CON_DIV_CLKCMU_CIS_CLK5, + CLK_CON_DIV_CLKCMU_CIS_CLK6, + CLK_CON_DIV_CLKCMU_CIS_CLK7, + CLK_CON_DIV_CLKCMU_CORE_BUS, + CLK_CON_DIV_CLKCMU_CPUCL0_DBG, + CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH, + CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH, + CLK_CON_DIV_CLKCMU_CPUCL2_SWITCH, + CLK_CON_DIV_CLKCMU_CSIS_BUS, + CLK_CON_DIV_CLKCMU_DISP_BUS, + CLK_CON_DIV_CLKCMU_DNS_BUS, + CLK_CON_DIV_CLKCMU_DPU_BUS, + CLK_CON_DIV_CLKCMU_EH_BUS, + CLK_CON_DIV_CLKCMU_G2D_G2D, + CLK_CON_DIV_CLKCMU_G2D_MSCL, + CLK_CON_DIV_CLKCMU_G3AA_G3AA, + CLK_CON_DIV_CLKCMU_G3D_BUSD, + CLK_CON_DIV_CLKCMU_G3D_GLB, + CLK_CON_DIV_CLKCMU_G3D_SWITCH, + CLK_CON_DIV_CLKCMU_GDC_GDC0, + CLK_CON_DIV_CLKCMU_GDC_GDC1, + CLK_CON_DIV_CLKCMU_GDC_SCSC, + CLK_CON_DIV_CLKCMU_HPM, + CLK_CON_DIV_CLKCMU_HSI0_BUS, + CLK_CON_DIV_CLKCMU_HSI0_DPGTC, + CLK_CON_DIV_CLKCMU_HSI0_USB31DRD, + CLK_CON_DIV_CLKCMU_HSI0_USBDPDBG, + CLK_CON_DIV_CLKCMU_HSI1_BUS, + CLK_CON_DIV_CLKCMU_HSI1_PCIE, + CLK_CON_DIV_CLKCMU_HSI2_BUS, + CLK_CON_DIV_CLKCMU_HSI2_MMC_CARD, + CLK_CON_DIV_CLKCMU_HSI2_PCIE, + CLK_CON_DIV_CLKCMU_HSI2_UFS_EMBD, + CLK_CON_DIV_CLKCMU_IPP_BUS, + CLK_CON_DIV_CLKCMU_ITP_BUS, + CLK_CON_DIV_CLKCMU_MCSC_ITSC, + CLK_CON_DIV_CLKCMU_MCSC_MCSC, + CLK_CON_DIV_CLKCMU_MFC_MFC, + CLK_CON_DIV_CLKCMU_MIF_BUSP, + CLK_CON_DIV_CLKCMU_MISC_BUS, + CLK_CON_DIV_CLKCMU_MISC_SSS, + CLK_CON_DIV_CLKCMU_OTP, + CLK_CON_DIV_CLKCMU_PDP_BUS, + CLK_CON_DIV_CLKCMU_PDP_VRA, + CLK_CON_DIV_CLKCMU_PERIC0_BUS, + CLK_CON_DIV_CLKCMU_PERIC0_IP, + CLK_CON_DIV_CLKCMU_PERIC1_BUS, + CLK_CON_DIV_CLKCMU_PERIC1_IP, + CLK_CON_DIV_CLKCMU_TNR_BUS, + CLK_CON_DIV_CLKCMU_TPU_BUS, + CLK_CON_DIV_CLKCMU_TPU_TPU, + CLK_CON_DIV_CLKCMU_TPU_TPUCTL, + CLK_CON_DIV_CLKCMU_TPU_UART, + CLK_CON_DIV_DIV_CLKCMU_CMU_BOOST, + CLK_CON_DIV_DIV_CLK_CMU_CMUREF, + CLK_CON_DIV_PLL_SHARED0_DIV2, + CLK_CON_DIV_PLL_SHARED0_DIV3, + CLK_CON_DIV_PLL_SHARED0_DIV4, + CLK_CON_DIV_PLL_SHARED0_DIV5, + CLK_CON_DIV_PLL_SHARED1_DIV2, + CLK_CON_DIV_PLL_SHARED1_DIV3, + CLK_CON_DIV_PLL_SHARED1_DIV4, + CLK_CON_DIV_PLL_SHARED2_DIV2, + CLK_CON_DIV_PLL_SHARED3_DIV2, + CLK_CON_GAT_CLKCMU_BUS0_BOOST, + CLK_CON_GAT_CLKCMU_BUS1_BOOST, + CLK_CON_GAT_CLKCMU_BUS2_BOOST, + CLK_CON_GAT_CLKCMU_CORE_BOOST, + CLK_CON_GAT_CLKCMU_CPUCL0_BOOST, + CLK_CON_GAT_CLKCMU_CPUCL1_BOOST, + CLK_CON_GAT_CLKCMU_CPUCL2_BOOST, + CLK_CON_GAT_CLKCMU_MIF_BOOST, + CLK_CON_GAT_CLKCMU_MIF_SWITCH, + CLK_CON_GAT_GATE_CLKCMU_BO_BUS, + CLK_CON_GAT_GATE_CLKCMU_BUS0_BUS, + CLK_CON_GAT_GATE_CLKCMU_BUS1_BUS, + CLK_CON_GAT_GATE_CLKCMU_BUS2_BUS, + CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0, + CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1, + CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2, + CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3, + CLK_CON_GAT_GATE_CLKCMU_CIS_CLK4, + CLK_CON_GAT_GATE_CLKCMU_CIS_CLK5, + CLK_CON_GAT_GATE_CLKCMU_CIS_CLK6, + CLK_CON_GAT_GATE_CLKCMU_CIS_CLK7, + CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST, + CLK_CON_GAT_GATE_CLKCMU_CORE_BUS, + CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_BUS, + CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH, + CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH, + CLK_CON_GAT_GATE_CLKCMU_CPUCL2_SWITCH, + CLK_CON_GAT_GATE_CLKCMU_CSIS_BUS, + CLK_CON_GAT_GATE_CLKCMU_DISP_BUS, + CLK_CON_GAT_GATE_CLKCMU_DNS_BUS, + CLK_CON_GAT_GATE_CLKCMU_DPU_BUS, + CLK_CON_GAT_GATE_CLKCMU_EH_BUS, + CLK_CON_GAT_GATE_CLKCMU_G2D_G2D, + CLK_CON_GAT_GATE_CLKCMU_G2D_MSCL, + CLK_CON_GAT_GATE_CLKCMU_G3AA_G3AA, + CLK_CON_GAT_GATE_CLKCMU_G3D_BUSD, + CLK_CON_GAT_GATE_CLKCMU_G3D_GLB, + CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH, + CLK_CON_GAT_GATE_CLKCMU_GDC_GDC0, + CLK_CON_GAT_GATE_CLKCMU_GDC_GDC1, + CLK_CON_GAT_GATE_CLKCMU_GDC_SCSC, + CLK_CON_GAT_GATE_CLKCMU_HPM, + CLK_CON_GAT_GATE_CLKCMU_HSI0_BUS, + CLK_CON_GAT_GATE_CLKCMU_HSI0_DPGTC, + CLK_CON_GAT_GATE_CLKCMU_HSI0_USB31DRD, + CLK_CON_GAT_GATE_CLKCMU_HSI0_USBDPDBG, + CLK_CON_GAT_GATE_CLKCMU_HSI1_BUS, + CLK_CON_GAT_GATE_CLKCMU_HSI1_PCIE, + CLK_CON_GAT_GATE_CLKCMU_HSI2_BUS, + CLK_CON_GAT_GATE_CLKCMU_HSI2_MMCCARD, + CLK_CON_GAT_GATE_CLKCMU_HSI2_PCIE, + CLK_CON_GAT_GATE_CLKCMU_HSI2_UFS_EMBD, + CLK_CON_GAT_GATE_CLKCMU_IPP_BUS, + CLK_CON_GAT_GATE_CLKCMU_ITP_BUS, + CLK_CON_GAT_GATE_CLKCMU_MCSC_ITSC, + CLK_CON_GAT_GATE_CLKCMU_MCSC_MCSC, + CLK_CON_GAT_GATE_CLKCMU_MFC_MFC, + CLK_CON_GAT_GATE_CLKCMU_MIF_BUSP, + CLK_CON_GAT_GATE_CLKCMU_MISC_BUS, + CLK_CON_GAT_GATE_CLKCMU_MISC_SSS, + CLK_CON_GAT_GATE_CLKCMU_PDP_BUS, + CLK_CON_GAT_GATE_CLKCMU_PDP_VRA, + CLK_CON_GAT_GATE_CLKCMU_PERIC0_BUS, + CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP, + CLK_CON_GAT_GATE_CLKCMU_PERIC1_BUS, + CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP, + CLK_CON_GAT_GATE_CLKCMU_TNR_BUS, + CLK_CON_GAT_GATE_CLKCMU_TOP_CMUREF, + CLK_CON_GAT_GATE_CLKCMU_TPU_BUS, + CLK_CON_GAT_GATE_CLKCMU_TPU_TPU, + CLK_CON_GAT_GATE_CLKCMU_TPU_TPUCTL, + CLK_CON_GAT_GATE_CLKCMU_TPU_UART, + DMYQCH_CON_CMU_TOP_CMUREF_QCH, + DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK0, + DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK1, + DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK2, + DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK3, + DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK4, + DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK5, + DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK6, + DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK7, + DMYQCH_CON_OTP_QCH, + QUEUE_CTRL_REG_BLK_CMU_CMU_TOP, + QUEUE_ENTRY0_BLK_CMU_CMU_TOP, + QUEUE_ENTRY1_BLK_CMU_CMU_TOP, + QUEUE_ENTRY2_BLK_CMU_CMU_TOP, + QUEUE_ENTRY3_BLK_CMU_CMU_TOP, + QUEUE_ENTRY4_BLK_CMU_CMU_TOP, + QUEUE_ENTRY5_BLK_CMU_CMU_TOP, + QUEUE_ENTRY6_BLK_CMU_CMU_TOP, + QUEUE_ENTRY7_BLK_CMU_CMU_TOP, + MIFMIRROR_QUEUE_CTRL_REG, + MIFMIRROR_QUEUE_ENTRY0, + MIFMIRROR_QUEUE_ENTRY1, + MIFMIRROR_QUEUE_ENTRY2, + MIFMIRROR_QUEUE_ENTRY3, + MIFMIRROR_QUEUE_ENTRY4, + MIFMIRROR_QUEUE_ENTRY5, + MIFMIRROR_QUEUE_ENTRY6, + MIFMIRROR_QUEUE_ENTRY7, + MIFMIRROR_QUEUE_BUSY, + GENERALIO_ACD_CHANNEL_0, + GENERALIO_ACD_CHANNEL_1, + GENERALIO_ACD_CHANNEL_2, + GENERALIO_ACD_CHANNEL_3, + GENERALIO_ACD_MASK, +}; + +static const struct samsung_pll_clock cmu_top_pll_clks[] __initconst = { + /* CMU_TOP_PURECLKCOMP */ + PLL(pll_0517x, CLK_FOUT_SHARED0_PLL, "fout_shared0_pll", "oscclk", + PLL_LOCKTIME_PLL_SHARED0, PLL_CON3_PLL_SHARED0, + NULL), + PLL(pll_0517x, CLK_FOUT_SHARED1_PLL, "fout_shared1_pll", "oscclk", + PLL_LOCKTIME_PLL_SHARED1, PLL_CON3_PLL_SHARED1, + NULL), + PLL(pll_0518x, CLK_FOUT_SHARED2_PLL, "fout_shared2_pll", "oscclk", + PLL_LOCKTIME_PLL_SHARED2, PLL_CON3_PLL_SHARED2, + NULL), + PLL(pll_0518x, CLK_FOUT_SHARED3_PLL, "fout_shared3_pll", "oscclk", + PLL_LOCKTIME_PLL_SHARED3, PLL_CON3_PLL_SHARED3, + NULL), + PLL(pll_0518x, CLK_FOUT_SPARE_PLL, "fout_spare_pll", "oscclk", + PLL_LOCKTIME_PLL_SPARE, PLL_CON3_PLL_SPARE, + NULL), +}; + +/* List of parent clocks for Muxes in CMU_TOP */ +PNAME(mout_pll_shared0_p) = { "oscclk", "fout_shared0_pll" }; +PNAME(mout_pll_shared1_p) = { "oscclk", "fout_shared1_pll" }; +PNAME(mout_pll_shared2_p) = { "oscclk", "fout_shared2_pll" }; +PNAME(mout_pll_shared3_p) = { "oscclk", "fout_shared3_pll" }; +PNAME(mout_pll_spare_p) = { "oscclk", "fout_spare_pll" }; +PNAME(mout_cmu_bo_bus_p) = { "fout_shared2_pll", "dout_cmu_shared0_div3", + "fout_shared3_pll", "dout_cmu_shared1_div3", + "dout_cmu_shared0_div4", + "dout_cmu_shared1_div4", + "fout_spare_pll", "oscclk" }; +PNAME(mout_cmu_bus0_bus_p) = { "dout_cmu_shared0_div4", + "dout_cmu_shared1_div4", + "dout_cmu_shared2_div2", + "dout_cmu_shared3_div2", + "fout_spare_pll", "oscclk", + "oscclk", "oscclk" }; +PNAME(mout_cmu_bus1_bus_p) = { "dout_cmu_shared0_div3", "fout_shared3_pll", + "dout_cmu_shared1_div3", + "dout_cmu_shared0_div4", + "dout_cmu_shared1_div4", + "dout_cmu_shared2_div2", + "fout_spare_pll", "oscclk" }; +PNAME(mout_cmu_bus2_bus_p) = { "dout_cmu_shared0_div2", + "dout_cmu_shared1_div2", + "fout_shared2_pll", "fout_shared3_pll", + "dout_cmu_shared0_div3", + "dout_cmu_shared1_div3", + "dout_cmu_shared0_div5", "fout_spare_pll" }; +PNAME(mout_cmu_cis_clk0_7_p) = { "oscclk", "dout_cmu_shared0_div3", + "dout_cmu_shared1_div3", + "dout_cmu_shared2_div2", + "dout_cmu_shared3_div2", "fout_spare_pll", + "oscclk", "oscclk" }; +PNAME(mout_cmu_cmu_boost_p) = { "dout_cmu_shared0_div4", + "dout_cmu_shared1_div4", + "dout_cmu_shared2_div2", + "dout_cmu_shared3_div2" }; +PNAME(mout_cmu_cmu_boost_option1_p) = { "dout_cmu_cmu_boost", + "gout_cmu_boost_option1" }; +PNAME(mout_cmu_core_bus_p) = { "dout_cmu_shared0_div2", + "dout_cmu_shared1_div2", + "fout_shared2_pll", "fout_shared3_pll", + "dout_cmu_shared0_div3", + "dout_cmu_shared1_div3", + "dout_cmu_shared0_div5", "fout_spare_pll" }; +PNAME(mout_cmu_cpucl0_dbg_p) = { "fout_shared2_pll", "fout_shared3_pll", + "dout_cmu_shared0_div4", + "dout_cmu_shared1_div4", + "dout_cmu_shared2_div2", "fout_spare_pll", + "oscclk", "oscclk" }; +PNAME(mout_cmu_cpucl0_switch_p) = { "fout_shared1_pll", "dout_cmu_shared0_div2", + "dout_cmu_shared1_div2", "fout_shared2_pll", + "fout_shared3_pll", "dout_cmu_shared0_div3", + "dout_cmu_shared1_div3", "fout_spare_pll" }; +PNAME(mout_cmu_cpucl1_switch_p) = { "fout_shared1_pll", "dout_cmu_shared0_div2", + "dout_cmu_shared1_div2", "fout_shared2_pll", + "fout_shared3_pll", "dout_cmu_shared0_div3", + "dout_cmu_shared1_div3", "fout_spare_pll" }; +PNAME(mout_cmu_cpucl2_switch_p) = { "fout_shared1_pll", "dout_cmu_shared0_div2", + "dout_cmu_shared1_div2", "fout_shared2_pll", + "fout_shared3_pll", "dout_cmu_shared0_div3", + "dout_cmu_shared1_div3", "fout_spare_pll" }; +PNAME(mout_cmu_csis_bus_p) = { "dout_cmu_shared0_div3", "fout_shared3_pll", + "dout_cmu_shared1_div3", + "dout_cmu_shared0_div4", + "dout_cmu_shared1_div4", + "dout_cmu_shared2_div2", + "fout_spare_pll", "oscclk" }; +PNAME(mout_cmu_disp_bus_p) = { "dout_cmu_shared0_div3", "fout_shared3_pll", + "dout_cmu_shared1_div3", + "dout_cmu_shared0_div4", + "dout_cmu_shared1_div4", + "dout_cmu_shared2_div2", + "fout_spare_pll", "oscclk" }; +PNAME(mout_cmu_dns_bus_p) = { "dout_cmu_shared0_div3", "fout_shared3_pll", + "dout_cmu_shared1_div3", + "dout_cmu_shared0_div4", + "dout_cmu_shared1_div4", + "dout_cmu_shared2_div2", + "fout_spare_pll", "oscclk" }; +PNAME(mout_cmu_dpu_p) = { "dout_cmu_shared0_div3", + "fout_shared3_pll", + "dout_cmu_shared1_div3", + "dout_cmu_shared0_div4", + "dout_cmu_shared1_div4", + "dout_cmu_shared2_div2", + "fout_spare_pll", "oscclk" }; +PNAME(mout_cmu_eh_bus_p) = { "dout_cmu_shared0_div2", + "dout_cmu_shared1_div2", + "fout_shared2_pll", "fout_shared3_pll", + "dout_cmu_shared0_div3", + "dout_cmu_shared1_div3", + "dout_cmu_shared0_div5", "fout_spare_pll" }; +PNAME(mout_cmu_g2d_g2d_p) = { "dout_cmu_shared0_div3", "fout_shared3_pll", + "dout_cmu_shared1_div3", + "dout_cmu_shared0_div4", + "dout_cmu_shared1_div4", + "dout_cmu_shared2_div2", + "fout_spare_pll", "oscclk" }; +PNAME(mout_cmu_g2d_mscl_p) = { "dout_cmu_shared0_div4", + "dout_cmu_shared1_div4", + "dout_cmu_shared2_div2", + "dout_cmu_shared3_div2", + "fout_spare_pll", "oscclk", + "oscclk", "oscclk" }; +PNAME(mout_cmu_g3aa_g3aa_p) = { "dout_cmu_shared0_div3", "fout_shared3_pll", + "dout_cmu_shared1_div3", + "dout_cmu_shared0_div4", + "dout_cmu_shared1_div4", + "dout_cmu_shared2_div2", + "fout_spare_pll", "oscclk" }; +PNAME(mout_cmu_g3d_busd_p) = { "dout_cmu_shared0_div2", + "dout_cmu_shared1_div2", + "fout_shared2_pll", "fout_shared3_pll", + "dout_cmu_shared0_div3", + "dout_cmu_shared1_div3", + "dout_cmu_shared0_div4", "fout_spare_pll" }; +PNAME(mout_cmu_g3d_glb_p) = { "dout_cmu_shared0_div2", + "dout_cmu_shared1_div2", + "fout_shared2_pll", "fout_shared3_pll", + "dout_cmu_shared0_div3", + "dout_cmu_shared1_div3", + "dout_cmu_shared0_div4", "fout_spare_pll" }; +PNAME(mout_cmu_g3d_switch_p) = { "fout_shared2_pll", "dout_cmu_shared0_div3", + "fout_shared3_pll", "dout_cmu_shared1_div3", + "dout_cmu_shared0_div4", + "dout_cmu_shared1_div4", + "fout_spare_pll", "fout_spare_pll"}; +PNAME(mout_cmu_gdc_gdc0_p) = { "dout_cmu_shared0_div3", "fout_shared3_pll", + "dout_cmu_shared1_div3", + "dout_cmu_shared0_div4", + "dout_cmu_shared1_div4", + "dout_cmu_shared2_div2", + "fout_spare_pll", "oscclk" }; +PNAME(mout_cmu_gdc_gdc1_p) = { "dout_cmu_shared0_div3", "fout_shared3_pll", + "dout_cmu_shared1_div3", + "dout_cmu_shared0_div4", + "dout_cmu_shared1_div4", + "dout_cmu_shared2_div2", + "fout_spare_pll", "oscclk" }; +PNAME(mout_cmu_gdc_scsc_p) = { "dout_cmu_shared0_div3", "fout_shared3_pll", + "dout_cmu_shared1_div3", + "dout_cmu_shared0_div4", + "dout_cmu_shared1_div4", + "dout_cmu_shared2_div2", + "fout_spare_pll", "oscclk" }; +PNAME(mout_cmu_hpm_p) = { "oscclk", "dout_cmu_shared1_div3", + "dout_cmu_shared0_div4", + "dout_cmu_shared2_div2" }; +PNAME(mout_cmu_hsi0_bus_p) = { "dout_cmu_shared0_div4", + "dout_cmu_shared1_div4", + "dout_cmu_shared2_div2", + "dout_cmu_shared3_div2", + "fout_spare_pll", "oscclk", + "oscclk", "oscclk" }; +PNAME(mout_cmu_hsi0_dpgtc_p) = { "oscclk", "dout_cmu_shared0_div4", + "dout_cmu_shared2_div2", "fout_spare_pll" }; +PNAME(mout_cmu_hsi0_usb31drd_p) = { "oscclk", "dout_cmu_shared2_div2" }; +PNAME(mout_cmu_hsi0_usbdpdbg_p) = { "oscclk", "dout_cmu_shared2_div2" }; +PNAME(mout_cmu_hsi1_bus_p) = { "dout_cmu_shared0_div4", + "dout_cmu_shared1_div4", + "dout_cmu_shared2_div2", + "dout_cmu_shared3_div2", + "fout_spare_pll" }; +PNAME(mout_cmu_hsi1_pcie_p) = { "oscclk", "dout_cmu_shared2_div2" }; +PNAME(mout_cmu_hsi2_bus_p) = { "dout_cmu_shared0_div4", + "dout_cmu_shared1_div4", + "dout_cmu_shared2_div2", + "dout_cmu_shared3_div2", + "fout_spare_pll", "oscclk", + "oscclk", "oscclk" }; +PNAME(mout_cmu_hsi2_mmc_card_p) = { "fout_shared2_pll", "fout_shared3_pll", + "dout_cmu_shared0_div4", "fout_spare_pll" }; +PNAME(mout_cmu_hsi2_pcie0_p) = { "oscclk", "dout_cmu_shared2_div2" }; +PNAME(mout_cmu_hsi2_ufs_embd_p) = { "oscclk", "dout_cmu_shared0_div4", + "dout_cmu_shared2_div2", "fout_spare_pll" }; +PNAME(mout_cmu_ipp_bus_p) = { "dout_cmu_shared0_div3", "fout_shared3_pll", + "dout_cmu_shared1_div3", + "dout_cmu_shared0_div4", + "dout_cmu_shared1_div4", + "dout_cmu_shared2_div2", + "fout_spare_pll", "oscclk" }; +PNAME(mout_cmu_itp_bus_p) = { "dout_cmu_shared0_div3", "fout_shared3_pll", + "dout_cmu_shared1_div3", + "dout_cmu_shared0_div4", + "dout_cmu_shared1_div4", + "dout_cmu_shared2_div2", + "fout_spare_pll", "oscclk" }; +PNAME(mout_cmu_mcsc_itsc_p) = { "dout_cmu_shared0_div3", "fout_shared3_pll", + "dout_cmu_shared1_div3", + "dout_cmu_shared0_div4", + "dout_cmu_shared1_div4", + "dout_cmu_shared2_div2", + "fout_spare_pll", "oscclk" }; +PNAME(mout_cmu_mcsc_mcsc_p) = { "dout_cmu_shared0_div3", "fout_shared3_pll", + "dout_cmu_shared1_div3", + "dout_cmu_shared0_div4", + "dout_cmu_shared1_div4", + "dout_cmu_shared2_div2", + "fout_spare_pll", "oscclk" }; +PNAME(mout_cmu_mfc_mfc_p) = { "dout_cmu_shared0_div3", "fout_shared3_pll", + "dout_cmu_shared0_div4", + "dout_cmu_shared1_div4", + "dout_cmu_shared2_div2", "fout_spare_pll", + "oscclk", "oscclk" }; +PNAME(mout_cmu_mif_busp_p) = { "dout_cmu_shared0_div4", + "dout_cmu_shared1_div4", + "dout_cmu_shared0_div5", "fout_spare_pll" }; +PNAME(mout_cmu_mif_switch_p) = { "fout_shared0_pll", "fout_shared1_pll", + "dout_cmu_shared0_div2", + "dout_cmu_shared1_div2", + "fout_shared2_pll", "dout_cmu_shared0_div3", + "fout_shared3_pll", "fout_spare_pll" }; +PNAME(mout_cmu_misc_bus_p) = { "dout_cmu_shared0_div4", + "dout_cmu_shared2_div2", + "dout_cmu_shared3_div2", "fout_spare_pll" }; +PNAME(mout_cmu_misc_sss_p) = { "dout_cmu_shared0_div4", + "dout_cmu_shared2_div2", + "dout_cmu_shared3_div2", "fout_spare_pll" }; +PNAME(mout_cmu_pdp_bus_p) = { "dout_cmu_shared0_div3", "fout_shared3_pll", + "dout_cmu_shared1_div3", + "dout_cmu_shared0_div4", + "dout_cmu_shared1_div4", + "dout_cmu_shared2_div2", + "fout_spare_pll", "oscclk" }; +PNAME(mout_cmu_pdp_vra_p) = { "fout_shared2_pll", "dout_cmu_shared0_div3", + "fout_shared3_pll", "dout_cmu_shared1_div3", + "dout_cmu_shared0_div4", + "dout_cmu_shared1_div4", + "fout_spare_pll", "oscclk" }; +PNAME(mout_cmu_peric0_bus_p) = { "dout_cmu_shared0_div4", + "dout_cmu_shared2_div2", + "dout_cmu_shared3_div2", "fout_spare_pll" }; +PNAME(mout_cmu_peric0_ip_p) = { "dout_cmu_shared0_div4", + "dout_cmu_shared2_div2", + "dout_cmu_shared3_div2", "fout_spare_pll" }; +PNAME(mout_cmu_peric1_bus_p) = { "dout_cmu_shared0_div4", + "dout_cmu_shared2_div2", + "dout_cmu_shared3_div2", "fout_spare_pll" }; +PNAME(mout_cmu_peric1_ip_p) = { "dout_cmu_shared0_div4", + "dout_cmu_shared2_div2", + "dout_cmu_shared3_div2", "fout_spare_pll" }; +PNAME(mout_cmu_tnr_bus_p) = { "dout_cmu_shared0_div3", "fout_shared3_pll", + "dout_cmu_shared1_div3", + "dout_cmu_shared0_div4", + "dout_cmu_shared1_div4", + "dout_cmu_shared2_div2", + "fout_spare_pll", "oscclk" }; +PNAME(mout_cmu_top_boost_option1_p) = { "oscclk", + "gout_cmu_boost_option1" }; +PNAME(mout_cmu_top_cmuref_p) = { "dout_cmu_shared0_div4", + "dout_cmu_shared1_div4", + "dout_cmu_shared2_div2", + "dout_cmu_shared3_div2" }; +PNAME(mout_cmu_tpu_bus_p) = { "dout_cmu_shared0_div2", + "dout_cmu_shared1_div2", + "fout_shared2_pll", + "fout_shared3_pll", + "dout_cmu_shared0_div3", + "dout_cmu_shared1_div3", + "dout_cmu_shared0_div4", + "fout_spare_pll" }; +PNAME(mout_cmu_tpu_tpu_p) = { "dout_cmu_shared0_div2", + "dout_cmu_shared1_div2", + "fout_shared2_pll", + "fout_shared3_pll", + "dout_cmu_shared0_div3", + "dout_cmu_shared1_div3", + "dout_cmu_shared0_div4", "fout_spare_pll" }; +PNAME(mout_cmu_tpu_tpuctl_p) = { "dout_cmu_shared0_div2", + "dout_cmu_shared1_div2", + "fout_shared2_pll", "fout_shared3_pll", + "dout_cmu_shared0_div3", + "dout_cmu_shared1_div3", + "dout_cmu_shared0_div4", "fout_spare_pll" }; +PNAME(mout_cmu_tpu_uart_p) = { "dout_cmu_shared0_div4", + "dout_cmu_shared2_div2", + "dout_cmu_shared3_div2", "fout_spare_pll" }; +PNAME(mout_cmu_cmuref_p) = { "mout_cmu_top_boost_option1", + "dout_cmu_cmuref" }; + +/* + * Register name to clock name mangling strategy used in this file + * + * Replace PLL_CON0_PLL with CLK_MOUT_PLL and mout_pll + * Replace CLK_CON_MUX_MUX_CLKCMU with CLK_MOUT_CMU and mout_cmu + * Replace CLK_CON_DIV_CLKCMU with CLK_DOUT_CMU and dout_cmu + * Replace CLK_CON_DIV_DIV_CLKCMU with CLK_DOUT_CMU and dout_cmu + * Replace CLK_CON_GAT_CLKCMU with CLK_GOUT_CMU and gout_cmu + * Replace CLK_CON_GAT_GATE_CLKCMU with CLK_GOUT_CMU and gout_cmu + * + * For gates remove _UID _BLK _IPCLKPORT and _RSTNSYNC + */ + +static const struct samsung_mux_clock cmu_top_mux_clks[] __initconst = { + MUX(CLK_MOUT_PLL_SHARED0, "mout_pll_shared0", mout_pll_shared0_p, + PLL_CON0_PLL_SHARED0, 4, 1), + MUX(CLK_MOUT_PLL_SHARED1, "mout_pll_shared1", mout_pll_shared1_p, + PLL_CON0_PLL_SHARED1, 4, 1), + MUX(CLK_MOUT_PLL_SHARED2, "mout_pll_shared2", mout_pll_shared2_p, + PLL_CON0_PLL_SHARED2, 4, 1), + MUX(CLK_MOUT_PLL_SHARED3, "mout_pll_shared3", mout_pll_shared3_p, + PLL_CON0_PLL_SHARED3, 4, 1), + MUX(CLK_MOUT_PLL_SPARE, "mout_pll_spare", mout_pll_spare_p, + PLL_CON0_PLL_SPARE, 4, 1), + MUX(CLK_MOUT_CMU_BO_BUS, "mout_cmu_bo_bus", mout_cmu_bo_bus_p, + CLK_CON_MUX_MUX_CLKCMU_BO_BUS, 0, 3), + MUX(CLK_MOUT_CMU_BUS0_BUS, "mout_cmu_bus0_bus", mout_cmu_bus0_bus_p, + CLK_CON_MUX_MUX_CLKCMU_BUS0_BUS, 0, 3), + MUX(CLK_MOUT_CMU_BUS1_BUS, "mout_cmu_bus1_bus", mout_cmu_bus1_bus_p, + CLK_CON_MUX_MUX_CLKCMU_BUS1_BUS, 0, 3), + MUX(CLK_MOUT_CMU_BUS2_BUS, "mout_cmu_bus2_bus", mout_cmu_bus2_bus_p, + CLK_CON_MUX_MUX_CLKCMU_BUS2_BUS, 0, 3), + MUX(CLK_MOUT_CMU_CIS_CLK0, "mout_cmu_cis_clk0", mout_cmu_cis_clk0_7_p, + CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0, 0, 3), + MUX(CLK_MOUT_CMU_CIS_CLK1, "mout_cmu_cis_clk1", mout_cmu_cis_clk0_7_p, + CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1, 0, 3), + MUX(CLK_MOUT_CMU_CIS_CLK2, "mout_cmu_cis_clk2", mout_cmu_cis_clk0_7_p, + CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2, 0, 3), + MUX(CLK_MOUT_CMU_CIS_CLK3, "mout_cmu_cis_clk3", mout_cmu_cis_clk0_7_p, + CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3, 0, 3), + MUX(CLK_MOUT_CMU_CIS_CLK4, "mout_cmu_cis_clk4", mout_cmu_cis_clk0_7_p, + CLK_CON_MUX_MUX_CLKCMU_CIS_CLK4, 0, 3), + MUX(CLK_MOUT_CMU_CIS_CLK5, "mout_cmu_cis_clk5", mout_cmu_cis_clk0_7_p, + CLK_CON_MUX_MUX_CLKCMU_CIS_CLK5, 0, 3), + MUX(CLK_MOUT_CMU_CIS_CLK6, "mout_cmu_cis_clk6", mout_cmu_cis_clk0_7_p, + CLK_CON_MUX_MUX_CLKCMU_CIS_CLK6, 0, 3), + MUX(CLK_MOUT_CMU_CIS_CLK7, "mout_cmu_cis_clk7", mout_cmu_cis_clk0_7_p, + CLK_CON_MUX_MUX_CLKCMU_CIS_CLK7, 0, 3), + MUX(CLK_MOUT_CMU_CMU_BOOST, "mout_cmu_cmu_boost", mout_cmu_cmu_boost_p, + CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST, 0, 2), + MUX(CLK_MOUT_CMU_BOOST_OPTION1, "mout_cmu_boost_option1", + mout_cmu_cmu_boost_option1_p, + CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_OPTION1, 0, 1), + MUX(CLK_MOUT_CMU_CORE_BUS, "mout_cmu_core_bus", mout_cmu_core_bus_p, + CLK_CON_MUX_MUX_CLKCMU_CORE_BUS, 0, 3), + MUX(CLK_MOUT_CMU_CPUCL0_DBG, "mout_cmu_cpucl0_dbg", + mout_cmu_cpucl0_dbg_p, CLK_CON_DIV_CLKCMU_CPUCL0_DBG, 0, 3), + MUX(CLK_MOUT_CMU_CPUCL0_SWITCH, "mout_cmu_cpucl0_switch", + mout_cmu_cpucl0_switch_p, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH, + 0, 3), + MUX(CLK_MOUT_CMU_CPUCL1_SWITCH, "mout_cmu_cpucl1_switch", + mout_cmu_cpucl1_switch_p, CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH, + 0, 3), + MUX(CLK_MOUT_CMU_CPUCL2_SWITCH, "mout_cmu_cpucl2_switch", + mout_cmu_cpucl2_switch_p, CLK_CON_MUX_MUX_CLKCMU_CPUCL2_SWITCH, + 0, 3), + MUX(CLK_MOUT_CMU_CSIS_BUS, "mout_cmu_csis_bus", mout_cmu_csis_bus_p, + CLK_CON_MUX_MUX_CLKCMU_CSIS_BUS, 0, 3), + MUX(CLK_MOUT_CMU_DISP_BUS, "mout_cmu_disp_bus", mout_cmu_disp_bus_p, + CLK_CON_MUX_MUX_CLKCMU_DISP_BUS, 0, 3), + MUX(CLK_MOUT_CMU_DNS_BUS, "mout_cmu_dns_bus", mout_cmu_dns_bus_p, + CLK_CON_MUX_MUX_CLKCMU_DNS_BUS, 0, 3), + MUX(CLK_MOUT_CMU_DPU_BUS, "mout_cmu_dpu_bus", mout_cmu_dpu_p, + CLK_CON_MUX_MUX_CLKCMU_DPU_BUS, 0, 3), + MUX(CLK_MOUT_CMU_EH_BUS, "mout_cmu_eh_bus", mout_cmu_eh_bus_p, + CLK_CON_MUX_MUX_CLKCMU_EH_BUS, 0, 3), + MUX(CLK_MOUT_CMU_G2D_G2D, "mout_cmu_g2d_g2d", mout_cmu_g2d_g2d_p, + CLK_CON_MUX_MUX_CLKCMU_G2D_G2D, 0, 3), + MUX(CLK_MOUT_CMU_G2D_MSCL, "mout_cmu_g2d_mscl", mout_cmu_g2d_mscl_p, + CLK_CON_MUX_MUX_CLKCMU_G2D_MSCL, 0, 3), + MUX(CLK_MOUT_CMU_G3AA_G3AA, "mout_cmu_g3aa_g3aa", mout_cmu_g3aa_g3aa_p, + CLK_CON_MUX_MUX_CLKCMU_G3AA_G3AA, 0, 3), + MUX(CLK_MOUT_CMU_G3D_BUSD, "mout_cmu_g3d_busd", mout_cmu_g3d_busd_p, + CLK_CON_MUX_MUX_CLKCMU_G3D_BUSD, 0, 3), + MUX(CLK_MOUT_CMU_G3D_GLB, "mout_cmu_g3d_glb", mout_cmu_g3d_glb_p, + CLK_CON_MUX_MUX_CLKCMU_G3D_GLB, 0, 3), + MUX(CLK_MOUT_CMU_G3D_SWITCH, "mout_cmu_g3d_switch", + mout_cmu_g3d_switch_p, CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH, 0, 3), + MUX(CLK_MOUT_CMU_GDC_GDC0, "mout_cmu_gdc_gdc0", mout_cmu_gdc_gdc0_p, + CLK_CON_MUX_MUX_CLKCMU_GDC_GDC0, 0, 3), + MUX(CLK_MOUT_CMU_GDC_GDC1, "mout_cmu_gdc_gdc1", mout_cmu_gdc_gdc1_p, + CLK_CON_MUX_MUX_CLKCMU_GDC_GDC1, 0, 3), + MUX(CLK_MOUT_CMU_GDC_SCSC, "mout_cmu_gdc_scsc", mout_cmu_gdc_scsc_p, + CLK_CON_MUX_MUX_CLKCMU_GDC_SCSC, 0, 3), + MUX(CLK_MOUT_CMU_HPM, "mout_cmu_hpm", mout_cmu_hpm_p, + CLK_CON_MUX_MUX_CLKCMU_HPM, 0, 2), + MUX(CLK_MOUT_CMU_HSI0_BUS, "mout_cmu_hsi0_bus", mout_cmu_hsi0_bus_p, + CLK_CON_MUX_MUX_CLKCMU_HSI0_BUS, 0, 3), + MUX(CLK_MOUT_CMU_HSI0_DPGTC, "mout_cmu_hsi0_dpgtc", + mout_cmu_hsi0_dpgtc_p, CLK_CON_MUX_MUX_CLKCMU_HSI0_DPGTC, 0, 2), + MUX(CLK_MOUT_CMU_HSI0_USB31DRD, "mout_cmu_hsi0_usb31drd", + mout_cmu_hsi0_usb31drd_p, CLK_CON_MUX_MUX_CLKCMU_HSI0_USB31DRD, + 0, 1), + MUX(CLK_MOUT_CMU_HSI0_USBDPDBG, "mout_cmu_hsi0_usbdpdbg", + mout_cmu_hsi0_usbdpdbg_p, CLK_CON_MUX_MUX_CLKCMU_HSI0_USBDPDBG, + 0, 1), + MUX(CLK_MOUT_CMU_HSI1_BUS, "mout_cmu_hsi1_bus", mout_cmu_hsi1_bus_p, + CLK_CON_MUX_MUX_CLKCMU_HSI1_BUS, 0, 3), + MUX(CLK_MOUT_CMU_HSI1_PCIE, "mout_cmu_hsi1_pcie", mout_cmu_hsi1_pcie_p, + CLK_CON_MUX_MUX_CLKCMU_HSI1_PCIE, 0, 1), + MUX(CLK_MOUT_CMU_HSI2_BUS, "mout_cmu_hsi2_bus", mout_cmu_hsi2_bus_p, + CLK_CON_MUX_MUX_CLKCMU_HSI2_BUS, 0, 3), + MUX(CLK_MOUT_CMU_HSI2_MMC_CARD, "mout_cmu_hsi2_mmc_card", + mout_cmu_hsi2_mmc_card_p, CLK_CON_MUX_MUX_CLKCMU_HSI2_MMC_CARD, + 0, 2), + MUX(CLK_MOUT_CMU_HSI2_PCIE, "mout_cmu_hsi2_pcie", mout_cmu_hsi2_pcie0_p, + CLK_CON_MUX_MUX_CLKCMU_HSI2_PCIE, 0, 1), + MUX(CLK_MOUT_CMU_HSI2_UFS_EMBD, "mout_cmu_hsi2_ufs_embd", + mout_cmu_hsi2_ufs_embd_p, CLK_CON_MUX_MUX_CLKCMU_HSI2_UFS_EMBD, + 0, 2), + MUX(CLK_MOUT_CMU_IPP_BUS, "mout_cmu_ipp_bus", mout_cmu_ipp_bus_p, + CLK_CON_MUX_MUX_CLKCMU_IPP_BUS, 0, 3), + MUX(CLK_MOUT_CMU_ITP_BUS, "mout_cmu_itp_bus", mout_cmu_itp_bus_p, + CLK_CON_MUX_MUX_CLKCMU_ITP_BUS, 0, 3), + MUX(CLK_MOUT_CMU_MCSC_ITSC, "mout_cmu_mcsc_itsc", mout_cmu_mcsc_itsc_p, + CLK_CON_MUX_MUX_CLKCMU_MCSC_ITSC, 0, 3), + MUX(CLK_MOUT_CMU_MCSC_MCSC, "mout_cmu_mcsc_mcsc", mout_cmu_mcsc_mcsc_p, + CLK_CON_MUX_MUX_CLKCMU_MCSC_MCSC, 0, 3), + MUX(CLK_MOUT_CMU_MFC_MFC, "mout_cmu_mfc_mfc", mout_cmu_mfc_mfc_p, + CLK_CON_MUX_MUX_CLKCMU_MFC_MFC, 0, 3), + MUX(CLK_MOUT_CMU_MIF_BUSP, "mout_cmu_mif_busp", mout_cmu_mif_busp_p, + CLK_CON_MUX_MUX_CLKCMU_MIF_BUSP, 0, 2), + MUX(CLK_MOUT_CMU_MIF_SWITCH, "mout_cmu_mif_switch", + mout_cmu_mif_switch_p, CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH, 0, 3), + MUX(CLK_MOUT_CMU_MISC_BUS, "mout_cmu_misc_bus", mout_cmu_misc_bus_p, + CLK_CON_MUX_MUX_CLKCMU_MISC_BUS, 0, 2), + MUX(CLK_MOUT_CMU_MISC_SSS, "mout_cmu_misc_sss", mout_cmu_misc_sss_p, + CLK_CON_MUX_MUX_CLKCMU_MISC_SSS, 0, 2), + MUX(CLK_MOUT_CMU_PDP_BUS, "mout_cmu_pdp_bus", mout_cmu_pdp_bus_p, + CLK_CON_MUX_MUX_CLKCMU_PDP_BUS, 0, 3), + MUX(CLK_MOUT_CMU_PDP_VRA, "mout_cmu_pdp_vra", mout_cmu_pdp_vra_p, + CLK_CON_MUX_MUX_CLKCMU_PDP_VRA, 0, 3), + MUX(CLK_MOUT_CMU_PERIC0_BUS, "mout_cmu_peric0_bus", + mout_cmu_peric0_bus_p, CLK_CON_MUX_MUX_CLKCMU_PERIC0_BUS, 0, 2), + MUX(CLK_MOUT_CMU_PERIC0_IP, "mout_cmu_peric0_ip", mout_cmu_peric0_ip_p, + CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP, 0, 2), + MUX(CLK_MOUT_CMU_PERIC1_BUS, "mout_cmu_peric1_bus", + mout_cmu_peric1_bus_p, CLK_CON_MUX_MUX_CLKCMU_PERIC1_BUS, 0, 2), + MUX(CLK_MOUT_CMU_PERIC1_IP, "mout_cmu_peric1_ip", mout_cmu_peric1_ip_p, + CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP, 0, 2), + MUX(CLK_MOUT_CMU_TNR_BUS, "mout_cmu_tnr_bus", mout_cmu_tnr_bus_p, + CLK_CON_MUX_MUX_CLKCMU_TNR_BUS, 0, 3), + MUX(CLK_MOUT_CMU_TOP_BOOST_OPTION1, "mout_cmu_top_boost_option1", + mout_cmu_top_boost_option1_p, + CLK_CON_MUX_MUX_CLKCMU_TOP_BOOST_OPTION1, 0, 1), + MUX(CLK_MOUT_CMU_TOP_CMUREF, "mout_cmu_top_cmuref", + mout_cmu_top_cmuref_p, CLK_CON_MUX_MUX_CLKCMU_TOP_CMUREF, 0, 2), + MUX(CLK_MOUT_CMU_TPU_BUS, "mout_cmu_tpu_bus", mout_cmu_tpu_bus_p, + CLK_CON_MUX_MUX_CLKCMU_TPU_BUS, 0, 3), + MUX(CLK_MOUT_CMU_TPU_TPU, "mout_cmu_tpu_tpu", mout_cmu_tpu_tpu_p, + CLK_CON_MUX_MUX_CLKCMU_TPU_TPU, 0, 3), + MUX(CLK_MOUT_CMU_TPU_TPUCTL, "mout_cmu_tpu_tpuctl", + mout_cmu_tpu_tpuctl_p, CLK_CON_MUX_MUX_CLKCMU_TPU_TPUCTL, 0, 3), + MUX(CLK_MOUT_CMU_TPU_UART, "mout_cmu_tpu_uart", mout_cmu_tpu_uart_p, + CLK_CON_MUX_MUX_CLKCMU_TPU_UART, 0, 2), + MUX(CLK_MOUT_CMU_CMUREF, "mout_cmu_cmuref", mout_cmu_cmuref_p, + CLK_CON_MUX_MUX_CMU_CMUREF, 0, 1), +}; + +static const struct samsung_div_clock cmu_top_div_clks[] __initconst = { + DIV(CLK_DOUT_CMU_BO_BUS, "dout_cmu_bo_bus", "gout_cmu_bo_bus", + CLK_CON_DIV_CLKCMU_BO_BUS, 0, 4), + DIV(CLK_DOUT_CMU_BUS0_BUS, "dout_cmu_bus0_bus", "gout_cmu_bus0_bus", + CLK_CON_DIV_CLKCMU_BUS0_BUS, 0, 4), + DIV(CLK_DOUT_CMU_BUS1_BUS, "dout_cmu_bus1_bus", "gout_cmu_bus1_bus", + CLK_CON_DIV_CLKCMU_BUS1_BUS, 0, 4), + DIV(CLK_DOUT_CMU_BUS2_BUS, "dout_cmu_bus2_bus", "gout_cmu_bus2_bus", + CLK_CON_DIV_CLKCMU_BUS2_BUS, 0, 4), + DIV(CLK_DOUT_CMU_CIS_CLK0, "dout_cmu_cis_clk0", "gout_cmu_cis_clk0", + CLK_CON_DIV_CLKCMU_CIS_CLK0, 0, 5), + DIV(CLK_DOUT_CMU_CIS_CLK1, "dout_cmu_cis_clk1", "gout_cmu_cis_clk1", + CLK_CON_DIV_CLKCMU_CIS_CLK1, 0, 5), + DIV(CLK_DOUT_CMU_CIS_CLK2, "dout_cmu_cis_clk2", "gout_cmu_cis_clk2", + CLK_CON_DIV_CLKCMU_CIS_CLK2, 0, 5), + DIV(CLK_DOUT_CMU_CIS_CLK3, "dout_cmu_cis_clk3", "gout_cmu_cis_clk3", + CLK_CON_DIV_CLKCMU_CIS_CLK3, 0, 5), + DIV(CLK_DOUT_CMU_CIS_CLK4, "dout_cmu_cis_clk4", "gout_cmu_cis_clk4", + CLK_CON_DIV_CLKCMU_CIS_CLK4, 0, 5), + DIV(CLK_DOUT_CMU_CIS_CLK5, "dout_cmu_cis_clk5", "gout_cmu_cis_clk5", + CLK_CON_DIV_CLKCMU_CIS_CLK5, 0, 5), + DIV(CLK_DOUT_CMU_CIS_CLK6, "dout_cmu_cis_clk6", "gout_cmu_cis_clk6", + CLK_CON_DIV_CLKCMU_CIS_CLK6, 0, 5), + DIV(CLK_DOUT_CMU_CIS_CLK7, "dout_cmu_cis_clk7", "gout_cmu_cis_clk7", + CLK_CON_DIV_CLKCMU_CIS_CLK7, 0, 5), + DIV(CLK_DOUT_CMU_CORE_BUS, "dout_cmu_core_bus", "gout_cmu_core_bus", + CLK_CON_DIV_CLKCMU_CORE_BUS, 0, 4), + DIV(CLK_DOUT_CMU_CPUCL0_DBG, "dout_cmu_cpucl0_dbg", + "gout_cmu_cpucl0_dbg", CLK_CON_DIV_CLKCMU_CPUCL0_DBG, 0, 4), + DIV(CLK_DOUT_CMU_CPUCL0_SWITCH, "dout_cmu_cpucl0_switch", + "gout_cmu_cpucl0_switch", CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH, 0, 3), + DIV(CLK_DOUT_CMU_CPUCL1_SWITCH, "dout_cmu_cpucl1_switch", + "gout_cmu_cpucl1_switch", CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH, 0, 3), + DIV(CLK_DOUT_CMU_CPUCL2_SWITCH, "dout_cmu_cpucl2_switch", + "gout_cmu_cpucl2_switch", CLK_CON_DIV_CLKCMU_CPUCL2_SWITCH, 0, 3), + DIV(CLK_DOUT_CMU_CSIS_BUS, "dout_cmu_csis_bus", "gout_cmu_csis_bus", + CLK_CON_DIV_CLKCMU_CSIS_BUS, 0, 4), + DIV(CLK_DOUT_CMU_DISP_BUS, "dout_cmu_disp_bus", "gout_cmu_disp_bus", + CLK_CON_DIV_CLKCMU_DISP_BUS, 0, 4), + DIV(CLK_DOUT_CMU_DNS_BUS, "dout_cmu_dns_bus", "gout_cmu_dns_bus", + CLK_CON_DIV_CLKCMU_DNS_BUS, 0, 4), + DIV(CLK_DOUT_CMU_DPU_BUS, "dout_cmu_dpu_bus", "gout_cmu_dpu_bus", + CLK_CON_DIV_CLKCMU_DPU_BUS, 0, 4), + DIV(CLK_DOUT_CMU_EH_BUS, "dout_cmu_eh_bus", "gout_cmu_eh_bus", + CLK_CON_DIV_CLKCMU_EH_BUS, 0, 4), + DIV(CLK_DOUT_CMU_G2D_G2D, "dout_cmu_g2d_g2d", "gout_cmu_g2d_g2d", + CLK_CON_DIV_CLKCMU_G2D_G2D, 0, 4), + DIV(CLK_DOUT_CMU_G2D_MSCL, "dout_cmu_g2d_mscl", "gout_cmu_g2d_mscl", + CLK_CON_DIV_CLKCMU_G2D_MSCL, 0, 4), + DIV(CLK_DOUT_CMU_G3AA_G3AA, "dout_cmu_g3aa_g3aa", "gout_cmu_g3aa_g3aa", + CLK_CON_DIV_CLKCMU_G3AA_G3AA, 0, 4), + DIV(CLK_DOUT_CMU_G3D_SWITCH, "dout_cmu_g3d_busd", "gout_cmu_g3d_busd", + CLK_CON_DIV_CLKCMU_G3D_BUSD, 0, 4), + DIV(CLK_DOUT_CMU_G3D_GLB, "dout_cmu_g3d_glb", "gout_cmu_g3d_glb", + CLK_CON_DIV_CLKCMU_G3D_GLB, 0, 4), + DIV(CLK_DOUT_CMU_G3D_SWITCH, "dout_cmu_g3d_switch", + "gout_cmu_g3d_switch", CLK_CON_DIV_CLKCMU_G3D_SWITCH, 0, 3), + DIV(CLK_DOUT_CMU_GDC_GDC0, "dout_cmu_gdc_gdc0", "gout_cmu_gdc_gdc0", + CLK_CON_DIV_CLKCMU_GDC_GDC0, 0, 4), + DIV(CLK_DOUT_CMU_GDC_GDC1, "dout_cmu_gdc_gdc1", "gout_cmu_gdc_gdc1", + CLK_CON_DIV_CLKCMU_GDC_GDC1, 0, 4), + DIV(CLK_DOUT_CMU_GDC_SCSC, "dout_cmu_gdc_scsc", "gout_cmu_gdc_scsc", + CLK_CON_DIV_CLKCMU_GDC_SCSC, 0, 4), + DIV(CLK_DOUT_CMU_CMU_HPM, "dout_cmu_hpm", "gout_cmu_hpm", + CLK_CON_DIV_CLKCMU_HPM, 0, 2), + DIV(CLK_DOUT_CMU_HSI0_BUS, "dout_cmu_hsi0_bus", "gout_cmu_hsi0_bus", + CLK_CON_DIV_CLKCMU_HSI0_BUS, 0, 4), + DIV(CLK_DOUT_CMU_HSI0_DPGTC, "dout_cmu_hsi0_dpgtc", + "gout_cmu_hsi0_dpgtc", CLK_CON_DIV_CLKCMU_HSI0_DPGTC, 0, 4), + DIV(CLK_DOUT_CMU_HSI0_USB31DRD, "dout_cmu_hsi0_usb31drd", + "gout_cmu_hsi0_usb31drd", CLK_CON_DIV_CLKCMU_HSI0_USB31DRD, 0, 5), + DIV(CLK_DOUT_CMU_HSI1_BUS, "dout_cmu_hsi1_bus", "gout_cmu_hsi1_bus", + CLK_CON_DIV_CLKCMU_HSI1_BUS, 0, 4), + DIV(CLK_DOUT_CMU_HSI1_PCIE, "dout_cmu_hsi1_pcie", "gout_cmu_hsi1_pcie", + CLK_CON_DIV_CLKCMU_HSI1_PCIE, 0, 3), + DIV(CLK_DOUT_CMU_HSI2_BUS, "dout_cmu_hsi2_bus", "gout_cmu_hsi2_bus", + CLK_CON_DIV_CLKCMU_HSI2_BUS, 0, 4), + DIV(CLK_DOUT_CMU_HSI2_MMC_CARD, "dout_cmu_hsi2_mmc_card", + "gout_cmu_hsi2_mmc_card", CLK_CON_DIV_CLKCMU_HSI2_MMC_CARD, 0, 9), + DIV(CLK_DOUT_CMU_HSI2_PCIE, "dout_cmu_hsi2_pcie", "gout_cmu_hsi2_pcie", + CLK_CON_DIV_CLKCMU_HSI2_PCIE, 0, 3), + DIV(CLK_DOUT_CMU_HSI2_UFS_EMBD, "dout_cmu_hsi2_ufs_embd", + "gout_cmu_hsi2_ufs_embd", CLK_CON_DIV_CLKCMU_HSI2_UFS_EMBD, 0, 4), + DIV(CLK_DOUT_CMU_IPP_BUS, "dout_cmu_ipp_bus", "gout_cmu_ipp_bus", + CLK_CON_DIV_CLKCMU_IPP_BUS, 0, 4), + DIV(CLK_DOUT_CMU_ITP_BUS, "dout_cmu_itp_bus", "gout_cmu_itp_bus", + CLK_CON_DIV_CLKCMU_ITP_BUS, 0, 4), + DIV(CLK_DOUT_CMU_MCSC_ITSC, "dout_cmu_mcsc_itsc", "gout_cmu_mcsc_itsc", + CLK_CON_DIV_CLKCMU_MCSC_ITSC, 0, 4), + DIV(CLK_DOUT_CMU_MCSC_MCSC, "dout_cmu_mcsc_mcsc", "gout_cmu_mcsc_mcsc", + CLK_CON_DIV_CLKCMU_MCSC_MCSC, 0, 4), + DIV(CLK_DOUT_CMU_MFC_MFC, "dout_cmu_mfc_mfc", "gout_cmu_mfc_mfc", + CLK_CON_DIV_CLKCMU_MFC_MFC, 0, 4), + DIV(CLK_DOUT_CMU_MIF_BUSP, "dout_cmu_mif_busp", "gout_cmu_mif_busp", + CLK_CON_DIV_CLKCMU_MIF_BUSP, 0, 4), + DIV(CLK_DOUT_CMU_MISC_BUS, "dout_cmu_misc_bus", "gout_cmu_misc_bus", + CLK_CON_DIV_CLKCMU_MISC_BUS, 0, 4), + DIV(CLK_DOUT_CMU_MISC_SSS, "dout_cmu_misc_sss", "gout_cmu_misc_sss", + CLK_CON_DIV_CLKCMU_MISC_SSS, 0, 4), + DIV(CLK_DOUT_CMU_PDP_BUS, "dout_cmu_pdp_bus", "gout_cmu_pdp_bus", + CLK_CON_DIV_CLKCMU_PDP_BUS, 0, 4), + DIV(CLK_DOUT_CMU_PDP_VRA, "dout_cmu_pdp_vra", "gout_cmu_pdp_vra", + CLK_CON_DIV_CLKCMU_PDP_VRA, 0, 4), + DIV(CLK_DOUT_CMU_PERIC0_BUS, "dout_cmu_peric0_bus", + "gout_cmu_peric0_bus", CLK_CON_DIV_CLKCMU_PERIC0_BUS, 0, 4), + DIV(CLK_DOUT_CMU_PERIC0_IP, "dout_cmu_peric0_ip", "gout_cmu_peric0_ip", + CLK_CON_DIV_CLKCMU_PERIC0_IP, 0, 4), + DIV(CLK_DOUT_CMU_PERIC1_BUS, "dout_cmu_peric1_bus", + "gout_cmu_peric1_bus", CLK_CON_DIV_CLKCMU_PERIC1_BUS, 0, 4), + DIV(CLK_DOUT_CMU_PERIC1_IP, "dout_cmu_peric1_ip", "gout_cmu_peric1_ip", + CLK_CON_DIV_CLKCMU_PERIC1_IP, 0, 4), + DIV(CLK_DOUT_CMU_TNR_BUS, "dout_cmu_tnr_bus", "gout_cmu_tnr_bus", + CLK_CON_DIV_CLKCMU_TNR_BUS, 0, 4), + DIV(CLK_DOUT_CMU_TPU_BUS, "dout_cmu_tpu_bus", "gout_cmu_tpu_bus", + CLK_CON_DIV_CLKCMU_TPU_BUS, 0, 4), + DIV(CLK_DOUT_CMU_TPU_TPU, "dout_cmu_tpu_tpu", "gout_cmu_tpu_tpu", + CLK_CON_DIV_CLKCMU_TPU_TPU, 0, 4), + DIV(CLK_DOUT_CMU_TPU_TPUCTL, "dout_cmu_tpu_tpuctl", + "gout_cmu_tpu_tpuctl", CLK_CON_DIV_CLKCMU_TPU_TPUCTL, 0, 4), + DIV(CLK_DOUT_CMU_TPU_UART, "dout_cmu_tpu_uart", "gout_cmu_tpu_uart", + CLK_CON_DIV_CLKCMU_TPU_UART, 0, 4), + DIV(CLK_DOUT_CMU_CMU_BOOST, "dout_cmu_cmu_boost", "gout_cmu_cmu_boost", + CLK_CON_DIV_DIV_CLKCMU_CMU_BOOST, 0, 2), + DIV(CLK_DOUT_CMU_CMU_CMUREF, "dout_cmu_cmuref", "gout_cmu_cmuref", + CLK_CON_DIV_DIV_CLK_CMU_CMUREF, 0, 2), + DIV(CLK_DOUT_CMU_SHARED0_DIV2, "dout_cmu_shared0_div2", + "mout_pll_shared0", CLK_CON_DIV_PLL_SHARED0_DIV2, 0, 1), + DIV(CLK_DOUT_CMU_SHARED0_DIV3, "dout_cmu_shared0_div3", + "mout_pll_shared0", CLK_CON_DIV_PLL_SHARED0_DIV3, 0, 2), + DIV(CLK_DOUT_CMU_SHARED0_DIV4, "dout_cmu_shared0_div4", + "dout_cmu_shared0_div2", CLK_CON_DIV_PLL_SHARED0_DIV4, 0, 1), + DIV(CLK_DOUT_CMU_SHARED0_DIV5, "dout_cmu_shared0_div5", + "mout_pll_shared0", CLK_CON_DIV_PLL_SHARED0_DIV5, 0, 3), + DIV(CLK_DOUT_CMU_SHARED1_DIV2, "dout_cmu_shared1_div2", + "mout_pll_shared1", CLK_CON_DIV_PLL_SHARED1_DIV2, 0, 1), + DIV(CLK_DOUT_CMU_SHARED1_DIV3, "dout_cmu_shared1_div3", + "mout_pll_shared1", CLK_CON_DIV_PLL_SHARED1_DIV3, 0, 2), + DIV(CLK_DOUT_CMU_SHARED1_DIV4, "dout_cmu_shared1_div4", + "mout_pll_shared1", CLK_CON_DIV_PLL_SHARED1_DIV4, 0, 1), + DIV(CLK_DOUT_CMU_SHARED2_DIV2, "dout_cmu_shared2_div2", + "mout_pll_shared2", CLK_CON_DIV_PLL_SHARED2_DIV2, 0, 1), + DIV(CLK_DOUT_CMU_SHARED3_DIV2, "dout_cmu_shared3_div2", + "mout_pll_shared3", CLK_CON_DIV_PLL_SHARED3_DIV2, 0, 1), +}; + +static const struct samsung_fixed_factor_clock cmu_top_ffactor[] __initconst = { + FFACTOR(CLK_DOUT_CMU_HSI0_USBDPDBG, "dout_cmu_hsi0_usbdpdbg", + "gout_cmu_hsi0_usbdpdbg", 1, 4, 0), + FFACTOR(CLK_DOUT_CMU_OTP, "dout_cmu_otp", "oscclk", 1, 8, 0), +}; + +static const struct samsung_gate_clock cmu_top_gate_clks[] __initconst = { + GATE(CLK_GOUT_BUS0_BOOST, "gout_cmu_bus0_boost", + "mout_cmu_boost_option1", CLK_CON_GAT_CLKCMU_BUS0_BOOST, 21, 0, 0), + GATE(CLK_GOUT_BUS1_BOOST, "gout_cmu_bus1_boost", + "mout_cmu_boost_option1", CLK_CON_GAT_CLKCMU_BUS1_BOOST, 21, 0, 0), + GATE(CLK_GOUT_BUS2_BOOST, "gout_cmu_bus2_boost", + "mout_cmu_boost_option1", CLK_CON_GAT_CLKCMU_BUS2_BOOST, 21, 0, 0), + GATE(CLK_GOUT_CORE_BOOST, "gout_cmu_core_boost", + "mout_cmu_boost_option1", CLK_CON_GAT_CLKCMU_CORE_BOOST, 21, 0, 0), + GATE(CLK_GOUT_CPUCL0_BOOST, "gout_cmu_cpucl0_boost", + "mout_cmu_boost_option1", CLK_CON_GAT_CLKCMU_CPUCL0_BOOST, + 21, 0, 0), + GATE(CLK_GOUT_CPUCL1_BOOST, "gout_cmu_cpucl1_boost", + "mout_cmu_boost_option1", CLK_CON_GAT_CLKCMU_CPUCL1_BOOST, + 21, 0, 0), + GATE(CLK_GOUT_CPUCL2_BOOST, "gout_cmu_cpucl2_boost", + "mout_cmu_boost_option1", CLK_CON_GAT_CLKCMU_CPUCL2_BOOST, + 21, 0, 0), + GATE(CLK_GOUT_MIF_BOOST, "gout_cmu_mif_boost", + "mout_cmu_boost_option1", CLK_CON_GAT_CLKCMU_MIF_BOOST, + 21, 0, 0), + GATE(CLK_GOUT_MIF_SWITCH, "gout_cmu_mif_switch", "mout_cmu_mif_switch", + CLK_CON_GAT_CLKCMU_MIF_SWITCH, 21, 0, 0), + GATE(CLK_GOUT_BO_BUS, "gout_cmu_bo_bus", "mout_cmu_bo_bus", + CLK_CON_GAT_GATE_CLKCMU_BO_BUS, 21, 0, 0), + GATE(CLK_GOUT_BUS0_BUS, "gout_cmu_bus0_bus", "mout_cmu_bus0_bus", + CLK_CON_GAT_GATE_CLKCMU_BUS0_BUS, 21, 0, 0), + GATE(CLK_GOUT_BUS1_BUS, "gout_cmu_bus1_bus", "mout_cmu_bus1_bus", + CLK_CON_GAT_GATE_CLKCMU_BUS1_BUS, 21, 0, 0), + GATE(CLK_GOUT_BUS2_BUS, "gout_cmu_bus2_bus", "mout_cmu_bus2_bus", + CLK_CON_GAT_GATE_CLKCMU_BUS2_BUS, 21, 0, 0), + GATE(CLK_GOUT_CIS_CLK0, "gout_cmu_cis_clk0", "mout_cmu_cis_clk0", + CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0, 21, 0, 0), + GATE(CLK_GOUT_CIS_CLK1, "gout_cmu_cis_clk1", "mout_cmu_cis_clk1", + CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1, 21, 0, 0), + GATE(CLK_GOUT_CIS_CLK2, "gout_cmu_cis_clk2", "mout_cmu_cis_clk2", + CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2, 21, 0, 0), + GATE(CLK_GOUT_CIS_CLK3, "gout_cmu_cis_clk3", "mout_cmu_cis_clk3", + CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3, 21, 0, 0), + GATE(CLK_GOUT_CIS_CLK4, "gout_cmu_cis_clk4", "mout_cmu_cis_clk4", + CLK_CON_GAT_GATE_CLKCMU_CIS_CLK4, 21, 0, 0), + GATE(CLK_GOUT_CIS_CLK5, "gout_cmu_cis_clk5", "mout_cmu_cis_clk5", + CLK_CON_GAT_GATE_CLKCMU_CIS_CLK5, 21, 0, 0), + GATE(CLK_GOUT_CIS_CLK6, "gout_cmu_cis_clk6", "mout_cmu_cis_clk6", + CLK_CON_GAT_GATE_CLKCMU_CIS_CLK6, 21, 0, 0), + GATE(CLK_GOUT_CIS_CLK7, "gout_cmu_cis_clk7", "mout_cmu_cis_clk7", + CLK_CON_GAT_GATE_CLKCMU_CIS_CLK7, 21, 0, 0), + GATE(CLK_GOUT_CMU_BOOST, "gout_cmu_cmu_boost", "mout_cmu_cmu_boost", + CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST, 21, 0, 0), + GATE(CLK_GOUT_CORE_BUS, "gout_cmu_core_bus", "mout_cmu_core_bus", + CLK_CON_GAT_GATE_CLKCMU_CORE_BUS, 21, 0, 0), + GATE(CLK_GOUT_CPUCL0_DBG, "gout_cmu_cpucl0_dbg", "mout_cmu_cpucl0_dbg", + CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_BUS, 21, 0, 0), + GATE(CLK_GOUT_CPUCL0_SWITCH, "gout_cmu_cpucl0_switch", + "mout_cmu_cpucl0_switch", CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH, + 21, 0, 0), + GATE(CLK_GOUT_CPUCL1_SWITCH, "gout_cmu_cpucl1_switch", + "mout_cmu_cpucl1_switch", CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH, + 21, 0, 0), + GATE(CLK_GOUT_CPUCL2_SWITCH, "gout_cmu_cpucl2_switch", + "mout_cmu_cpucl2_switch", CLK_CON_GAT_GATE_CLKCMU_CPUCL2_SWITCH, + 21, 0, 0), + GATE(CLK_GOUT_CSIS_BUS, "gout_cmu_csis_bus", "mout_cmu_csis_bus", + CLK_CON_GAT_GATE_CLKCMU_CSIS_BUS, 21, 0, 0), + GATE(CLK_GOUT_DISP_BUS, "gout_cmu_disp_bus", "mout_cmu_disp_bus", + CLK_CON_GAT_GATE_CLKCMU_DISP_BUS, 21, 0, 0), + GATE(CLK_GOUT_DNS_BUS, "gout_cmu_dns_bus", "mout_cmu_dns_bus", + CLK_CON_GAT_GATE_CLKCMU_DNS_BUS, 21, 0, 0), + GATE(CLK_GOUT_DPU_BUS, "gout_cmu_dpu_bus", "mout_cmu_dpu_bus", + CLK_CON_GAT_GATE_CLKCMU_DPU_BUS, 21, 0, 0), + GATE(CLK_GOUT_EH_BUS, "gout_cmu_eh_bus", "mout_cmu_eh_bus", + CLK_CON_GAT_GATE_CLKCMU_EH_BUS, 21, 0, 0), + GATE(CLK_GOUT_G2D_G2D, "gout_cmu_g2d_g2d", "mout_cmu_g2d_g2d", + CLK_CON_GAT_GATE_CLKCMU_G2D_G2D, 21, 0, 0), + GATE(CLK_GOUT_G2D_MSCL, "gout_cmu_g2d_mscl", "mout_cmu_g2d_mscl", + CLK_CON_GAT_GATE_CLKCMU_G2D_MSCL, 21, 0, 0), + GATE(CLK_GOUT_G3AA_G3AA, "gout_cmu_g3aa_g3aa", "mout_cmu_g3aa_g3aa", + CLK_CON_MUX_MUX_CLKCMU_G3AA_G3AA, 21, 0, 0), + GATE(CLK_GOUT_G3D_BUSD, "gout_cmu_g3d_busd", "mout_cmu_g3d_busd", + CLK_CON_GAT_GATE_CLKCMU_G3D_BUSD, 21, 0, 0), + GATE(CLK_GOUT_G3D_GLB, "gout_cmu_g3d_glb", "mout_cmu_g3d_glb", + CLK_CON_GAT_GATE_CLKCMU_G3D_GLB, 21, 0, 0), + GATE(CLK_GOUT_G3D_SWITCH, "gout_cmu_g3d_switch", "mout_cmu_g3d_switch", + CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH, 21, 0, 0), + GATE(CLK_GOUT_GDC_GDC0, "gout_cmu_gdc_gdc0", "mout_cmu_gdc_gdc0", + CLK_CON_GAT_GATE_CLKCMU_GDC_GDC0, 21, 0, 0), + GATE(CLK_GOUT_GDC_GDC1, "gout_cmu_gdc_gdc1", "mout_cmu_gdc_gdc1", + CLK_CON_GAT_GATE_CLKCMU_GDC_GDC1, 21, 0, 0), + GATE(CLK_GOUT_GDC_SCSC, "gout_cmu_gdc_scsc", "mout_cmu_gdc_scsc", + CLK_CON_GAT_GATE_CLKCMU_GDC_SCSC, 21, 0, 0), + GATE(CLK_GOUT_CMU_HPM, "gout_cmu_hpm", "mout_cmu_hpm", + CLK_CON_GAT_GATE_CLKCMU_HPM, 21, 0, 0), + GATE(CLK_GOUT_HSI0_BUS, "gout_cmu_hsi0_bus", "mout_cmu_hsi0_bus", + CLK_CON_GAT_GATE_CLKCMU_HSI0_BUS, 21, 0, 0), + GATE(CLK_GOUT_HSI0_DPGTC, "gout_cmu_hsi0_dpgtc", "mout_cmu_hsi0_dpgtc", + CLK_CON_GAT_GATE_CLKCMU_HSI0_DPGTC, 21, 0, 0), + GATE(CLK_GOUT_HSI0_USB31DRD, "gout_cmu_hsi0_usb31drd", + "mout_cmu_hsi0_usb31drd", CLK_CON_GAT_GATE_CLKCMU_HSI0_USB31DRD, + 21, 0, 0), + GATE(CLK_GOUT_HSI0_USBDPDBG, "gout_cmu_hsi0_usbdpdbg", + "mout_cmu_hsi0_usbdpdbg", CLK_CON_GAT_GATE_CLKCMU_HSI0_USBDPDBG, + 21, 0, 0), + GATE(CLK_GOUT_HSI1_BUS, "gout_cmu_hsi1_bus", "mout_cmu_hsi1_bus", + CLK_CON_GAT_GATE_CLKCMU_HSI1_BUS, 21, 0, 0), + GATE(CLK_GOUT_HSI1_PCIE, "gout_cmu_hsi1_pcie", "mout_cmu_hsi1_pcie", + CLK_CON_GAT_GATE_CLKCMU_HSI1_PCIE, 21, 0, 0), + GATE(CLK_GOUT_HSI2_BUS, "gout_cmu_hsi2_bus", "mout_cmu_hsi2_bus", + CLK_CON_GAT_GATE_CLKCMU_HSI2_BUS, 21, 0, 0), + GATE(CLK_GOUT_HSI2_MMC_CARD, "gout_cmu_hsi2_mmc_card", + "mout_cmu_hsi2_mmc_card", CLK_CON_GAT_GATE_CLKCMU_HSI2_MMCCARD, + 21, 0, 0), + GATE(CLK_GOUT_HSI2_PCIE, "gout_cmu_hsi2_pcie", "mout_cmu_hsi2_pcie", + CLK_CON_GAT_GATE_CLKCMU_HSI2_PCIE, 21, 0, 0), + GATE(CLK_GOUT_HSI2_UFS_EMBD, "gout_cmu_hsi2_ufs_embd", + "mout_cmu_hsi2_ufs_embd", CLK_CON_GAT_GATE_CLKCMU_HSI2_UFS_EMBD, + 21, 0, 0), + GATE(CLK_GOUT_IPP_BUS, "gout_cmu_ipp_bus", "mout_cmu_ipp_bus", + CLK_CON_GAT_GATE_CLKCMU_IPP_BUS, 21, 0, 0), + GATE(CLK_GOUT_ITP_BUS, "gout_cmu_itp_bus", "mout_cmu_itp_bus", + CLK_CON_GAT_GATE_CLKCMU_ITP_BUS, 21, 0, 0), + GATE(CLK_GOUT_MCSC_ITSC, "gout_cmu_mcsc_itsc", "mout_cmu_mcsc_itsc", + CLK_CON_GAT_GATE_CLKCMU_MCSC_ITSC, 21, 0, 0), + GATE(CLK_GOUT_MCSC_MCSC, "gout_cmu_mcsc_mcsc", "mout_cmu_mcsc_mcsc", + CLK_CON_GAT_GATE_CLKCMU_MCSC_MCSC, 21, 0, 0), + GATE(CLK_GOUT_MFC_MFC, "gout_cmu_mfc_mfc", "mout_cmu_mfc_mfc", + CLK_CON_GAT_GATE_CLKCMU_MFC_MFC, 21, 0, 0), + GATE(CLK_GOUT_MIF_BUSP, "gout_cmu_mif_busp", "mout_cmu_mif_busp", + CLK_CON_GAT_GATE_CLKCMU_MIF_BUSP, 21, 0, 0), + GATE(CLK_GOUT_MISC_BUS, "gout_cmu_misc_bus", "mout_cmu_misc_bus", + CLK_CON_GAT_GATE_CLKCMU_MISC_BUS, 21, 0, 0), + GATE(CLK_GOUT_MISC_SSS, "gout_cmu_misc_sss", "mout_cmu_misc_sss", + CLK_CON_GAT_GATE_CLKCMU_MISC_SSS, 21, 0, 0), + GATE(CLK_GOUT_PDP_BUS, "gout_cmu_pdp_bus", "mout_cmu_pdp_bus", + CLK_CON_GAT_GATE_CLKCMU_PDP_BUS, 21, 0, 0), + GATE(CLK_GOUT_PDP_VRA, "gout_cmu_pdp_vra", "mout_cmu_pdp_vra", + CLK_CON_GAT_GATE_CLKCMU_PDP_BUS, 21, 0, 0), + GATE(CLK_GOUT_PERIC0_BUS, "gout_cmu_peric0_bus", "mout_cmu_peric0_bus", + CLK_CON_GAT_GATE_CLKCMU_PERIC0_BUS, 21, 0, 0), + GATE(CLK_GOUT_PERIC0_IP, "gout_cmu_peric0_ip", "mout_cmu_peric0_ip", + CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP, 21, 0, 0), + GATE(CLK_GOUT_PERIC1_BUS, "gout_cmu_peric1_bus", "mout_cmu_peric1_bus", + CLK_CON_GAT_GATE_CLKCMU_PERIC1_BUS, 21, 0, 0), + GATE(CLK_GOUT_PERIC1_IP, "gout_cmu_peric1_ip", "mout_cmu_peric1_ip", + CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP, 21, 0, 0), + GATE(CLK_GOUT_TNR_BUS, "gout_cmu_tnr_bus", "mout_cmu_tnr_bus", + CLK_CON_GAT_GATE_CLKCMU_TNR_BUS, 21, 0, 0), + GATE(CLK_GOUT_TOP_CMUREF, "gout_cmu_top_cmuref", "mout_cmu_top_cmuref", + CLK_CON_GAT_GATE_CLKCMU_TOP_CMUREF, 21, 0, 0), + GATE(CLK_GOUT_TPU_BUS, "gout_cmu_tpu_bus", "mout_cmu_tpu_bus", + CLK_CON_GAT_GATE_CLKCMU_TPU_BUS, 21, 0, 0), + GATE(CLK_GOUT_TPU_TPU, "gout_cmu_tpu_tpu", "mout_cmu_tpu_tpu", + CLK_CON_GAT_GATE_CLKCMU_TPU_TPU, 21, 0, 0), + GATE(CLK_GOUT_TPU_TPUCTL, "gout_cmu_tpu_tpuctl", "mout_cmu_tpu_tpuctl", + CLK_CON_GAT_GATE_CLKCMU_TPU_TPUCTL, 21, 0, 0), + GATE(CLK_GOUT_TPU_UART, "gout_cmu_tpu_uart", "mout_cmu_tpu_uart", + CLK_CON_GAT_GATE_CLKCMU_TPU_UART, 21, 0, 0), +}; + +static const struct samsung_cmu_info top_cmu_info __initconst = { + .pll_clks = cmu_top_pll_clks, + .nr_pll_clks = ARRAY_SIZE(cmu_top_pll_clks), + .mux_clks = cmu_top_mux_clks, + .nr_mux_clks = ARRAY_SIZE(cmu_top_mux_clks), + .div_clks = cmu_top_div_clks, + .nr_div_clks = ARRAY_SIZE(cmu_top_div_clks), + .fixed_factor_clks = cmu_top_ffactor, + .nr_fixed_factor_clks = ARRAY_SIZE(cmu_top_ffactor), + .gate_clks = cmu_top_gate_clks, + .nr_gate_clks = ARRAY_SIZE(cmu_top_gate_clks), + .nr_clk_ids = CLKS_NR_TOP, + .clk_regs = cmu_top_clk_regs, + .nr_clk_regs = ARRAY_SIZE(cmu_top_clk_regs), +}; + +static void __init gs101_cmu_top_init(struct device_node *np) +{ + exynos_arm64_register_cmu(NULL, np, &top_cmu_info); +} + +/* Register CMU_TOP early, as it's a dependency for other early domains */ +CLK_OF_DECLARE(gs101_cmu_top, "google,gs101-cmu-top", + gs101_cmu_top_init); + +/* ---- CMU_APM ------------------------------------------------------------- */ + +/* Register Offset definitions for CMU_APM (0x17400000) */ +#define APM_CMU_APM_CONTROLLER_OPTION 0x0800 +#define CLKOUT_CON_BLK_APM_CMU_APM_CLKOUT0 0x0810 +#define CLK_CON_MUX_MUX_CLKCMU_APM_FUNC 0x1000 +#define CLK_CON_MUX_MUX_CLKCMU_APM_FUNCSRC 0x1004 +#define CLK_CON_DIV_DIV_CLK_APM_BOOST 0x1800 +#define CLK_CON_DIV_DIV_CLK_APM_USI0_UART 0x1804 +#define CLK_CON_DIV_DIV_CLK_APM_USI0_USI 0x1808 +#define CLK_CON_DIV_DIV_CLK_APM_USI1_UART 0x180c +#define CLK_CON_GAT_CLK_BLK_APM_UID_APM_CMU_APM_IPCLKPORT_PCLK 0x2000 +#define CLK_CON_GAT_CLK_BUS0_BOOST_OPTION1 0x2004 +#define CLK_CON_GAT_CLK_CMU_BOOST_OPTION1 0x2008 +#define CLK_CON_GAT_CLK_CORE_BOOST_OPTION1 0x200c +#define CLK_CON_GAT_GATE_CLKCMU_APM_FUNC 0x2010 +#define CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK 0x2014 +#define CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_FAR_ALIVE_IPCLKPORT_PCLK 0x2018 +#define CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK 0x201c +#define CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_RTC_IPCLKPORT_PCLK 0x2020 +#define CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_TRTC_IPCLKPORT_PCLK 0x2024 +#define CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_UART_IPCLKPORT_IPCLK 0x2028 +#define CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_UART_IPCLKPORT_PCLK 0x202c +#define CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_USI_IPCLKPORT_IPCLK 0x2030 +#define CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_USI_IPCLKPORT_PCLK 0x2034 +#define CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI1_UART_IPCLKPORT_IPCLK 0x2038 +#define CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI1_UART_IPCLKPORT_PCLK 0x203c +#define CLK_CON_GAT_GOUT_BLK_APM_UID_D_TZPC_APM_IPCLKPORT_PCLK 0x2040 +#define CLK_CON_GAT_GOUT_BLK_APM_UID_GPC_APM_IPCLKPORT_PCLK 0x2044 +#define CLK_CON_GAT_GOUT_BLK_APM_UID_GREBEINTEGRATION_IPCLKPORT_HCLK 0x2048 +#define CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_ACLK 0x204c +#define CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_PCLK 0x2050 +#define CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_G_SWD_IPCLKPORT_I_CLK 0x2054 +#define CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_AOCAPM_IPCLKPORT_I_CLK 0x2058 +#define CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_IPCLKPORT_I_CLK 0x205c +#define CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_D_APM_IPCLKPORT_I_CLK 0x2060 +#define CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_G_DBGCORE_IPCLKPORT_I_CLK 0x2064 +#define CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_G_SCAN2DRAM_IPCLKPORT_I_CLK 0x2068 +#define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_AOC_IPCLKPORT_PCLK 0x206c +#define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_AP_IPCLKPORT_PCLK 0x2070 +#define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_GSA_IPCLKPORT_PCLK 0x2074 +#define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_SWD_IPCLKPORT_PCLK 0x207c +#define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_TPU_IPCLKPORT_PCLK 0x2080 +#define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP_AOC_IPCLKPORT_PCLK 0x2084 +#define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP_DBGCORE_IPCLKPORT_PCLK 0x2088 +#define CLK_CON_GAT_GOUT_BLK_APM_UID_PMU_INTR_GEN_IPCLKPORT_PCLK 0x208c +#define CLK_CON_GAT_GOUT_BLK_APM_UID_ROM_CRC32_HOST_IPCLKPORT_ACLK 0x2090 +#define CLK_CON_GAT_GOUT_BLK_APM_UID_ROM_CRC32_HOST_IPCLKPORT_PCLK 0x2094 +#define CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_BUS_IPCLKPORT_CLK 0x2098 +#define CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI0_UART_IPCLKPORT_CLK 0x209c +#define CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI0_USI_IPCLKPORT_CLK 0x20a0 +#define CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI1_UART_IPCLKPORT_CLK 0x20a4 +#define CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_APM_IPCLKPORT_PCLK 0x20a8 +#define CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_SUB_APM_IPCLKPORT_PCLK 0x20ac +#define CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_D_APM_IPCLKPORT_ACLK 0x20b0 +#define CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_D_APM_IPCLKPORT_PCLK 0x20b4 +#define CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_G_DBGCORE_IPCLKPORT_ACLK 0x20b8 +#define CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_G_DBGCORE_IPCLKPORT_PCLK 0x20bc +#define CLK_CON_GAT_GOUT_BLK_APM_UID_SS_DBGCORE_IPCLKPORT_SS_DBGCORE_IPCLKPORT_HCLK 0x20c0 +#define CLK_CON_GAT_GOUT_BLK_APM_UID_SYSMMU_D_APM_IPCLKPORT_CLK_S2 0x20c4 +#define CLK_CON_GAT_GOUT_BLK_APM_UID_SYSREG_APM_IPCLKPORT_PCLK 0x20cc +#define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_APM_IPCLKPORT_ACLK 0x20d0 +#define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_APM_IPCLKPORT_PCLK 0x20d4 +#define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_DBGCORE_IPCLKPORT_ACLK 0x20d8 +#define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_DBGCORE_IPCLKPORT_PCLK 0x20dc +#define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_G_SWD_IPCLKPORT_ACLK 0x20e0 +#define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_G_SWD_IPCLKPORT_PCLK 0x20e4 +#define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_AOCAPM_IPCLKPORT_ACLK 0x20e8 +#define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_AOCAPM_IPCLKPORT_PCLK 0x20ec +#define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_APM_IPCLKPORT_ACLK 0x20f0 +#define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_APM_IPCLKPORT_PCLK 0x20f4 +#define CLK_CON_GAT_GOUT_BLK_APM_UID_WDT_APM_IPCLKPORT_PCLK 0x20f8 +#define CLK_CON_GAT_GOUT_BLK_APM_UID_XIU_DP_APM_IPCLKPORT_ACLK 0x20fc +#define PCH_CON_LHM_AXI_G_SWD_PCH 0x3000 +#define PCH_CON_LHM_AXI_P_AOCAPM_PCH 0x3004 +#define PCH_CON_LHM_AXI_P_APM_PCH 0x3008 +#define PCH_CON_LHS_AXI_D_APM_PCH 0x300c +#define PCH_CON_LHS_AXI_G_DBGCORE_PCH 0x3010 +#define PCH_CON_LHS_AXI_G_SCAN2DRAM_PCH 0x3014 +#define QCH_CON_APBIF_GPIO_ALIVE_QCH 0x3018 +#define QCH_CON_APBIF_GPIO_FAR_ALIVE_QCH 0x301c +#define QCH_CON_APBIF_PMU_ALIVE_QCH 0x3020 +#define QCH_CON_APBIF_RTC_QCH 0x3024 +#define QCH_CON_APBIF_TRTC_QCH 0x3028 +#define QCH_CON_APM_CMU_APM_QCH 0x302c +#define QCH_CON_APM_USI0_UART_QCH 0x3030 +#define QCH_CON_APM_USI0_USI_QCH 0x3034 +#define QCH_CON_APM_USI1_UART_QCH 0x3038 +#define QCH_CON_D_TZPC_APM_QCH 0x303c +#define QCH_CON_GPC_APM_QCH 0x3040 +#define QCH_CON_GREBEINTEGRATION_QCH_DBG 0x3044 +#define QCH_CON_GREBEINTEGRATION_QCH_GREBE 0x3048 +#define QCH_CON_INTMEM_QCH 0x304c +#define QCH_CON_LHM_AXI_G_SWD_QCH 0x3050 +#define QCH_CON_LHM_AXI_P_AOCAPM_QCH 0x3054 +#define QCH_CON_LHM_AXI_P_APM_QCH 0x3058 +#define QCH_CON_LHS_AXI_D_APM_QCH 0x305c +#define QCH_CON_LHS_AXI_G_DBGCORE_QCH 0x3060 +#define QCH_CON_LHS_AXI_G_SCAN2DRAM_QCH 0x3064 +#define QCH_CON_MAILBOX_APM_AOC_QCH 0x3068 +#define QCH_CON_MAILBOX_APM_AP_QCH 0x306c +#define QCH_CON_MAILBOX_APM_GSA_QCH 0x3070 +#define QCH_CON_MAILBOX_APM_SWD_QCH 0x3078 +#define QCH_CON_MAILBOX_APM_TPU_QCH 0x307c +#define QCH_CON_MAILBOX_AP_AOC_QCH 0x3080 +#define QCH_CON_MAILBOX_AP_DBGCORE_QCH 0x3084 +#define QCH_CON_PMU_INTR_GEN_QCH 0x3088 +#define QCH_CON_ROM_CRC32_HOST_QCH 0x308c +#define QCH_CON_RSTNSYNC_CLK_APM_BUS_QCH_GREBE 0x3090 +#define QCH_CON_RSTNSYNC_CLK_APM_BUS_QCH_GREBE_DBG 0x3094 +#define QCH_CON_SPEEDY_APM_QCH 0x3098 +#define QCH_CON_SPEEDY_SUB_APM_QCH 0x309c +#define QCH_CON_SSMT_D_APM_QCH 0x30a0 +#define QCH_CON_SSMT_G_DBGCORE_QCH 0x30a4 +#define QCH_CON_SS_DBGCORE_QCH_DBG 0x30a8 +#define QCH_CON_SS_DBGCORE_QCH_GREBE 0x30ac +#define QCH_CON_SYSMMU_D_APM_QCH 0x30b0 +#define QCH_CON_SYSREG_APM_QCH 0x30b8 +#define QCH_CON_UASC_APM_QCH 0x30bc +#define QCH_CON_UASC_DBGCORE_QCH 0x30c0 +#define QCH_CON_UASC_G_SWD_QCH 0x30c4 +#define QCH_CON_UASC_P_AOCAPM_QCH 0x30c8 +#define QCH_CON_UASC_P_APM_QCH 0x30cc +#define QCH_CON_WDT_APM_QCH 0x30d0 +#define QUEUE_CTRL_REG_BLK_APM_CMU_APM 0x3c00 + +static const unsigned long apm_clk_regs[] __initconst = { + APM_CMU_APM_CONTROLLER_OPTION, + CLKOUT_CON_BLK_APM_CMU_APM_CLKOUT0, + CLK_CON_MUX_MUX_CLKCMU_APM_FUNC, + CLK_CON_MUX_MUX_CLKCMU_APM_FUNCSRC, + CLK_CON_DIV_DIV_CLK_APM_BOOST, + CLK_CON_DIV_DIV_CLK_APM_USI0_UART, + CLK_CON_DIV_DIV_CLK_APM_USI0_USI, + CLK_CON_DIV_DIV_CLK_APM_USI1_UART, + CLK_CON_GAT_CLK_BLK_APM_UID_APM_CMU_APM_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BUS0_BOOST_OPTION1, + CLK_CON_GAT_CLK_CMU_BOOST_OPTION1, + CLK_CON_GAT_CLK_CORE_BOOST_OPTION1, + CLK_CON_GAT_GATE_CLKCMU_APM_FUNC, + CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_FAR_ALIVE_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_RTC_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_TRTC_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_UART_IPCLKPORT_IPCLK, + CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_UART_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_USI_IPCLKPORT_IPCLK, + CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_USI_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI1_UART_IPCLKPORT_IPCLK, + CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI1_UART_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_APM_UID_D_TZPC_APM_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_APM_UID_GPC_APM_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_APM_UID_GREBEINTEGRATION_IPCLKPORT_HCLK, + CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_G_SWD_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_AOCAPM_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_D_APM_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_G_DBGCORE_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_G_SCAN2DRAM_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_AOC_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_AP_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_GSA_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_SWD_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_TPU_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP_AOC_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP_DBGCORE_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_APM_UID_PMU_INTR_GEN_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_APM_UID_ROM_CRC32_HOST_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_APM_UID_ROM_CRC32_HOST_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_BUS_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI0_UART_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI0_USI_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI1_UART_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_APM_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_SUB_APM_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_D_APM_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_D_APM_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_G_DBGCORE_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_G_DBGCORE_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_APM_UID_SS_DBGCORE_IPCLKPORT_SS_DBGCORE_IPCLKPORT_HCLK, + CLK_CON_GAT_GOUT_BLK_APM_UID_SYSMMU_D_APM_IPCLKPORT_CLK_S2, + CLK_CON_GAT_GOUT_BLK_APM_UID_SYSREG_APM_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_APM_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_APM_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_DBGCORE_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_DBGCORE_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_G_SWD_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_G_SWD_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_AOCAPM_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_AOCAPM_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_APM_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_APM_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_APM_UID_WDT_APM_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_APM_UID_XIU_DP_APM_IPCLKPORT_ACLK, +}; + +PNAME(mout_apm_func_p) = { "oscclk", "mout_apm_funcsrc", + "pad_clk_apm", "oscclk" }; +PNAME(mout_apm_funcsrc_p) = { "pll_alv_div2_apm", "pll_alv_div4_apm", + "pll_alv_div16_apm" }; + +static const struct samsung_fixed_rate_clock apm_fixed_clks[] __initconst = { + FRATE(CLK_APM_PLL_DIV2_APM, "pll_alv_div2_apm", NULL, 0, 393216000), + FRATE(CLK_APM_PLL_DIV4_APM, "pll_alv_div4_apm", NULL, 0, 196608000), + FRATE(CLK_APM_PLL_DIV16_APM, "pll_alv_div16_apm", NULL, 0, 49152000), +}; + +static const struct samsung_mux_clock apm_mux_clks[] __initconst = { + MUX(CLK_MOUT_APM_FUNC, "mout_apm_func", mout_apm_func_p, + CLK_CON_MUX_MUX_CLKCMU_APM_FUNC, 4, 1), + MUX(CLK_MOUT_APM_FUNCSRC, "mout_apm_funcsrc", mout_apm_funcsrc_p, + CLK_CON_MUX_MUX_CLKCMU_APM_FUNCSRC, 3, 1), +}; + +static const struct samsung_div_clock apm_div_clks[] __initconst = { + DIV(CLK_DOUT_APM_BOOST, "dout_apm_boost", "gout_apm_func", + CLK_CON_DIV_DIV_CLK_APM_BOOST, 0, 1), + DIV(CLK_DOUT_APM_USI0_UART, "dout_apm_usi0_uart", "gout_apm_func", + CLK_CON_DIV_DIV_CLK_APM_USI0_UART, 0, 7), + DIV(CLK_DOUT_APM_USI0_USI, "dout_apm_usi0_usi", "gout_apm_func", + CLK_CON_DIV_DIV_CLK_APM_USI0_USI, 0, 7), + DIV(CLK_DOUT_APM_USI1_UART, "dout_apm_usi1_uart", "gout_apm_func", + CLK_CON_DIV_DIV_CLK_APM_USI1_UART, 0, 7), +}; + +static const struct samsung_gate_clock apm_gate_clks[] __initconst = { + GATE(CLK_GOUT_APM_APM_CMU_APM_PCLK, + "gout_apm_apm_cmu_apm_pclk", "mout_apm_func", + CLK_CON_GAT_CLK_BLK_APM_UID_APM_CMU_APM_IPCLKPORT_PCLK, 21, 0, 0), + GATE(CLK_GOUT_BUS0_BOOST_OPTION1, "gout_bus0_boost_option1", + "dout_apm_boost", CLK_CON_GAT_CLK_BUS0_BOOST_OPTION1, 21, 0, 0), + GATE(CLK_GOUT_CMU_BOOST_OPTION1, "gout_cmu_boost_option1", + "dout_apm_boost", CLK_CON_GAT_CLK_CMU_BOOST_OPTION1, 21, 0, 0), + GATE(CLK_GOUT_CORE_BOOST_OPTION1, "gout_core_boost_option1", + "dout_apm_boost", CLK_CON_GAT_CLK_CORE_BOOST_OPTION1, 21, 0, 0), + GATE(CLK_GOUT_APM_FUNC, "gout_apm_func", "mout_apm_func", + CLK_CON_GAT_GATE_CLKCMU_APM_FUNC, 21, 0, 0), + GATE(CLK_GOUT_APM_APBIF_GPIO_ALIVE_PCLK, + "gout_apm_apbif_gpio_alive_pclk", "gout_apm_func", + CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK, + 21, 0, 0), + GATE(CLK_GOUT_APM_APBIF_GPIO_FAR_ALIVE_PCLK, + "gout_apm_apbif_gpio_far_alive_pclk", "gout_apm_func", + CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_FAR_ALIVE_IPCLKPORT_PCLK, + 21, 0, 0), + GATE(CLK_GOUT_APM_APBIF_PMU_ALIVE_PCLK, + "gout_apm_apbif_pmu_alive_pclk", "gout_apm_func", + CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK, + 21, 0, 0), + GATE(CLK_GOUT_APM_APBIF_RTC_PCLK, + "gout_apm_apbif_rtc_pclk", "gout_apm_func", + CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_RTC_IPCLKPORT_PCLK, 21, 0, 0), + GATE(CLK_GOUT_APM_APBIF_TRTC_PCLK, + "gout_apm_apbif_trtc_pclk", "gout_apm_func", + CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_TRTC_IPCLKPORT_PCLK, 21, 0, 0), + GATE(CLK_GOUT_APM_APM_USI0_UART_IPCLK, + "gout_apm_apm_usi0_uart_ipclk", "dout_apm_usi0_uart", + CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_UART_IPCLKPORT_IPCLK, + 21, 0, 0), + GATE(CLK_GOUT_APM_APM_USI0_UART_PCLK, + "gout_apm_apm_usi0_uart_pclk", "gout_apm_func", + CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_UART_IPCLKPORT_PCLK, + 21, 0, 0), + GATE(CLK_GOUT_APM_APM_USI0_USI_IPCLK, + "gout_apm_apm_usi0_usi_ipclk", "dout_apm_usi0_usi", + CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_USI_IPCLKPORT_IPCLK, + 21, 0, 0), + GATE(CLK_GOUT_APM_APM_USI0_USI_PCLK, + "gout_apm_apm_usi0_usi_pclk", "gout_apm_func", + CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_USI_IPCLKPORT_PCLK, + 21, 0, 0), + GATE(CLK_GOUT_APM_APM_USI1_UART_IPCLK, + "gout_apm_apm_usi1_uart_ipclk", "dout_apm_usi1_uart", + CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI1_UART_IPCLKPORT_IPCLK, + 21, 0, 0), + GATE(CLK_GOUT_APM_APM_USI1_UART_PCLK, + "gout_apm_apm_usi1_uart_pclk", "gout_apm_func", + CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI1_UART_IPCLKPORT_PCLK, + 21, 0, 0), + GATE(CLK_GOUT_APM_D_TZPC_APM_PCLK, + "gout_apm_d_tzpc_apm_pclk", "gout_apm_func", + CLK_CON_GAT_GOUT_BLK_APM_UID_D_TZPC_APM_IPCLKPORT_PCLK, 21, 0, 0), + GATE(CLK_GOUT_APM_GPC_APM_PCLK, + "gout_apm_gpc_apm_pclk", "gout_apm_func", + CLK_CON_GAT_GOUT_BLK_APM_UID_GPC_APM_IPCLKPORT_PCLK, 21, 0, 0), + GATE(CLK_GOUT_APM_GREBEINTEGRATION_HCLK, + "gout_apm_grebeintegration_hclk", "gout_apm_func", + CLK_CON_GAT_GOUT_BLK_APM_UID_GREBEINTEGRATION_IPCLKPORT_HCLK, + 21, 0, 0), + GATE(CLK_GOUT_APM_INTMEM_ACLK, + "gout_apm_intmem_aclk", "gout_apm_func", + CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_ACLK, 21, 0, 0), + GATE(CLK_GOUT_APM_INTMEM_PCLK, + "gout_apm_intmem_pclk", "gout_apm_func", + CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_PCLK, 21, 0, 0), + GATE(CLK_GOUT_APM_LHM_AXI_G_SWD_I_CLK, + "gout_apm_lhm_axi_g_swd_i_clk", "gout_apm_func", + CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_G_SWD_IPCLKPORT_I_CLK, + 21, 0, 0), + GATE(CLK_GOUT_APM_LHM_AXI_P_AOCAPM_I_CLK, + "gout_apm_lhm_axi_p_aocapm_i_clk", "gout_apm_func", + CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_AOCAPM_IPCLKPORT_I_CLK, + 21, 0, 0), + GATE(CLK_GOUT_APM_LHM_AXI_P_APM_I_CLK, + "gout_apm_lhm_axi_p_apm_i_clk", "gout_apm_func", + CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_D_APM_IPCLKPORT_I_CLK, + 21, 0, 0), + GATE(CLK_GOUT_APM_LHS_AXI_D_APM_I_CLK, + "gout_apm_lhs_axi_d_apm_i_clk", "gout_apm_func", + CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_D_APM_IPCLKPORT_I_CLK, + 21, 0, 0), + GATE(CLK_GOUT_APM_LHS_AXI_G_DBGCORE_I_CLK, + "gout_apm_lhs_axi_g_dbgcore_i_clk", "gout_apm_func", + CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_G_DBGCORE_IPCLKPORT_I_CLK, + 21, 0, 0), + GATE(CLK_GOUT_APM_LHS_AXI_G_SCAN2DRAM_I_CLK, + "gout_apm_lhs_axi_g_scan2dram_i_clk", + "gout_apm_func", + CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_G_SCAN2DRAM_IPCLKPORT_I_CLK, + 21, 0, 0), + GATE(CLK_GOUT_APM_MAILBOX_APM_AOC_PCLK, + "gout_apm_mailbox_apm_aoc_pclk", "gout_apm_func", + CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_AOC_IPCLKPORT_PCLK, + 21, 0, 0), + GATE(CLK_GOUT_APM_MAILBOX_APM_AP_PCLK, + "gout_apm_mailbox_apm_ap_pclk", "gout_apm_func", + CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_AP_IPCLKPORT_PCLK, + 21, 0, 0), + GATE(CLK_GOUT_APM_MAILBOX_APM_GSA_PCLK, + "gout_apm_mailbox_apm_gsa_pclk", "gout_apm_func", + CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_GSA_IPCLKPORT_PCLK, + 21, 0, 0), + GATE(CLK_GOUT_APM_MAILBOX_APM_SWD_PCLK, + "gout_apm_mailbox_apm_swd_pclk", "gout_apm_func", + CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_SWD_IPCLKPORT_PCLK, + 21, 0, 0), + GATE(CLK_GOUT_APM_MAILBOX_APM_TPU_PCLK, + "gout_apm_mailbox_apm_tpu_pclk", "gout_apm_func", + CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_TPU_IPCLKPORT_PCLK, + 21, 0, 0), + GATE(CLK_GOUT_APM_MAILBOX_AP_AOC_PCLK, + "gout_apm_mailbox_ap_aoc_pclk", "gout_apm_func", + CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP_AOC_IPCLKPORT_PCLK, + 21, 0, 0), + GATE(CLK_GOUT_APM_MAILBOX_AP_DBGCORE_PCLK, + "gout_apm_mailbox_ap_dbgcore_pclk", "gout_apm_func", + CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP_DBGCORE_IPCLKPORT_PCLK, + 21, 0, 0), + GATE(CLK_GOUT_APM_PMU_INTR_GEN_PCLK, + "gout_apm_pmu_intr_gen_pclk", "gout_apm_func", + CLK_CON_GAT_GOUT_BLK_APM_UID_PMU_INTR_GEN_IPCLKPORT_PCLK, + 21, 0, 0), + GATE(CLK_GOUT_APM_ROM_CRC32_HOST_ACLK, + "gout_apm_rom_crc32_host_aclk", "gout_apm_func", + CLK_CON_GAT_GOUT_BLK_APM_UID_ROM_CRC32_HOST_IPCLKPORT_ACLK, + 21, 0, 0), + GATE(CLK_GOUT_APM_ROM_CRC32_HOST_PCLK, + "gout_apm_rom_crc32_host_pclk", "gout_apm_func", + CLK_CON_GAT_GOUT_BLK_APM_UID_ROM_CRC32_HOST_IPCLKPORT_PCLK, + 21, 0, 0), + GATE(CLK_GOUT_APM_CLK_APM_BUS_CLK, + "gout_apm_clk_apm_bus_clk", "gout_apm_func", + CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_BUS_IPCLKPORT_CLK, + 21, 0, 0), + GATE(CLK_GOUT_APM_CLK_APM_USI0_UART_CLK, + "gout_apm_clk_apm_usi0_uart_clk", + "dout_apm_usi0_uart", + CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI0_UART_IPCLKPORT_CLK, + 21, 0, 0), + GATE(CLK_GOUT_APM_CLK_APM_USI0_USI_CLK, + "gout_apm_clk_apm_usi0_usi_clk", + "dout_apm_usi0_usi", + CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI0_UART_IPCLKPORT_CLK, + 21, 0, 0), + GATE(CLK_GOUT_APM_CLK_APM_USI1_UART_CLK, + "gout_apm_clk_apm_usi1_uart_clk", + "dout_apm_usi1_uart", + CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI1_UART_IPCLKPORT_CLK, + 21, 0, 0), + GATE(CLK_GOUT_APM_SPEEDY_APM_PCLK, + "gout_apm_speedy_apm_pclk", "gout_apm_func", + CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_APM_IPCLKPORT_PCLK, 21, 0, 0), + GATE(CLK_GOUT_APM_SPEEDY_SUB_APM_PCLK, + "gout_apm_speedy_sub_apm_pclk", "gout_apm_func", + CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_SUB_APM_IPCLKPORT_PCLK, + 21, 0, 0), + GATE(CLK_GOUT_APM_SSMT_D_APM_ACLK, + "gout_apm_ssmt_d_apm_aclk", "gout_apm_func", + CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_D_APM_IPCLKPORT_ACLK, 21, 0, 0), + GATE(CLK_GOUT_APM_SSMT_D_APM_PCLK, + "gout_apm_ssmt_d_apm_pclk", "gout_apm_func", + CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_D_APM_IPCLKPORT_PCLK, 21, 0, 0), + GATE(CLK_GOUT_APM_SSMT_G_DBGCORE_ACLK, + "gout_apm_ssmt_g_dbgcore_aclk", "gout_apm_func", + CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_G_DBGCORE_IPCLKPORT_ACLK, + 21, 0, 0), + GATE(CLK_GOUT_APM_SSMT_G_DBGCORE_PCLK, + "gout_apm_ssmt_g_dbgcore_pclk", "gout_apm_func", + CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_G_DBGCORE_IPCLKPORT_PCLK, + 21, 0, 0), + GATE(CLK_GOUT_APM_SS_DBGCORE_SS_DBGCORE_HCLK, + "gout_apm_ss_dbgcore_ss_dbgcore_hclk", + "gout_apm_func", + CLK_CON_GAT_GOUT_BLK_APM_UID_SS_DBGCORE_IPCLKPORT_SS_DBGCORE_IPCLKPORT_HCLK, + 21, 0, 0), + GATE(CLK_GOUT_APM_SYSMMU_D_APM_CLK_S2, + "gout_apm_sysmmu_d_dpm_clk_s2", "gout_apm_func", + CLK_CON_GAT_GOUT_BLK_APM_UID_SYSMMU_D_APM_IPCLKPORT_CLK_S2, + 21, 0, 0), + GATE(CLK_GOUT_APM_SYSREG_APM_PCLK, + "gout_apm_sysreg_apm_pclk", "gout_apm_func", + CLK_CON_GAT_GOUT_BLK_APM_UID_SYSREG_APM_IPCLKPORT_PCLK, 21, 0, 0), + GATE(CLK_GOUT_APM_UASC_APM_ACLK, + "gout_apm_uasc_apm_aclk", "gout_apm_func", + CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_APM_IPCLKPORT_ACLK, 21, 0, 0), + GATE(CLK_GOUT_APM_UASC_APM_PCLK, + "gout_apm_uasc_apm_pclk", "gout_apm_func", + CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_APM_IPCLKPORT_PCLK, 21, 0, 0), + GATE(CLK_GOUT_APM_UASC_DBGCORE_ACLK, + "gout_apm_uasc_dbgcore_aclk", "gout_apm_func", + CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_DBGCORE_IPCLKPORT_ACLK, + 21, 0, 0), + GATE(CLK_GOUT_APM_UASC_DBGCORE_PCLK, + "gout_apm_uasc_dbgcore_pclk", "gout_apm_func", + CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_DBGCORE_IPCLKPORT_PCLK, + 21, 0, 0), + GATE(CLK_GOUT_APM_UASC_G_SWD_ACLK, + "gout_apm_uasc_g_swd_aclk", "gout_apm_func", + CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_G_SWD_IPCLKPORT_ACLK, 21, 0, 0), + GATE(CLK_GOUT_APM_UASC_G_SWD_PCLK, + "gout_apm_uasc_g_swd_pclk", "gout_apm_func", + CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_G_SWD_IPCLKPORT_PCLK, 21, 0, 0), + GATE(CLK_GOUT_APM_UASC_P_AOCAPM_ACLK, + "gout_apm_uasc_p_aocapm_aclk", "gout_apm_func", + CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_AOCAPM_IPCLKPORT_ACLK, + 21, 0, 0), + GATE(CLK_GOUT_APM_UASC_P_AOCAPM_PCLK, + "gout_apm_uasc_p_aocapm_pclk", "gout_apm_func", + CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_G_SWD_IPCLKPORT_PCLK, 21, 0, 0), + GATE(CLK_GOUT_APM_UASC_P_APM_ACLK, + "gout_apm_uasc_p_apm_aclk", "gout_apm_func", + CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_APM_IPCLKPORT_ACLK, 21, 0, 0), + GATE(CLK_GOUT_APM_UASC_P_APM_PCLK, + "gout_apm_uasc_p_apm_pclk", "gout_apm_func", + CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_APM_IPCLKPORT_PCLK, 21, 0, 0), + GATE(CLK_GOUT_APM_WDT_APM_PCLK, + "gout_apm_wdt_apm_pclk", "gout_apm_func", + CLK_CON_GAT_GOUT_BLK_APM_UID_WDT_APM_IPCLKPORT_PCLK, 21, 0, 0), + GATE(CLK_GOUT_APM_XIU_DP_APM_ACLK, + "gout_apm_xiu_dp_apm_aclk", "gout_apm_func", + CLK_CON_GAT_GOUT_BLK_APM_UID_XIU_DP_APM_IPCLKPORT_ACLK, 21, 0, 0), +}; + +static const struct samsung_cmu_info apm_cmu_info __initconst = { + .mux_clks = apm_mux_clks, + .nr_mux_clks = ARRAY_SIZE(apm_mux_clks), + .div_clks = apm_div_clks, + .nr_div_clks = ARRAY_SIZE(apm_div_clks), + .gate_clks = apm_gate_clks, + .nr_gate_clks = ARRAY_SIZE(apm_gate_clks), + .fixed_clks = apm_fixed_clks, + .nr_fixed_clks = ARRAY_SIZE(apm_fixed_clks), + .nr_clk_ids = CLKS_NR_APM, + .clk_regs = apm_clk_regs, + .nr_clk_regs = ARRAY_SIZE(apm_clk_regs), +}; + +/* ---- CMU_MISC ------------------------------------------------------------ */ + +/* Register Offset definitions for CMU_MISC (0x10010000) */ +#define PLL_CON0_MUX_CLKCMU_MISC_BUS_USER 0x0600 +#define PLL_CON1_MUX_CLKCMU_MISC_BUS_USER 0x0604 +#define PLL_CON0_MUX_CLKCMU_MISC_SSS_USER 0x0610 +#define PLL_CON1_MUX_CLKCMU_MISC_SSS_USER 0x0614 +#define MISC_CMU_MISC_CONTROLLER_OPTION 0x0800 +#define CLKOUT_CON_BLK_MISC_CMU_MISC_CLKOUT0 0x0810 +#define CLK_CON_MUX_MUX_CLK_MISC_GIC 0x1000 +#define CLK_CON_DIV_DIV_CLK_MISC_BUSP 0x1800 +#define CLK_CON_DIV_DIV_CLK_MISC_GIC 0x1804 +#define CLK_CON_GAT_CLK_BLK_MISC_UID_MISC_CMU_MISC_IPCLKPORT_PCLK 0x2000 +#define CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_BIRA_IPCLKPORT_I_OSCCLK 0x2004 +#define CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_BISR_IPCLKPORT_I_OSCCLK 0x2008 +#define CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_TOP_IPCLKPORT_I_OSCCLK 0x200c +#define CLK_CON_GAT_CLK_BLK_MISC_UID_RSTNSYNC_CLK_MISC_OSCCLK_IPCLKPORT_CLK 0x2010 +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_ADM_AHB_SSS_IPCLKPORT_HCLKM 0x2014 +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_AD_APB_DIT_IPCLKPORT_PCLKM 0x2018 +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_AD_APB_PUF_IPCLKPORT_PCLKM 0x201c +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_DIT_IPCLKPORT_ICLKL2A 0x2020 +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_D_TZPC_MISC_IPCLKPORT_PCLK 0x2024 +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_GIC_IPCLKPORT_GICCLK 0x2028 +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_GPC_MISC_IPCLKPORT_PCLK 0x202c +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AST_ICC_CPUGIC_IPCLKPORT_I_CLK 0x2030 +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AXI_D_SSS_IPCLKPORT_I_CLK 0x2034 +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AXI_P_GIC_IPCLKPORT_I_CLK 0x2038 +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AXI_P_MISC_IPCLKPORT_I_CLK 0x203c +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_LHS_ACEL_D_MISC_IPCLKPORT_I_CLK 0x2040 +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_LHS_AST_IRI_GICCPU_IPCLKPORT_I_CLK 0x2044 +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_LHS_AXI_D_SSS_IPCLKPORT_I_CLK 0x2048 +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_MCT_IPCLKPORT_PCLK 0x204c +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_BIRA_IPCLKPORT_PCLK 0x2050 +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_BISR_IPCLKPORT_PCLK 0x2054 +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_TOP_IPCLKPORT_PCLK 0x2058 +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_PDMA_IPCLKPORT_ACLK 0x205c +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_PPMU_DMA_IPCLKPORT_ACLK 0x2060 +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_PPMU_MISC_IPCLKPORT_ACLK 0x2064 +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_PPMU_MISC_IPCLKPORT_PCLK 0x2068 +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_PUF_IPCLKPORT_I_CLK 0x206c +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_DIT_IPCLKPORT_ACLK 0x2070 +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_DIT_IPCLKPORT_PCLK 0x2074 +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PDMA_IPCLKPORT_ACLK 0x2078 +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PDMA_IPCLKPORT_PCLK 0x207c +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PPMU_DMA_IPCLKPORT_ACLK 0x2080 +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PPMU_DMA_IPCLKPORT_PCLK 0x2084 +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_RTIC_IPCLKPORT_ACLK 0x2088 +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_RTIC_IPCLKPORT_PCLK 0x208c +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SPDMA_IPCLKPORT_ACLK 0x2090 +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SPDMA_IPCLKPORT_PCLK 0x2094 +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SSS_IPCLKPORT_ACLK 0x2098 +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SSS_IPCLKPORT_PCLK 0x209c +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_BUSD_IPCLKPORT_CLK 0x20a0 +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_BUSP_IPCLKPORT_CLK 0x20a4 +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_GIC_IPCLKPORT_CLK 0x20a8 +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_SSS_IPCLKPORT_CLK 0x20ac +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_RTIC_IPCLKPORT_I_ACLK 0x20b0 +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_RTIC_IPCLKPORT_I_PCLK 0x20b4 +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SPDMA_IPCLKPORT_ACLK 0x20b8 +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_DIT_IPCLKPORT_ACLK 0x20bc +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_DIT_IPCLKPORT_PCLK 0x20c0 +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PDMA_IPCLKPORT_ACLK 0x20c4 +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PDMA_IPCLKPORT_PCLK 0x20c8 +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PPMU_DMA_IPCLKPORT_ACLK 0x20cc +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PPMU_DMA_IPCLKPORT_PCLK 0x20d0 +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_RTIC_IPCLKPORT_ACLK 0x20d4 +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_RTIC_IPCLKPORT_PCLK 0x20d8 +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SPDMA_IPCLKPORT_ACLK 0x20dc +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SPDMA_IPCLKPORT_PCLK 0x20e0 +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SSS_IPCLKPORT_ACLK 0x20e4 +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SSS_IPCLKPORT_PCLK 0x20e8 +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSS_IPCLKPORT_I_ACLK 0x20ec +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSS_IPCLKPORT_I_PCLK 0x20f0 +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSMMU_MISC_IPCLKPORT_CLK_S2 0x20f4 +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSMMU_SSS_IPCLKPORT_CLK_S1 0x20f8 +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSREG_MISC_IPCLKPORT_PCLK 0x20fc +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_TMU_SUB_IPCLKPORT_PCLK 0x2100 +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_TMU_TOP_IPCLKPORT_PCLK 0x2104 +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_WDT_CLUSTER0_IPCLKPORT_PCLK 0x2108 +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_WDT_CLUSTER1_IPCLKPORT_PCLK 0x210c +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_XIU_D_MISC_IPCLKPORT_ACLK 0x2110 +#define DMYQCH_CON_PPMU_DMA_QCH 0x3000 +#define DMYQCH_CON_PUF_QCH 0x3004 +#define PCH_CON_LHM_AXI_D_SSS_PCH 0x300c +#define PCH_CON_LHM_AXI_P_GIC_PCH 0x3010 +#define PCH_CON_LHM_AXI_P_MISC_PCH 0x3014 +#define PCH_CON_LHS_ACEL_D_MISC_PCH 0x3018 +#define PCH_CON_LHS_AST_IRI_GICCPU_PCH 0x301c +#define PCH_CON_LHS_AXI_D_SSS_PCH 0x3020 +#define QCH_CON_ADM_AHB_SSS_QCH 0x3024 +#define QCH_CON_DIT_QCH 0x3028 +#define QCH_CON_GIC_QCH 0x3030 +#define QCH_CON_LHM_AST_ICC_CPUGIC_QCH 0x3038 +#define QCH_CON_LHM_AXI_D_SSS_QCH 0x303c +#define QCH_CON_LHM_AXI_P_GIC_QCH 0x3040 +#define QCH_CON_LHM_AXI_P_MISC_QCH 0x3044 +#define QCH_CON_LHS_ACEL_D_MISC_QCH 0x3048 +#define QCH_CON_LHS_AST_IRI_GICCPU_QCH 0x304c +#define QCH_CON_LHS_AXI_D_SSS_QCH 0x3050 +#define QCH_CON_MCT_QCH 0x3054 +#define QCH_CON_MISC_CMU_MISC_QCH 0x3058 +#define QCH_CON_OTP_CON_BIRA_QCH 0x305c +#define QCH_CON_OTP_CON_BISR_QCH 0x3060 +#define QCH_CON_OTP_CON_TOP_QCH 0x3064 +#define QCH_CON_PDMA_QCH 0x3068 +#define QCH_CON_PPMU_MISC_QCH 0x306c +#define QCH_CON_QE_DIT_QCH 0x3070 +#define QCH_CON_QE_PDMA_QCH 0x3074 +#define QCH_CON_QE_PPMU_DMA_QCH 0x3078 +#define QCH_CON_QE_RTIC_QCH 0x307c +#define QCH_CON_QE_SPDMA_QCH 0x3080 +#define QCH_CON_QE_SSS_QCH 0x3084 +#define QCH_CON_RTIC_QCH 0x3088 +#define QCH_CON_SPDMA_QCH 0x308c +#define QCH_CON_SSMT_DIT_QCH 0x3090 +#define QCH_CON_SSMT_PDMA_QCH 0x3094 +#define QCH_CON_SSMT_PPMU_DMA_QCH 0x3098 +#define QCH_CON_SSMT_RTIC_QCH 0x309c +#define QCH_CON_SSMT_SPDMA_QCH 0x30a0 +#define QCH_CON_SSMT_SSS_QCH 0x30a4 +#define QCH_CON_SSS_QCH 0x30a8 +#define QCH_CON_SYSMMU_MISC_QCH 0x30ac +#define QCH_CON_SYSMMU_SSS_QCH 0x30b0 +#define QCH_CON_SYSREG_MISC_QCH 0x30b4 +#define QCH_CON_TMU_SUB_QCH 0x30b8 +#define QCH_CON_TMU_TOP_QCH 0x30bc +#define QCH_CON_WDT_CLUSTER0_QCH 0x30c0 +#define QCH_CON_WDT_CLUSTER1_QCH 0x30c4 +#define QUEUE_CTRL_REG_BLK_MISC_CMU_MISC 0x3c00 + +static const unsigned long misc_clk_regs[] __initconst = { + PLL_CON0_MUX_CLKCMU_MISC_BUS_USER, + PLL_CON1_MUX_CLKCMU_MISC_BUS_USER, + PLL_CON0_MUX_CLKCMU_MISC_SSS_USER, + PLL_CON1_MUX_CLKCMU_MISC_SSS_USER, + MISC_CMU_MISC_CONTROLLER_OPTION, + CLKOUT_CON_BLK_MISC_CMU_MISC_CLKOUT0, + CLK_CON_MUX_MUX_CLK_MISC_GIC, + CLK_CON_DIV_DIV_CLK_MISC_BUSP, + CLK_CON_DIV_DIV_CLK_MISC_GIC, + CLK_CON_GAT_CLK_BLK_MISC_UID_MISC_CMU_MISC_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_BIRA_IPCLKPORT_I_OSCCLK, + CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_BISR_IPCLKPORT_I_OSCCLK, + CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_TOP_IPCLKPORT_I_OSCCLK, + CLK_CON_GAT_CLK_BLK_MISC_UID_RSTNSYNC_CLK_MISC_OSCCLK_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_MISC_UID_ADM_AHB_SSS_IPCLKPORT_HCLKM, + CLK_CON_GAT_GOUT_BLK_MISC_UID_AD_APB_DIT_IPCLKPORT_PCLKM, + CLK_CON_GAT_GOUT_BLK_MISC_UID_AD_APB_PUF_IPCLKPORT_PCLKM, + CLK_CON_GAT_GOUT_BLK_MISC_UID_DIT_IPCLKPORT_ICLKL2A, + CLK_CON_GAT_GOUT_BLK_MISC_UID_D_TZPC_MISC_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_MISC_UID_GIC_IPCLKPORT_GICCLK, + CLK_CON_GAT_GOUT_BLK_MISC_UID_GPC_MISC_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AST_ICC_CPUGIC_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AXI_D_SSS_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AXI_P_GIC_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AXI_P_MISC_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_MISC_UID_LHS_ACEL_D_MISC_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_MISC_UID_LHS_AST_IRI_GICCPU_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_MISC_UID_LHS_AXI_D_SSS_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_MISC_UID_MCT_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_BIRA_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_BISR_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_TOP_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_MISC_UID_PDMA_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_MISC_UID_PPMU_DMA_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_MISC_UID_PPMU_MISC_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_MISC_UID_PPMU_MISC_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_MISC_UID_PUF_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_DIT_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_DIT_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PDMA_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PDMA_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PPMU_DMA_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PPMU_DMA_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_RTIC_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_RTIC_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SPDMA_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SPDMA_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SSS_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SSS_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_BUSD_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_BUSP_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_GIC_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_SSS_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_MISC_UID_RTIC_IPCLKPORT_I_ACLK, + CLK_CON_GAT_GOUT_BLK_MISC_UID_RTIC_IPCLKPORT_I_PCLK, + CLK_CON_GAT_GOUT_BLK_MISC_UID_SPDMA_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_DIT_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_DIT_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PDMA_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PDMA_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PPMU_DMA_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PPMU_DMA_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_RTIC_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_RTIC_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SPDMA_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SPDMA_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SSS_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SSS_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_MISC_UID_SSS_IPCLKPORT_I_ACLK, + CLK_CON_GAT_GOUT_BLK_MISC_UID_SSS_IPCLKPORT_I_PCLK, + CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSMMU_MISC_IPCLKPORT_CLK_S2, + CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSMMU_SSS_IPCLKPORT_CLK_S1, + CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSREG_MISC_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_MISC_UID_TMU_SUB_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_MISC_UID_TMU_TOP_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_MISC_UID_WDT_CLUSTER0_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_MISC_UID_WDT_CLUSTER1_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_MISC_UID_XIU_D_MISC_IPCLKPORT_ACLK, + DMYQCH_CON_PPMU_DMA_QCH, + DMYQCH_CON_PUF_QCH, + PCH_CON_LHM_AXI_D_SSS_PCH, + PCH_CON_LHM_AXI_P_GIC_PCH, + PCH_CON_LHM_AXI_P_MISC_PCH, + PCH_CON_LHS_ACEL_D_MISC_PCH, + PCH_CON_LHS_AST_IRI_GICCPU_PCH, + PCH_CON_LHS_AXI_D_SSS_PCH, + QCH_CON_ADM_AHB_SSS_QCH, + QCH_CON_DIT_QCH, + QCH_CON_GIC_QCH, + QCH_CON_LHM_AST_ICC_CPUGIC_QCH, + QCH_CON_LHM_AXI_D_SSS_QCH, + QCH_CON_LHM_AXI_P_GIC_QCH, + QCH_CON_LHM_AXI_P_MISC_QCH, + QCH_CON_LHS_ACEL_D_MISC_QCH, + QCH_CON_LHS_AST_IRI_GICCPU_QCH, + QCH_CON_LHS_AXI_D_SSS_QCH, + QCH_CON_MCT_QCH, + QCH_CON_MISC_CMU_MISC_QCH, + QCH_CON_OTP_CON_BIRA_QCH, + QCH_CON_OTP_CON_BISR_QCH, + QCH_CON_OTP_CON_TOP_QCH, + QCH_CON_PDMA_QCH, + QCH_CON_PPMU_MISC_QCH, + QCH_CON_QE_DIT_QCH, + QCH_CON_QE_PDMA_QCH, + QCH_CON_QE_PPMU_DMA_QCH, + QCH_CON_QE_RTIC_QCH, + QCH_CON_QE_SPDMA_QCH, + QCH_CON_QE_SSS_QCH, + QCH_CON_RTIC_QCH, + QCH_CON_SPDMA_QCH, + QCH_CON_SSMT_DIT_QCH, + QCH_CON_SSMT_PDMA_QCH, + QCH_CON_SSMT_PPMU_DMA_QCH, + QCH_CON_SSMT_RTIC_QCH, + QCH_CON_SSMT_SPDMA_QCH, + QCH_CON_SSMT_SSS_QCH, + QCH_CON_SSS_QCH, + QCH_CON_SYSMMU_MISC_QCH, + QCH_CON_SYSMMU_SSS_QCH, + QCH_CON_SYSREG_MISC_QCH, + QCH_CON_TMU_SUB_QCH, + QCH_CON_TMU_TOP_QCH, + QCH_CON_WDT_CLUSTER0_QCH, + QCH_CON_WDT_CLUSTER1_QCH, + QUEUE_CTRL_REG_BLK_MISC_CMU_MISC, +}; + + /* List of parent clocks for Muxes in CMU_MISC */ +PNAME(mout_misc_bus_user_p) = { "oscclk", "dout_cmu_misc_bus" }; +PNAME(mout_misc_sss_user_p) = { "oscclk", "dout_cmu_misc_sss" }; +PNAME(mout_misc_gic_p) = { "dout_misc_gic", "oscclk" }; + +static const struct samsung_mux_clock misc_mux_clks[] __initconst = { + MUX(CLK_MOUT_MISC_BUS_USER, "mout_misc_bus_user", mout_misc_bus_user_p, + PLL_CON0_MUX_CLKCMU_MISC_BUS_USER, 4, 1), + MUX(CLK_MOUT_MISC_SSS_USER, "mout_misc_sss_user", mout_misc_sss_user_p, + PLL_CON0_MUX_CLKCMU_MISC_SSS_USER, 4, 1), + MUX(CLK_MOUT_MISC_GIC, "mout_misc_gic", mout_misc_gic_p, + CLK_CON_MUX_MUX_CLK_MISC_GIC, 0, 0), +}; + +static const struct samsung_div_clock misc_div_clks[] __initconst = { + DIV(CLK_DOUT_MISC_BUSP, "dout_misc_busp", "mout_misc_bus_user", + CLK_CON_DIV_DIV_CLK_MISC_BUSP, 0, 3), + DIV(CLK_DOUT_MISC_GIC, "dout_misc_gic", "mout_misc_bus_user", + CLK_CON_DIV_DIV_CLK_MISC_GIC, 0, 3), +}; + +static const struct samsung_gate_clock misc_gate_clks[] __initconst = { + GATE(CLK_GOUT_MISC_MISC_CMU_MISC_PCLK, + "gout_misc_misc_cmu_misc_pclk", "dout_misc_busp", + CLK_CON_GAT_CLK_BLK_MISC_UID_MISC_CMU_MISC_IPCLKPORT_PCLK, + 21, 0, 0), + GATE(CLK_GOUT_MISC_OTP_CON_BIRA_I_OSCCLK, + "gout_misc_otp_con_bira_i_oscclk", "oscclk", + CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_BIRA_IPCLKPORT_I_OSCCLK, + 21, 0, 0), + GATE(CLK_GOUT_MISC_OTP_CON_BISR_I_OSCCLK, + "gout_misc_otp_con_bisr_i_oscclk", "oscclk", + CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_BISR_IPCLKPORT_I_OSCCLK, + 21, 0, 0), + GATE(CLK_GOUT_MISC_OTP_CON_TOP_I_OSCCLK, + "gout_misc_otp_con_top_i_oscclk", "oscclk", + CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_TOP_IPCLKPORT_I_OSCCLK, + 21, 0, 0), + GATE(CLK_GOUT_MISC_CLK_MISC_OSCCLK_CLK, + "gout_misc_clk_misc_oscclk_clk", "oscclk", + CLK_CON_GAT_CLK_BLK_MISC_UID_RSTNSYNC_CLK_MISC_OSCCLK_IPCLKPORT_CLK, + 21, 0, 0), + GATE(CLK_GOUT_MISC_ADM_AHB_SSS_HCLKM, + "gout_misc_adm_ahb_sss_hclkm", "mout_misc_sss_user", + CLK_CON_GAT_GOUT_BLK_MISC_UID_ADM_AHB_SSS_IPCLKPORT_HCLKM, + 21, 0, 0), + GATE(CLK_GOUT_MISC_AD_APB_DIT_PCLKM, + "gout_misc_ad_apb_dit_pclkm", "mout_misc_bus_user", + CLK_CON_GAT_GOUT_BLK_MISC_UID_AD_APB_DIT_IPCLKPORT_PCLKM, + 21, 0, 0), + GATE(CLK_GOUT_MISC_D_TZPC_MISC_PCLK, + "gout_misc_d_tzpc_misc_pclk", "dout_misc_busp", + CLK_CON_GAT_GOUT_BLK_MISC_UID_D_TZPC_MISC_IPCLKPORT_PCLK, + 21, 0, 0), + GATE(CLK_GOUT_MISC_GIC_GICCLK, + "gout_misc_gic_gicclk", "mout_misc_gic", + CLK_CON_GAT_GOUT_BLK_MISC_UID_GIC_IPCLKPORT_GICCLK, + 21, 0, 0), + GATE(CLK_GOUT_MISC_GPC_MISC_PCLK, + "gout_misc_gpc_misc_pclk", "dout_misc_busp", + CLK_CON_GAT_GOUT_BLK_MISC_UID_GPC_MISC_IPCLKPORT_PCLK, + 21, 0, 0), + GATE(CLK_GOUT_MISC_LHM_AST_ICC_CPUGIC_I_CLK, + "gout_misc_lhm_ast_icc_gpugic_i_clk", "mout_misc_gic", + CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AST_ICC_CPUGIC_IPCLKPORT_I_CLK, + 21, 0, 0), + GATE(CLK_GOUT_MISC_LHM_AXI_D_SSS_I_CLK, + "gout_misc_lhm_axi_d_sss_i_clk", "mout_misc_bus_user", + CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AXI_D_SSS_IPCLKPORT_I_CLK, + 21, 0, 0), + GATE(CLK_GOUT_MISC_LHM_AXI_P_GIC_I_CLK, + "gout_misc_lhm_axi_p_gic_i_clk", "mout_misc_gic", + CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AXI_P_GIC_IPCLKPORT_I_CLK, + 21, 0, 0), + GATE(CLK_GOUT_MISC_LHM_AXI_P_MISC_I_CLK, + "gout_misc_lhm_axi_p_misc_i_clk", "dout_misc_busp", + CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AXI_P_MISC_IPCLKPORT_I_CLK, + 21, 0, 0), + GATE(CLK_GOUT_MISC_LHS_ACEL_D_MISC_I_CLK, + "gout_misc_lhs_acel_d_misc_i_clk", "mout_misc_bus_user", + CLK_CON_GAT_GOUT_BLK_MISC_UID_LHS_ACEL_D_MISC_IPCLKPORT_I_CLK, + 21, 0, 0), + GATE(CLK_GOUT_MISC_LHS_AST_IRI_GICCPU_I_CLK, + "gout_misc_lhs_ast_iri_giccpu_i_clk", "mout_misc_gic", + CLK_CON_GAT_GOUT_BLK_MISC_UID_LHS_AST_IRI_GICCPU_IPCLKPORT_I_CLK, + 21, 0, 0), + GATE(CLK_GOUT_MISC_LHS_AXI_D_SSS_I_CLK, + "gout_misc_lhs_axi_d_sss_i_clk", "mout_misc_sss_user", + CLK_CON_GAT_GOUT_BLK_MISC_UID_LHS_AXI_D_SSS_IPCLKPORT_I_CLK, + 21, 0, 0), + GATE(CLK_GOUT_MISC_MCT_PCLK, "gout_misc_mct_pclk", + "dout_misc_busp", + CLK_CON_GAT_GOUT_BLK_MISC_UID_MCT_IPCLKPORT_PCLK, + 21, 0, 0), + GATE(CLK_GOUT_MISC_OTP_CON_BIRA_PCLK, + "gout_misc_otp_con_bira_pclk", "dout_misc_busp", + CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_BIRA_IPCLKPORT_PCLK, + 21, 0, 0), + GATE(CLK_GOUT_MISC_OTP_CON_BISR_PCLK, + "gout_misc_otp_con_bisr_pclk", "dout_misc_busp", + CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_BISR_IPCLKPORT_PCLK, + 21, 0, 0), + GATE(CLK_GOUT_MISC_OTP_CON_TOP_PCLK, + "gout_misc_otp_con_top_pclk", "dout_misc_busp", + CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_TOP_IPCLKPORT_PCLK, + 21, 0, 0), + GATE(CLK_GOUT_MISC_PDMA_ACLK, "gout_misc_pdma_aclk", + "mout_misc_bus_user", + CLK_CON_GAT_GOUT_BLK_MISC_UID_PDMA_IPCLKPORT_ACLK, + 21, 0, 0), + GATE(CLK_GOUT_MISC_PPMU_MISC_ACLK, + "gout_misc_ppmu_misc_aclk", "mout_misc_bus_user", + CLK_CON_GAT_GOUT_BLK_MISC_UID_PPMU_MISC_IPCLKPORT_ACLK, + 21, 0, 0), + GATE(CLK_GOUT_MISC_PPMU_MISC_PCLK, + "gout_misc_ppmu_misc_pclk", "dout_misc_busp", + CLK_CON_GAT_GOUT_BLK_MISC_UID_PPMU_MISC_IPCLKPORT_PCLK, + 21, 0, 0), + GATE(CLK_GOUT_MISC_PUF_I_CLK, + "gout_misc_puf_i_clk", "mout_misc_sss_user", + CLK_CON_GAT_GOUT_BLK_MISC_UID_PUF_IPCLKPORT_I_CLK, + 21, 0, 0), + GATE(CLK_GOUT_MISC_QE_DIT_ACLK, + "gout_misc_qe_dit_aclk", "mout_misc_bus_user", + CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_DIT_IPCLKPORT_ACLK, + 21, 0, 0), + GATE(CLK_GOUT_MISC_QE_DIT_PCLK, + "gout_misc_qe_dit_pclk", "dout_misc_busp", + CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_DIT_IPCLKPORT_PCLK, + 21, 0, 0), + GATE(CLK_GOUT_MISC_QE_PDMA_ACLK, + "gout_misc_qe_pdma_aclk", "mout_misc_bus_user", + CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PDMA_IPCLKPORT_ACLK, + 21, 0, 0), + GATE(CLK_GOUT_MISC_QE_PDMA_PCLK, + "gout_misc_qe_pdma_pclk", "dout_misc_busp", + CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PDMA_IPCLKPORT_PCLK, + 21, 0, 0), + GATE(CLK_GOUT_MISC_QE_PPMU_DMA_ACLK, + "gout_misc_qe_ppmu_dma_aclk", "mout_misc_bus_user", + CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PPMU_DMA_IPCLKPORT_ACLK, + 21, 0, 0), + GATE(CLK_GOUT_MISC_QE_PPMU_DMA_PCLK, + "gout_misc_qe_ppmu_dma_pclk", "dout_misc_busp", + CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PPMU_DMA_IPCLKPORT_PCLK, + 21, 0, 0), + GATE(CLK_GOUT_MISC_QE_RTIC_ACLK, + "gout_misc_qe_rtic_aclk", "mout_misc_bus_user", + CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_RTIC_IPCLKPORT_ACLK, + 21, 0, 0), + GATE(CLK_GOUT_MISC_QE_RTIC_PCLK, + "gout_misc_qe_rtic_pclk", "dout_misc_busp", + CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_RTIC_IPCLKPORT_PCLK, + 21, 0, 0), + GATE(CLK_GOUT_MISC_QE_SPDMA_ACLK, + "gout_misc_qe_spdma_aclk", "mout_misc_bus_user", + CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SPDMA_IPCLKPORT_ACLK, + 21, 0, 0), + GATE(CLK_GOUT_MISC_QE_SPDMA_PCLK, + "gout_misc_qe_spdma_pclk", "dout_misc_busp", + CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SPDMA_IPCLKPORT_PCLK, + 21, 0, 0), + GATE(CLK_GOUT_MISC_QE_SSS_ACLK, + "gout_misc_qe_sss_aclk", "mout_misc_sss_user", + CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SSS_IPCLKPORT_ACLK, + 21, 0, 0), + GATE(CLK_GOUT_MISC_QE_SSS_PCLK, + "gout_misc_qe_sss_pclk", "dout_misc_busp", + CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SSS_IPCLKPORT_PCLK, + 21, 0, 0), + GATE(CLK_GOUT_MISC_CLK_MISC_BUSD_CLK, + "gout_misc_clk_misc_busd_clk", "mout_misc_bus_user", + CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_BUSD_IPCLKPORT_CLK, + 21, 0, 0), + GATE(CLK_GOUT_MISC_CLK_MISC_BUSP_CLK, + "gout_misc_clk_misc_busp_clk", "dout_misc_busp", + CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_BUSP_IPCLKPORT_CLK, + 21, 0, 0), + GATE(CLK_GOUT_MISC_CLK_MISC_GIC_CLK, + "gout_misc_clk_misc_gic_clk", "mout_misc_gic", + CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_GIC_IPCLKPORT_CLK, + 21, 0, 0), + GATE(CLK_GOUT_MISC_CLK_MISC_SSS_CLK, + "gout_misc_clk_misc_sss_clk", "mout_misc_sss_user", + CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_SSS_IPCLKPORT_CLK, + 21, 0, 0), + GATE(CLK_GOUT_MISC_RTIC_I_ACLK, + "gout_misc_rtic_i_aclk", "mout_misc_bus_user", + CLK_CON_GAT_GOUT_BLK_MISC_UID_RTIC_IPCLKPORT_I_ACLK, + 21, 0, 0), + GATE(CLK_GOUT_MISC_RTIC_I_PCLK, "gout_misc_rtic_i_pclk", + "dout_misc_busp", + CLK_CON_GAT_GOUT_BLK_MISC_UID_RTIC_IPCLKPORT_I_PCLK, + 21, 0, 0), + GATE(CLK_GOUT_MISC_SPDMA_ACLK, + "gout_misc_spdma_ipclockport_aclk", "mout_misc_bus_user", + CLK_CON_GAT_GOUT_BLK_MISC_UID_SPDMA_IPCLKPORT_ACLK, + 21, 0, 0), + GATE(CLK_GOUT_MISC_SSMT_DIT_ACLK, + "gout_misc_ssmt_dit_aclk", "mout_misc_bus_user", + CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_DIT_IPCLKPORT_ACLK, + 21, 0, 0), + GATE(CLK_GOUT_MISC_SSMT_DIT_PCLK, + "gout_misc_ssmt_dit_pclk", "dout_misc_busp", + CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_DIT_IPCLKPORT_PCLK, + 21, 0, 0), + GATE(CLK_GOUT_MISC_SSMT_PDMA_ACLK, + "gout_misc_ssmt_pdma_aclk", "mout_misc_bus_user", + CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PDMA_IPCLKPORT_ACLK, + 21, 0, 0), + GATE(CLK_GOUT_MISC_SSMT_PDMA_PCLK, + "gout_misc_ssmt_pdma_pclk", "dout_misc_busp", + CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PDMA_IPCLKPORT_PCLK, + 21, 0, 0), + GATE(CLK_GOUT_MISC_SSMT_PPMU_DMA_ACLK, + "gout_misc_ssmt_ppmu_dma_aclk", "mout_misc_bus_user", + CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PPMU_DMA_IPCLKPORT_ACLK, + 21, 0, 0), + GATE(CLK_GOUT_MISC_SSMT_PPMU_DMA_PCLK, + "gout_misc_ssmt_ppmu_dma_pclk", "dout_misc_busp", + CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PPMU_DMA_IPCLKPORT_PCLK, + 21, 0, 0), + GATE(CLK_GOUT_MISC_SSMT_RTIC_ACLK, + "gout_misc_ssmt_rtic_aclk", "mout_misc_bus_user", + CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_RTIC_IPCLKPORT_ACLK, + 21, 0, 0), + GATE(CLK_GOUT_MISC_SSMT_RTIC_PCLK, + "gout_misc_ssmt_rtic_pclk", "dout_misc_busp", + CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_RTIC_IPCLKPORT_PCLK, + 21, 0, 0), + GATE(CLK_GOUT_MISC_SSMT_SPDMA_ACLK, + "gout_misc_ssmt_spdma_aclk", "mout_misc_bus_user", + CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SPDMA_IPCLKPORT_ACLK, + 21, 0, 0), + GATE(CLK_GOUT_MISC_SSMT_SPDMA_PCLK, + "gout_misc_ssmt_spdma_pclk", "dout_misc_busp", + CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SPDMA_IPCLKPORT_PCLK, + 21, 0, 0), + GATE(CLK_GOUT_MISC_SSMT_SSS_ACLK, + "gout_misc_ssmt_sss_aclk", "mout_misc_bus_user", + CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SSS_IPCLKPORT_ACLK, + 21, 0, 0), + GATE(CLK_GOUT_MISC_SSMT_SSS_PCLK, + "gout_misc_ssmt_sss_pclk", "dout_misc_busp", + CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SSS_IPCLKPORT_PCLK, + 21, 0, 0), + GATE(CLK_GOUT_MISC_SSS_I_ACLK, + "gout_misc_sss_i_aclk", "mout_misc_bus_user", + CLK_CON_GAT_GOUT_BLK_MISC_UID_SSS_IPCLKPORT_I_ACLK, + 21, 0, 0), + GATE(CLK_GOUT_MISC_SSS_I_PCLK, + "gout_misc_sss_i_pclk", "dout_misc_busp", + CLK_CON_GAT_GOUT_BLK_MISC_UID_SSS_IPCLKPORT_I_PCLK, + 21, 0, 0), + GATE(CLK_GOUT_MISC_SYSMMU_MISC_CLK_S2, + "gout_misc_sysmmu_misc_clk_s2", "mout_misc_bus_user", + CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSMMU_MISC_IPCLKPORT_CLK_S2, + 21, 0, 0), + GATE(CLK_GOUT_MISC_SYSMMU_SSS_CLK_S1, + "gout_misc_sysmmu_sss_clk_s1", "mout_misc_sss_user", + CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSMMU_SSS_IPCLKPORT_CLK_S1, + 21, 0, 0), + GATE(CLK_GOUT_MISC_SYSREG_MISC_PCLK, + "gout_misc_sysreg_misc_pclk", "dout_misc_busp", + CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSREG_MISC_IPCLKPORT_PCLK, + 21, 0, 0), + GATE(CLK_GOUT_MISC_TMU_SUB_PCLK, + "gout_misc_tmu_sub_pclk", "dout_misc_busp", + CLK_CON_GAT_GOUT_BLK_MISC_UID_TMU_SUB_IPCLKPORT_PCLK, + 21, 0, 0), + GATE(CLK_GOUT_MISC_TMU_TOP_PCLK, + "gout_misc_tmu_top_pclk", "dout_misc_busp", + CLK_CON_GAT_GOUT_BLK_MISC_UID_TMU_TOP_IPCLKPORT_PCLK, + 21, 0, 0), + GATE(CLK_GOUT_MISC_WDT_CLUSTER0_PCLK, + "gout_misc_wdt_cluster0_pclk", "dout_misc_busp", + CLK_CON_GAT_GOUT_BLK_MISC_UID_WDT_CLUSTER0_IPCLKPORT_PCLK, + 21, 0, 0), + GATE(CLK_GOUT_MISC_WDT_CLUSTER1_PCLK, + "gout_misc_wdt_cluster1_pclk", "dout_misc_busp", + CLK_CON_GAT_GOUT_BLK_MISC_UID_WDT_CLUSTER1_IPCLKPORT_PCLK, + 21, 0, 0), + GATE(CLK_GOUT_MISC_XIU_D_MISC_ACLK, + "gout_misc_xiu_d_misc_aclk", "mout_misc_bus_user", + CLK_CON_GAT_GOUT_BLK_MISC_UID_XIU_D_MISC_IPCLKPORT_ACLK, + 21, 0, 0), +}; + +static const struct samsung_cmu_info misc_cmu_info __initconst = { + .mux_clks = misc_mux_clks, + .nr_mux_clks = ARRAY_SIZE(misc_mux_clks), + .div_clks = misc_div_clks, + .nr_div_clks = ARRAY_SIZE(misc_div_clks), + .gate_clks = misc_gate_clks, + .nr_gate_clks = ARRAY_SIZE(misc_gate_clks), + .nr_clk_ids = CLKS_NR_MISC, + .clk_regs = misc_clk_regs, + .nr_clk_regs = ARRAY_SIZE(misc_clk_regs), + .clk_name = "dout_cmu_misc_bus", +}; + +/* ---- platform_driver ----------------------------------------------------- */ + +static int __init gs101_cmu_probe(struct platform_device *pdev) +{ + const struct samsung_cmu_info *info; + struct device *dev = &pdev->dev; + + info = of_device_get_match_data(dev); + exynos_arm64_register_cmu(dev, dev->of_node, info); + + return 0; +} + +static const struct of_device_id gs101_cmu_of_match[] = { + { + .compatible = "google,gs101-cmu-apm", + .data = &apm_cmu_info, + }, { + .compatible = "google,gs101-cmu-misc", + .data = &misc_cmu_info, + }, { + }, +}; + +static struct platform_driver gs101_cmu_driver __refdata = { + .driver = { + .name = "gs101-cmu", + .of_match_table = gs101_cmu_of_match, + .suppress_bind_attrs = true, + }, + .probe = gs101_cmu_probe, +}; + +static int __init gs101_cmu_init(void) +{ + return platform_driver_register(&gs101_cmu_driver); +} +core_initcall(gs101_cmu_init); From c95f5b21a0eaa4a2701c28e2b209f9a7e09cd4f0 Mon Sep 17 00:00:00 2001 From: Peter Griffin Date: Mon, 11 Dec 2023 16:23:28 +0000 Subject: [PATCH 36/40] tty: serial: samsung: Add gs101 compatible and common fifoszdt_serial_drv_data Add serial driver data for Google Tensor gs101 SoC and a common fifoszdt_serial_drv_data that can be used by platforms that specify the samsung,uart-fifosize DT property. A corresponding dt-bindings patch updates the yaml to ensure samsung,uart-fifosize is a required property. Tested-by: Will McVicker Acked-by: Greg Kroah-Hartman Reviewed-by: Sam Protsenko Reviewed-by: Arnd Bergmann Signed-off-by: Peter Griffin Link: https://lore.kernel.org/r/20231211162331.435900-14-peter.griffin@linaro.org Signed-off-by: Krzysztof Kozlowski --- drivers/tty/serial/samsung_tty.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/tty/serial/samsung_tty.c b/drivers/tty/serial/samsung_tty.c index 3bd552841cd2..66bd6c090ace 100644 --- a/drivers/tty/serial/samsung_tty.c +++ b/drivers/tty/serial/samsung_tty.c @@ -2492,14 +2492,25 @@ static const struct s3c24xx_serial_drv_data exynos850_serial_drv_data = { .fifosize = { 256, 64, 64, 64 }, }; +/* + * Common drv_data struct for platforms that specify samsung,uart-fifosize in + * device tree. + */ +static const struct s3c24xx_serial_drv_data exynos_fifoszdt_serial_drv_data = { + EXYNOS_COMMON_SERIAL_DRV_DATA(), + .fifosize = { 0 }, +}; + #define EXYNOS4210_SERIAL_DRV_DATA (&exynos4210_serial_drv_data) #define EXYNOS5433_SERIAL_DRV_DATA (&exynos5433_serial_drv_data) #define EXYNOS850_SERIAL_DRV_DATA (&exynos850_serial_drv_data) +#define EXYNOS_FIFOSZDT_DRV_DATA (&exynos_fifoszdt_serial_drv_data) #else #define EXYNOS4210_SERIAL_DRV_DATA NULL #define EXYNOS5433_SERIAL_DRV_DATA NULL #define EXYNOS850_SERIAL_DRV_DATA NULL +#define EXYNOS_FIFOSZDT_DRV_DATA NULL #endif #ifdef CONFIG_ARCH_APPLE @@ -2583,6 +2594,9 @@ static const struct platform_device_id s3c24xx_serial_driver_ids[] = { }, { .name = "artpec8-uart", .driver_data = (kernel_ulong_t)ARTPEC8_SERIAL_DRV_DATA, + }, { + .name = "gs101-uart", + .driver_data = (kernel_ulong_t)EXYNOS_FIFOSZDT_DRV_DATA, }, { }, }; @@ -2604,6 +2618,8 @@ static const struct of_device_id s3c24xx_uart_dt_match[] = { .data = EXYNOS850_SERIAL_DRV_DATA }, { .compatible = "axis,artpec8-uart", .data = ARTPEC8_SERIAL_DRV_DATA }, + { .compatible = "google,gs101-uart", + .data = EXYNOS_FIFOSZDT_DRV_DATA }, {}, }; MODULE_DEVICE_TABLE(of, s3c24xx_uart_dt_match); From 6584cd34901056bc12e015781e4adf03b44ba485 Mon Sep 17 00:00:00 2001 From: Peter Griffin Date: Mon, 11 Dec 2023 16:23:25 +0000 Subject: [PATCH 37/40] watchdog: s3c2410_wdt: Add support for WTCON register DBGACK_MASK bit The WDT uses the CPU core signal DBGACK to determine whether the SoC is running in debug mode or not. If the DBGACK signal is asserted and DBGACK_MASK bit is enabled, then WDT output and interrupt is masked (disabled). Presence of the DBGACK_MASK bit is determined by adding a new QUIRK_HAS_DBGACK_BIT quirk. Also update to use BIT macro to avoid checkpatch --strict warnings. Tested-by: Will McVicker Reviewed-by: Sam Protsenko Signed-off-by: Peter Griffin Link: https://lore.kernel.org/r/20231211162331.435900-11-peter.griffin@linaro.org Signed-off-by: Krzysztof Kozlowski --- drivers/watchdog/s3c2410_wdt.c | 28 +++++++++++++++++++++++++--- 1 file changed, 25 insertions(+), 3 deletions(-) diff --git a/drivers/watchdog/s3c2410_wdt.c b/drivers/watchdog/s3c2410_wdt.c index 0b4bd883ff28..7ecb762a371d 100644 --- a/drivers/watchdog/s3c2410_wdt.c +++ b/drivers/watchdog/s3c2410_wdt.c @@ -9,6 +9,7 @@ * (c) Copyright 1996 Alan Cox */ +#include #include #include #include @@ -34,9 +35,10 @@ #define S3C2410_WTCNT_MAXCNT 0xffff -#define S3C2410_WTCON_RSTEN (1 << 0) -#define S3C2410_WTCON_INTEN (1 << 2) -#define S3C2410_WTCON_ENABLE (1 << 5) +#define S3C2410_WTCON_RSTEN BIT(0) +#define S3C2410_WTCON_INTEN BIT(2) +#define S3C2410_WTCON_ENABLE BIT(5) +#define S3C2410_WTCON_DBGACK_MASK BIT(16) #define S3C2410_WTCON_DIV16 (0 << 3) #define S3C2410_WTCON_DIV32 (1 << 3) @@ -100,12 +102,17 @@ * %QUIRK_HAS_PMU_CNT_EN: PMU block has some register (e.g. CLUSTERx_NONCPU_OUT) * with "watchdog counter enable" bit. That bit should be set to make watchdog * counter running. + * + * %QUIRK_HAS_DBGACK_BIT: WTCON register has DBGACK_MASK bit. Setting the + * DBGACK_MASK bit disables the watchdog outputs when the SoC is in debug mode. + * Debug mode is determined by the DBGACK CPU signal. */ #define QUIRK_HAS_WTCLRINT_REG (1 << 0) #define QUIRK_HAS_PMU_MASK_RESET (1 << 1) #define QUIRK_HAS_PMU_RST_STAT (1 << 2) #define QUIRK_HAS_PMU_AUTO_DISABLE (1 << 3) #define QUIRK_HAS_PMU_CNT_EN (1 << 4) +#define QUIRK_HAS_DBGACK_BIT BIT(5) /* These quirks require that we have a PMU register map */ #define QUIRKS_HAVE_PMUREG \ @@ -375,6 +382,19 @@ static int s3c2410wdt_enable(struct s3c2410_wdt *wdt, bool en) return 0; } +/* Disable watchdog outputs if CPU is in debug mode */ +static void s3c2410wdt_mask_dbgack(struct s3c2410_wdt *wdt) +{ + unsigned long wtcon; + + if (!(wdt->drv_data->quirks & QUIRK_HAS_DBGACK_BIT)) + return; + + wtcon = readl(wdt->reg_base + S3C2410_WTCON); + wtcon |= S3C2410_WTCON_DBGACK_MASK; + writel(wtcon, wdt->reg_base + S3C2410_WTCON); +} + static int s3c2410wdt_keepalive(struct watchdog_device *wdd) { struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd); @@ -700,6 +720,8 @@ static int s3c2410wdt_probe(struct platform_device *pdev) wdt->wdt_device.bootstatus = s3c2410wdt_get_bootstatus(wdt); wdt->wdt_device.parent = dev; + s3c2410wdt_mask_dbgack(wdt); + /* * If "tmr_atboot" param is non-zero, start the watchdog right now. Also * set WDOG_HW_RUNNING bit, so that watchdog core can kick the watchdog. From d429928dde2d7e3e98cbea5f170d089d10a45c39 Mon Sep 17 00:00:00 2001 From: Peter Griffin Date: Mon, 11 Dec 2023 16:23:26 +0000 Subject: [PATCH 38/40] watchdog: s3c2410_wdt: Update QUIRK macros to use BIT macro Update the remaining QUIRK macros to use the BIT macro. Reviewed-by: Sam Protsenko Signed-off-by: Peter Griffin Link: https://lore.kernel.org/r/20231211162331.435900-12-peter.griffin@linaro.org Signed-off-by: Krzysztof Kozlowski --- drivers/watchdog/s3c2410_wdt.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/watchdog/s3c2410_wdt.c b/drivers/watchdog/s3c2410_wdt.c index 7ecb762a371d..b7a03668f743 100644 --- a/drivers/watchdog/s3c2410_wdt.c +++ b/drivers/watchdog/s3c2410_wdt.c @@ -107,11 +107,11 @@ * DBGACK_MASK bit disables the watchdog outputs when the SoC is in debug mode. * Debug mode is determined by the DBGACK CPU signal. */ -#define QUIRK_HAS_WTCLRINT_REG (1 << 0) -#define QUIRK_HAS_PMU_MASK_RESET (1 << 1) -#define QUIRK_HAS_PMU_RST_STAT (1 << 2) -#define QUIRK_HAS_PMU_AUTO_DISABLE (1 << 3) -#define QUIRK_HAS_PMU_CNT_EN (1 << 4) +#define QUIRK_HAS_WTCLRINT_REG BIT(0) +#define QUIRK_HAS_PMU_MASK_RESET BIT(1) +#define QUIRK_HAS_PMU_RST_STAT BIT(2) +#define QUIRK_HAS_PMU_AUTO_DISABLE BIT(3) +#define QUIRK_HAS_PMU_CNT_EN BIT(4) #define QUIRK_HAS_DBGACK_BIT BIT(5) /* These quirks require that we have a PMU register map */ From 796bb2d3a16c1e786ed51183162783405b5c8f85 Mon Sep 17 00:00:00 2001 From: Peter Griffin Date: Mon, 11 Dec 2023 16:23:27 +0000 Subject: [PATCH 39/40] watchdog: s3c2410_wdt: Add support for Google gs101 SoC This patch adds the compatibles and drvdata for the Google gs101 SoC found in Pixel 6, Pixel 6a & Pixel 6 pro phones. Similar to Exynos850 it has two watchdog instances, one for each cluster and has some control bits in PMU registers. gs101 also has the dbgack_mask bit in wtcon register, so we also enable QUIRK_HAS_DBGACK_BIT. Tested-by: Will McVicker Reviewed-by: Sam Protsenko Signed-off-by: Peter Griffin Reviewed-by: Guenter Roeck Link: https://lore.kernel.org/r/20231211162331.435900-13-peter.griffin@linaro.org Signed-off-by: Krzysztof Kozlowski --- drivers/watchdog/s3c2410_wdt.c | 47 +++++++++++++++++++++++++++++++--- 1 file changed, 43 insertions(+), 4 deletions(-) diff --git a/drivers/watchdog/s3c2410_wdt.c b/drivers/watchdog/s3c2410_wdt.c index b7a03668f743..349d30462c8c 100644 --- a/drivers/watchdog/s3c2410_wdt.c +++ b/drivers/watchdog/s3c2410_wdt.c @@ -69,6 +69,13 @@ #define EXYNOSAUTOV9_CLUSTER0_WDTRESET_BIT 25 #define EXYNOSAUTOV9_CLUSTER1_WDTRESET_BIT 24 +#define GS_CLUSTER0_NONCPU_OUT 0x1220 +#define GS_CLUSTER1_NONCPU_OUT 0x1420 +#define GS_CLUSTER0_NONCPU_INT_EN 0x1244 +#define GS_CLUSTER1_NONCPU_INT_EN 0x1444 +#define GS_CLUSTER2_NONCPU_INT_EN 0x1644 +#define GS_RST_STAT_REG_OFFSET 0x3B44 + /** * DOC: Quirk flags for different Samsung watchdog IP-cores * @@ -270,7 +277,35 @@ static const struct s3c2410_wdt_variant drv_data_exynosautov9_cl1 = { QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_CNT_EN, }; +static const struct s3c2410_wdt_variant drv_data_gs101_cl0 = { + .mask_reset_reg = GS_CLUSTER0_NONCPU_INT_EN, + .mask_bit = 2, + .mask_reset_inv = true, + .rst_stat_reg = GS_RST_STAT_REG_OFFSET, + .rst_stat_bit = 0, + .cnt_en_reg = GS_CLUSTER0_NONCPU_OUT, + .cnt_en_bit = 8, + .quirks = QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_MASK_RESET | + QUIRK_HAS_PMU_CNT_EN | QUIRK_HAS_WTCLRINT_REG | + QUIRK_HAS_DBGACK_BIT, +}; + +static const struct s3c2410_wdt_variant drv_data_gs101_cl1 = { + .mask_reset_reg = GS_CLUSTER1_NONCPU_INT_EN, + .mask_bit = 2, + .mask_reset_inv = true, + .rst_stat_reg = GS_RST_STAT_REG_OFFSET, + .rst_stat_bit = 1, + .cnt_en_reg = GS_CLUSTER1_NONCPU_OUT, + .cnt_en_bit = 7, + .quirks = QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_MASK_RESET | + QUIRK_HAS_PMU_CNT_EN | QUIRK_HAS_WTCLRINT_REG | + QUIRK_HAS_DBGACK_BIT, +}; + static const struct of_device_id s3c2410_wdt_match[] = { + { .compatible = "google,gs101-wdt", + .data = &drv_data_gs101_cl0 }, { .compatible = "samsung,s3c2410-wdt", .data = &drv_data_s3c2410 }, { .compatible = "samsung,s3c6410-wdt", @@ -607,7 +642,8 @@ s3c2410_get_wdt_drv_data(struct platform_device *pdev, struct s3c2410_wdt *wdt) #ifdef CONFIG_OF /* Choose Exynos850/ExynosAutov9 driver data w.r.t. cluster index */ if (variant == &drv_data_exynos850_cl0 || - variant == &drv_data_exynosautov9_cl0) { + variant == &drv_data_exynosautov9_cl0 || + variant == &drv_data_gs101_cl0) { u32 index; int err; @@ -620,9 +656,12 @@ s3c2410_get_wdt_drv_data(struct platform_device *pdev, struct s3c2410_wdt *wdt) case 0: break; case 1: - variant = (variant == &drv_data_exynos850_cl0) ? - &drv_data_exynos850_cl1 : - &drv_data_exynosautov9_cl1; + if (variant == &drv_data_exynos850_cl0) + variant = &drv_data_exynos850_cl1; + else if (variant == &drv_data_exynosautov9_cl0) + variant = &drv_data_exynosautov9_cl1; + else if (variant == &drv_data_gs101_cl0) + variant = &drv_data_gs101_cl1; break; default: return dev_err_probe(dev, -EINVAL, "wrong cluster index: %u\n", index); From 35f32e39b4d9b436354c2a37623c393a2ac7cf87 Mon Sep 17 00:00:00 2001 From: Tudor Ambarus Date: Mon, 18 Dec 2023 06:43:33 +0000 Subject: [PATCH 40/40] dt-bindings: clock: google,gs101: rename CMU_TOP gate defines The gs101 clock defines from the bindings header are derived from the clock register names found in the datasheet under some certain rules. The CMU TOP gate clock defines missed to include the required "CMU" differentiator which will cause collisions with the gate clock defines of other clock units. Rename the TOP gate clock defines to include "CMU". Update the clock driver to use the new defines in order to not break compilation and bisect-ability. There are no device trees that use the previous defines. Fixes: 0a910f160638 ("dt-bindings: clock: Add Google gs101 clock management unit bindings") Signed-off-by: Tudor Ambarus Reviewed-by: Sam Protsenko Reviewed-by: Peter Griffin Link: https://lore.kernel.org/r/20231218064333.479885-1-tudor.ambarus@linaro.org Signed-off-by: Krzysztof Kozlowski --- drivers/clk/samsung/clk-gs101.c | 167 ++++++++++++----------- include/dt-bindings/clock/google,gs101.h | 144 +++++++++---------- 2 files changed, 159 insertions(+), 152 deletions(-) diff --git a/drivers/clk/samsung/clk-gs101.c b/drivers/clk/samsung/clk-gs101.c index a3dda97f5eb9..0964bb11657f 100644 --- a/drivers/clk/samsung/clk-gs101.c +++ b/drivers/clk/samsung/clk-gs101.c @@ -17,7 +17,7 @@ #include "clk-exynos-arm64.h" /* NOTE: Must be equal to the last clock ID increased by one */ -#define CLKS_NR_TOP (CLK_GOUT_TPU_UART + 1) +#define CLKS_NR_TOP (CLK_GOUT_CMU_TPU_UART + 1) #define CLKS_NR_APM (CLK_APM_PLL_DIV16_APM + 1) #define CLKS_NR_MISC (CLK_GOUT_MISC_XIU_D_MISC_ACLK + 1) @@ -1259,160 +1259,167 @@ static const struct samsung_fixed_factor_clock cmu_top_ffactor[] __initconst = { }; static const struct samsung_gate_clock cmu_top_gate_clks[] __initconst = { - GATE(CLK_GOUT_BUS0_BOOST, "gout_cmu_bus0_boost", + GATE(CLK_GOUT_CMU_BUS0_BOOST, "gout_cmu_bus0_boost", "mout_cmu_boost_option1", CLK_CON_GAT_CLKCMU_BUS0_BOOST, 21, 0, 0), - GATE(CLK_GOUT_BUS1_BOOST, "gout_cmu_bus1_boost", + GATE(CLK_GOUT_CMU_BUS1_BOOST, "gout_cmu_bus1_boost", "mout_cmu_boost_option1", CLK_CON_GAT_CLKCMU_BUS1_BOOST, 21, 0, 0), - GATE(CLK_GOUT_BUS2_BOOST, "gout_cmu_bus2_boost", + GATE(CLK_GOUT_CMU_BUS2_BOOST, "gout_cmu_bus2_boost", "mout_cmu_boost_option1", CLK_CON_GAT_CLKCMU_BUS2_BOOST, 21, 0, 0), - GATE(CLK_GOUT_CORE_BOOST, "gout_cmu_core_boost", + GATE(CLK_GOUT_CMU_CORE_BOOST, "gout_cmu_core_boost", "mout_cmu_boost_option1", CLK_CON_GAT_CLKCMU_CORE_BOOST, 21, 0, 0), - GATE(CLK_GOUT_CPUCL0_BOOST, "gout_cmu_cpucl0_boost", + GATE(CLK_GOUT_CMU_CPUCL0_BOOST, "gout_cmu_cpucl0_boost", "mout_cmu_boost_option1", CLK_CON_GAT_CLKCMU_CPUCL0_BOOST, 21, 0, 0), - GATE(CLK_GOUT_CPUCL1_BOOST, "gout_cmu_cpucl1_boost", + GATE(CLK_GOUT_CMU_CPUCL1_BOOST, "gout_cmu_cpucl1_boost", "mout_cmu_boost_option1", CLK_CON_GAT_CLKCMU_CPUCL1_BOOST, 21, 0, 0), - GATE(CLK_GOUT_CPUCL2_BOOST, "gout_cmu_cpucl2_boost", + GATE(CLK_GOUT_CMU_CPUCL2_BOOST, "gout_cmu_cpucl2_boost", "mout_cmu_boost_option1", CLK_CON_GAT_CLKCMU_CPUCL2_BOOST, 21, 0, 0), - GATE(CLK_GOUT_MIF_BOOST, "gout_cmu_mif_boost", + GATE(CLK_GOUT_CMU_MIF_BOOST, "gout_cmu_mif_boost", "mout_cmu_boost_option1", CLK_CON_GAT_CLKCMU_MIF_BOOST, 21, 0, 0), - GATE(CLK_GOUT_MIF_SWITCH, "gout_cmu_mif_switch", "mout_cmu_mif_switch", - CLK_CON_GAT_CLKCMU_MIF_SWITCH, 21, 0, 0), - GATE(CLK_GOUT_BO_BUS, "gout_cmu_bo_bus", "mout_cmu_bo_bus", + GATE(CLK_GOUT_CMU_MIF_SWITCH, "gout_cmu_mif_switch", + "mout_cmu_mif_switch", CLK_CON_GAT_CLKCMU_MIF_SWITCH, 21, 0, 0), + GATE(CLK_GOUT_CMU_BO_BUS, "gout_cmu_bo_bus", "mout_cmu_bo_bus", CLK_CON_GAT_GATE_CLKCMU_BO_BUS, 21, 0, 0), - GATE(CLK_GOUT_BUS0_BUS, "gout_cmu_bus0_bus", "mout_cmu_bus0_bus", + GATE(CLK_GOUT_CMU_BUS0_BUS, "gout_cmu_bus0_bus", "mout_cmu_bus0_bus", CLK_CON_GAT_GATE_CLKCMU_BUS0_BUS, 21, 0, 0), - GATE(CLK_GOUT_BUS1_BUS, "gout_cmu_bus1_bus", "mout_cmu_bus1_bus", + GATE(CLK_GOUT_CMU_BUS1_BUS, "gout_cmu_bus1_bus", "mout_cmu_bus1_bus", CLK_CON_GAT_GATE_CLKCMU_BUS1_BUS, 21, 0, 0), - GATE(CLK_GOUT_BUS2_BUS, "gout_cmu_bus2_bus", "mout_cmu_bus2_bus", + GATE(CLK_GOUT_CMU_BUS2_BUS, "gout_cmu_bus2_bus", "mout_cmu_bus2_bus", CLK_CON_GAT_GATE_CLKCMU_BUS2_BUS, 21, 0, 0), - GATE(CLK_GOUT_CIS_CLK0, "gout_cmu_cis_clk0", "mout_cmu_cis_clk0", + GATE(CLK_GOUT_CMU_CIS_CLK0, "gout_cmu_cis_clk0", "mout_cmu_cis_clk0", CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0, 21, 0, 0), - GATE(CLK_GOUT_CIS_CLK1, "gout_cmu_cis_clk1", "mout_cmu_cis_clk1", + GATE(CLK_GOUT_CMU_CIS_CLK1, "gout_cmu_cis_clk1", "mout_cmu_cis_clk1", CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1, 21, 0, 0), - GATE(CLK_GOUT_CIS_CLK2, "gout_cmu_cis_clk2", "mout_cmu_cis_clk2", + GATE(CLK_GOUT_CMU_CIS_CLK2, "gout_cmu_cis_clk2", "mout_cmu_cis_clk2", CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2, 21, 0, 0), - GATE(CLK_GOUT_CIS_CLK3, "gout_cmu_cis_clk3", "mout_cmu_cis_clk3", + GATE(CLK_GOUT_CMU_CIS_CLK3, "gout_cmu_cis_clk3", "mout_cmu_cis_clk3", CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3, 21, 0, 0), - GATE(CLK_GOUT_CIS_CLK4, "gout_cmu_cis_clk4", "mout_cmu_cis_clk4", + GATE(CLK_GOUT_CMU_CIS_CLK4, "gout_cmu_cis_clk4", "mout_cmu_cis_clk4", CLK_CON_GAT_GATE_CLKCMU_CIS_CLK4, 21, 0, 0), - GATE(CLK_GOUT_CIS_CLK5, "gout_cmu_cis_clk5", "mout_cmu_cis_clk5", + GATE(CLK_GOUT_CMU_CIS_CLK5, "gout_cmu_cis_clk5", "mout_cmu_cis_clk5", CLK_CON_GAT_GATE_CLKCMU_CIS_CLK5, 21, 0, 0), - GATE(CLK_GOUT_CIS_CLK6, "gout_cmu_cis_clk6", "mout_cmu_cis_clk6", + GATE(CLK_GOUT_CMU_CIS_CLK6, "gout_cmu_cis_clk6", "mout_cmu_cis_clk6", CLK_CON_GAT_GATE_CLKCMU_CIS_CLK6, 21, 0, 0), - GATE(CLK_GOUT_CIS_CLK7, "gout_cmu_cis_clk7", "mout_cmu_cis_clk7", + GATE(CLK_GOUT_CMU_CIS_CLK7, "gout_cmu_cis_clk7", "mout_cmu_cis_clk7", CLK_CON_GAT_GATE_CLKCMU_CIS_CLK7, 21, 0, 0), - GATE(CLK_GOUT_CMU_BOOST, "gout_cmu_cmu_boost", "mout_cmu_cmu_boost", + GATE(CLK_GOUT_CMU_CMU_BOOST, "gout_cmu_cmu_boost", "mout_cmu_cmu_boost", CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST, 21, 0, 0), - GATE(CLK_GOUT_CORE_BUS, "gout_cmu_core_bus", "mout_cmu_core_bus", + GATE(CLK_GOUT_CMU_CORE_BUS, "gout_cmu_core_bus", "mout_cmu_core_bus", CLK_CON_GAT_GATE_CLKCMU_CORE_BUS, 21, 0, 0), - GATE(CLK_GOUT_CPUCL0_DBG, "gout_cmu_cpucl0_dbg", "mout_cmu_cpucl0_dbg", - CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_BUS, 21, 0, 0), - GATE(CLK_GOUT_CPUCL0_SWITCH, "gout_cmu_cpucl0_switch", + GATE(CLK_GOUT_CMU_CPUCL0_DBG, "gout_cmu_cpucl0_dbg", + "mout_cmu_cpucl0_dbg", CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_BUS, + 21, 0, 0), + GATE(CLK_GOUT_CMU_CPUCL0_SWITCH, "gout_cmu_cpucl0_switch", "mout_cmu_cpucl0_switch", CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH, 21, 0, 0), - GATE(CLK_GOUT_CPUCL1_SWITCH, "gout_cmu_cpucl1_switch", + GATE(CLK_GOUT_CMU_CPUCL1_SWITCH, "gout_cmu_cpucl1_switch", "mout_cmu_cpucl1_switch", CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH, 21, 0, 0), - GATE(CLK_GOUT_CPUCL2_SWITCH, "gout_cmu_cpucl2_switch", + GATE(CLK_GOUT_CMU_CPUCL2_SWITCH, "gout_cmu_cpucl2_switch", "mout_cmu_cpucl2_switch", CLK_CON_GAT_GATE_CLKCMU_CPUCL2_SWITCH, 21, 0, 0), - GATE(CLK_GOUT_CSIS_BUS, "gout_cmu_csis_bus", "mout_cmu_csis_bus", + GATE(CLK_GOUT_CMU_CSIS_BUS, "gout_cmu_csis_bus", "mout_cmu_csis_bus", CLK_CON_GAT_GATE_CLKCMU_CSIS_BUS, 21, 0, 0), - GATE(CLK_GOUT_DISP_BUS, "gout_cmu_disp_bus", "mout_cmu_disp_bus", + GATE(CLK_GOUT_CMU_DISP_BUS, "gout_cmu_disp_bus", "mout_cmu_disp_bus", CLK_CON_GAT_GATE_CLKCMU_DISP_BUS, 21, 0, 0), - GATE(CLK_GOUT_DNS_BUS, "gout_cmu_dns_bus", "mout_cmu_dns_bus", + GATE(CLK_GOUT_CMU_DNS_BUS, "gout_cmu_dns_bus", "mout_cmu_dns_bus", CLK_CON_GAT_GATE_CLKCMU_DNS_BUS, 21, 0, 0), - GATE(CLK_GOUT_DPU_BUS, "gout_cmu_dpu_bus", "mout_cmu_dpu_bus", + GATE(CLK_GOUT_CMU_DPU_BUS, "gout_cmu_dpu_bus", "mout_cmu_dpu_bus", CLK_CON_GAT_GATE_CLKCMU_DPU_BUS, 21, 0, 0), - GATE(CLK_GOUT_EH_BUS, "gout_cmu_eh_bus", "mout_cmu_eh_bus", + GATE(CLK_GOUT_CMU_EH_BUS, "gout_cmu_eh_bus", "mout_cmu_eh_bus", CLK_CON_GAT_GATE_CLKCMU_EH_BUS, 21, 0, 0), - GATE(CLK_GOUT_G2D_G2D, "gout_cmu_g2d_g2d", "mout_cmu_g2d_g2d", + GATE(CLK_GOUT_CMU_G2D_G2D, "gout_cmu_g2d_g2d", "mout_cmu_g2d_g2d", CLK_CON_GAT_GATE_CLKCMU_G2D_G2D, 21, 0, 0), - GATE(CLK_GOUT_G2D_MSCL, "gout_cmu_g2d_mscl", "mout_cmu_g2d_mscl", + GATE(CLK_GOUT_CMU_G2D_MSCL, "gout_cmu_g2d_mscl", "mout_cmu_g2d_mscl", CLK_CON_GAT_GATE_CLKCMU_G2D_MSCL, 21, 0, 0), - GATE(CLK_GOUT_G3AA_G3AA, "gout_cmu_g3aa_g3aa", "mout_cmu_g3aa_g3aa", + GATE(CLK_GOUT_CMU_G3AA_G3AA, "gout_cmu_g3aa_g3aa", "mout_cmu_g3aa_g3aa", CLK_CON_MUX_MUX_CLKCMU_G3AA_G3AA, 21, 0, 0), - GATE(CLK_GOUT_G3D_BUSD, "gout_cmu_g3d_busd", "mout_cmu_g3d_busd", + GATE(CLK_GOUT_CMU_G3D_BUSD, "gout_cmu_g3d_busd", "mout_cmu_g3d_busd", CLK_CON_GAT_GATE_CLKCMU_G3D_BUSD, 21, 0, 0), - GATE(CLK_GOUT_G3D_GLB, "gout_cmu_g3d_glb", "mout_cmu_g3d_glb", + GATE(CLK_GOUT_CMU_G3D_GLB, "gout_cmu_g3d_glb", "mout_cmu_g3d_glb", CLK_CON_GAT_GATE_CLKCMU_G3D_GLB, 21, 0, 0), - GATE(CLK_GOUT_G3D_SWITCH, "gout_cmu_g3d_switch", "mout_cmu_g3d_switch", - CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH, 21, 0, 0), - GATE(CLK_GOUT_GDC_GDC0, "gout_cmu_gdc_gdc0", "mout_cmu_gdc_gdc0", + GATE(CLK_GOUT_CMU_G3D_SWITCH, "gout_cmu_g3d_switch", + "mout_cmu_g3d_switch", CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH, + 21, 0, 0), + GATE(CLK_GOUT_CMU_GDC_GDC0, "gout_cmu_gdc_gdc0", "mout_cmu_gdc_gdc0", CLK_CON_GAT_GATE_CLKCMU_GDC_GDC0, 21, 0, 0), - GATE(CLK_GOUT_GDC_GDC1, "gout_cmu_gdc_gdc1", "mout_cmu_gdc_gdc1", + GATE(CLK_GOUT_CMU_GDC_GDC1, "gout_cmu_gdc_gdc1", "mout_cmu_gdc_gdc1", CLK_CON_GAT_GATE_CLKCMU_GDC_GDC1, 21, 0, 0), - GATE(CLK_GOUT_GDC_SCSC, "gout_cmu_gdc_scsc", "mout_cmu_gdc_scsc", + GATE(CLK_GOUT_CMU_GDC_SCSC, "gout_cmu_gdc_scsc", "mout_cmu_gdc_scsc", CLK_CON_GAT_GATE_CLKCMU_GDC_SCSC, 21, 0, 0), GATE(CLK_GOUT_CMU_HPM, "gout_cmu_hpm", "mout_cmu_hpm", CLK_CON_GAT_GATE_CLKCMU_HPM, 21, 0, 0), - GATE(CLK_GOUT_HSI0_BUS, "gout_cmu_hsi0_bus", "mout_cmu_hsi0_bus", + GATE(CLK_GOUT_CMU_HSI0_BUS, "gout_cmu_hsi0_bus", "mout_cmu_hsi0_bus", CLK_CON_GAT_GATE_CLKCMU_HSI0_BUS, 21, 0, 0), - GATE(CLK_GOUT_HSI0_DPGTC, "gout_cmu_hsi0_dpgtc", "mout_cmu_hsi0_dpgtc", - CLK_CON_GAT_GATE_CLKCMU_HSI0_DPGTC, 21, 0, 0), - GATE(CLK_GOUT_HSI0_USB31DRD, "gout_cmu_hsi0_usb31drd", + GATE(CLK_GOUT_CMU_HSI0_DPGTC, "gout_cmu_hsi0_dpgtc", + "mout_cmu_hsi0_dpgtc", CLK_CON_GAT_GATE_CLKCMU_HSI0_DPGTC, + 21, 0, 0), + GATE(CLK_GOUT_CMU_HSI0_USB31DRD, "gout_cmu_hsi0_usb31drd", "mout_cmu_hsi0_usb31drd", CLK_CON_GAT_GATE_CLKCMU_HSI0_USB31DRD, 21, 0, 0), - GATE(CLK_GOUT_HSI0_USBDPDBG, "gout_cmu_hsi0_usbdpdbg", + GATE(CLK_GOUT_CMU_HSI0_USBDPDBG, "gout_cmu_hsi0_usbdpdbg", "mout_cmu_hsi0_usbdpdbg", CLK_CON_GAT_GATE_CLKCMU_HSI0_USBDPDBG, 21, 0, 0), - GATE(CLK_GOUT_HSI1_BUS, "gout_cmu_hsi1_bus", "mout_cmu_hsi1_bus", + GATE(CLK_GOUT_CMU_HSI1_BUS, "gout_cmu_hsi1_bus", "mout_cmu_hsi1_bus", CLK_CON_GAT_GATE_CLKCMU_HSI1_BUS, 21, 0, 0), - GATE(CLK_GOUT_HSI1_PCIE, "gout_cmu_hsi1_pcie", "mout_cmu_hsi1_pcie", + GATE(CLK_GOUT_CMU_HSI1_PCIE, "gout_cmu_hsi1_pcie", "mout_cmu_hsi1_pcie", CLK_CON_GAT_GATE_CLKCMU_HSI1_PCIE, 21, 0, 0), - GATE(CLK_GOUT_HSI2_BUS, "gout_cmu_hsi2_bus", "mout_cmu_hsi2_bus", + GATE(CLK_GOUT_CMU_HSI2_BUS, "gout_cmu_hsi2_bus", "mout_cmu_hsi2_bus", CLK_CON_GAT_GATE_CLKCMU_HSI2_BUS, 21, 0, 0), - GATE(CLK_GOUT_HSI2_MMC_CARD, "gout_cmu_hsi2_mmc_card", + GATE(CLK_GOUT_CMU_HSI2_MMC_CARD, "gout_cmu_hsi2_mmc_card", "mout_cmu_hsi2_mmc_card", CLK_CON_GAT_GATE_CLKCMU_HSI2_MMCCARD, 21, 0, 0), - GATE(CLK_GOUT_HSI2_PCIE, "gout_cmu_hsi2_pcie", "mout_cmu_hsi2_pcie", + GATE(CLK_GOUT_CMU_HSI2_PCIE, "gout_cmu_hsi2_pcie", "mout_cmu_hsi2_pcie", CLK_CON_GAT_GATE_CLKCMU_HSI2_PCIE, 21, 0, 0), - GATE(CLK_GOUT_HSI2_UFS_EMBD, "gout_cmu_hsi2_ufs_embd", + GATE(CLK_GOUT_CMU_HSI2_UFS_EMBD, "gout_cmu_hsi2_ufs_embd", "mout_cmu_hsi2_ufs_embd", CLK_CON_GAT_GATE_CLKCMU_HSI2_UFS_EMBD, 21, 0, 0), - GATE(CLK_GOUT_IPP_BUS, "gout_cmu_ipp_bus", "mout_cmu_ipp_bus", + GATE(CLK_GOUT_CMU_IPP_BUS, "gout_cmu_ipp_bus", "mout_cmu_ipp_bus", CLK_CON_GAT_GATE_CLKCMU_IPP_BUS, 21, 0, 0), - GATE(CLK_GOUT_ITP_BUS, "gout_cmu_itp_bus", "mout_cmu_itp_bus", + GATE(CLK_GOUT_CMU_ITP_BUS, "gout_cmu_itp_bus", "mout_cmu_itp_bus", CLK_CON_GAT_GATE_CLKCMU_ITP_BUS, 21, 0, 0), - GATE(CLK_GOUT_MCSC_ITSC, "gout_cmu_mcsc_itsc", "mout_cmu_mcsc_itsc", + GATE(CLK_GOUT_CMU_MCSC_ITSC, "gout_cmu_mcsc_itsc", "mout_cmu_mcsc_itsc", CLK_CON_GAT_GATE_CLKCMU_MCSC_ITSC, 21, 0, 0), - GATE(CLK_GOUT_MCSC_MCSC, "gout_cmu_mcsc_mcsc", "mout_cmu_mcsc_mcsc", + GATE(CLK_GOUT_CMU_MCSC_MCSC, "gout_cmu_mcsc_mcsc", "mout_cmu_mcsc_mcsc", CLK_CON_GAT_GATE_CLKCMU_MCSC_MCSC, 21, 0, 0), - GATE(CLK_GOUT_MFC_MFC, "gout_cmu_mfc_mfc", "mout_cmu_mfc_mfc", + GATE(CLK_GOUT_CMU_MFC_MFC, "gout_cmu_mfc_mfc", "mout_cmu_mfc_mfc", CLK_CON_GAT_GATE_CLKCMU_MFC_MFC, 21, 0, 0), - GATE(CLK_GOUT_MIF_BUSP, "gout_cmu_mif_busp", "mout_cmu_mif_busp", + GATE(CLK_GOUT_CMU_MIF_BUSP, "gout_cmu_mif_busp", "mout_cmu_mif_busp", CLK_CON_GAT_GATE_CLKCMU_MIF_BUSP, 21, 0, 0), - GATE(CLK_GOUT_MISC_BUS, "gout_cmu_misc_bus", "mout_cmu_misc_bus", + GATE(CLK_GOUT_CMU_MISC_BUS, "gout_cmu_misc_bus", "mout_cmu_misc_bus", CLK_CON_GAT_GATE_CLKCMU_MISC_BUS, 21, 0, 0), - GATE(CLK_GOUT_MISC_SSS, "gout_cmu_misc_sss", "mout_cmu_misc_sss", + GATE(CLK_GOUT_CMU_MISC_SSS, "gout_cmu_misc_sss", "mout_cmu_misc_sss", CLK_CON_GAT_GATE_CLKCMU_MISC_SSS, 21, 0, 0), - GATE(CLK_GOUT_PDP_BUS, "gout_cmu_pdp_bus", "mout_cmu_pdp_bus", + GATE(CLK_GOUT_CMU_PDP_BUS, "gout_cmu_pdp_bus", "mout_cmu_pdp_bus", CLK_CON_GAT_GATE_CLKCMU_PDP_BUS, 21, 0, 0), - GATE(CLK_GOUT_PDP_VRA, "gout_cmu_pdp_vra", "mout_cmu_pdp_vra", + GATE(CLK_GOUT_CMU_PDP_VRA, "gout_cmu_pdp_vra", "mout_cmu_pdp_vra", CLK_CON_GAT_GATE_CLKCMU_PDP_BUS, 21, 0, 0), - GATE(CLK_GOUT_PERIC0_BUS, "gout_cmu_peric0_bus", "mout_cmu_peric0_bus", - CLK_CON_GAT_GATE_CLKCMU_PERIC0_BUS, 21, 0, 0), - GATE(CLK_GOUT_PERIC0_IP, "gout_cmu_peric0_ip", "mout_cmu_peric0_ip", + GATE(CLK_GOUT_CMU_PERIC0_BUS, "gout_cmu_peric0_bus", + "mout_cmu_peric0_bus", CLK_CON_GAT_GATE_CLKCMU_PERIC0_BUS, + 21, 0, 0), + GATE(CLK_GOUT_CMU_PERIC0_IP, "gout_cmu_peric0_ip", "mout_cmu_peric0_ip", CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP, 21, 0, 0), - GATE(CLK_GOUT_PERIC1_BUS, "gout_cmu_peric1_bus", "mout_cmu_peric1_bus", - CLK_CON_GAT_GATE_CLKCMU_PERIC1_BUS, 21, 0, 0), - GATE(CLK_GOUT_PERIC1_IP, "gout_cmu_peric1_ip", "mout_cmu_peric1_ip", + GATE(CLK_GOUT_CMU_PERIC1_BUS, "gout_cmu_peric1_bus", + "mout_cmu_peric1_bus", CLK_CON_GAT_GATE_CLKCMU_PERIC1_BUS, + 21, 0, 0), + GATE(CLK_GOUT_CMU_PERIC1_IP, "gout_cmu_peric1_ip", "mout_cmu_peric1_ip", CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP, 21, 0, 0), - GATE(CLK_GOUT_TNR_BUS, "gout_cmu_tnr_bus", "mout_cmu_tnr_bus", + GATE(CLK_GOUT_CMU_TNR_BUS, "gout_cmu_tnr_bus", "mout_cmu_tnr_bus", CLK_CON_GAT_GATE_CLKCMU_TNR_BUS, 21, 0, 0), - GATE(CLK_GOUT_TOP_CMUREF, "gout_cmu_top_cmuref", "mout_cmu_top_cmuref", - CLK_CON_GAT_GATE_CLKCMU_TOP_CMUREF, 21, 0, 0), - GATE(CLK_GOUT_TPU_BUS, "gout_cmu_tpu_bus", "mout_cmu_tpu_bus", + GATE(CLK_GOUT_CMU_TOP_CMUREF, "gout_cmu_top_cmuref", + "mout_cmu_top_cmuref", CLK_CON_GAT_GATE_CLKCMU_TOP_CMUREF, + 21, 0, 0), + GATE(CLK_GOUT_CMU_TPU_BUS, "gout_cmu_tpu_bus", "mout_cmu_tpu_bus", CLK_CON_GAT_GATE_CLKCMU_TPU_BUS, 21, 0, 0), - GATE(CLK_GOUT_TPU_TPU, "gout_cmu_tpu_tpu", "mout_cmu_tpu_tpu", + GATE(CLK_GOUT_CMU_TPU_TPU, "gout_cmu_tpu_tpu", "mout_cmu_tpu_tpu", CLK_CON_GAT_GATE_CLKCMU_TPU_TPU, 21, 0, 0), - GATE(CLK_GOUT_TPU_TPUCTL, "gout_cmu_tpu_tpuctl", "mout_cmu_tpu_tpuctl", - CLK_CON_GAT_GATE_CLKCMU_TPU_TPUCTL, 21, 0, 0), - GATE(CLK_GOUT_TPU_UART, "gout_cmu_tpu_uart", "mout_cmu_tpu_uart", + GATE(CLK_GOUT_CMU_TPU_TPUCTL, "gout_cmu_tpu_tpuctl", + "mout_cmu_tpu_tpuctl", CLK_CON_GAT_GATE_CLKCMU_TPU_TPUCTL, + 21, 0, 0), + GATE(CLK_GOUT_CMU_TPU_UART, "gout_cmu_tpu_uart", "mout_cmu_tpu_uart", CLK_CON_GAT_GATE_CLKCMU_TPU_UART, 21, 0, 0), }; diff --git a/include/dt-bindings/clock/google,gs101.h b/include/dt-bindings/clock/google,gs101.h index 9761c0b24e66..21adec22387c 100644 --- a/include/dt-bindings/clock/google,gs101.h +++ b/include/dt-bindings/clock/google,gs101.h @@ -166,79 +166,79 @@ #define CLK_DOUT_CMU_SHARED3_DIV2 150 /* CMU_TOP Gates */ -#define CLK_GOUT_BUS0_BOOST 151 -#define CLK_GOUT_BUS1_BOOST 152 -#define CLK_GOUT_BUS2_BOOST 153 -#define CLK_GOUT_CORE_BOOST 154 -#define CLK_GOUT_CPUCL0_BOOST 155 -#define CLK_GOUT_CPUCL1_BOOST 156 -#define CLK_GOUT_CPUCL2_BOOST 157 -#define CLK_GOUT_MIF_BOOST 158 -#define CLK_GOUT_MIF_SWITCH 159 -#define CLK_GOUT_BO_BUS 160 -#define CLK_GOUT_BUS0_BUS 161 -#define CLK_GOUT_BUS1_BUS 162 -#define CLK_GOUT_BUS2_BUS 163 -#define CLK_GOUT_CIS_CLK0 164 -#define CLK_GOUT_CIS_CLK1 165 -#define CLK_GOUT_CIS_CLK2 166 -#define CLK_GOUT_CIS_CLK3 167 -#define CLK_GOUT_CIS_CLK4 168 -#define CLK_GOUT_CIS_CLK5 169 -#define CLK_GOUT_CIS_CLK6 170 -#define CLK_GOUT_CIS_CLK7 171 -#define CLK_GOUT_CMU_BOOST 172 -#define CLK_GOUT_CORE_BUS 173 -#define CLK_GOUT_CPUCL0_DBG 174 -#define CLK_GOUT_CPUCL0_SWITCH 175 -#define CLK_GOUT_CPUCL1_SWITCH 176 -#define CLK_GOUT_CPUCL2_SWITCH 177 -#define CLK_GOUT_CSIS_BUS 178 -#define CLK_GOUT_DISP_BUS 179 -#define CLK_GOUT_DNS_BUS 180 -#define CLK_GOUT_DPU_BUS 181 -#define CLK_GOUT_EH_BUS 182 -#define CLK_GOUT_G2D_G2D 183 -#define CLK_GOUT_G2D_MSCL 184 -#define CLK_GOUT_G3AA_G3AA 185 -#define CLK_GOUT_G3D_BUSD 186 -#define CLK_GOUT_G3D_GLB 187 -#define CLK_GOUT_G3D_SWITCH 188 -#define CLK_GOUT_GDC_GDC0 189 -#define CLK_GOUT_GDC_GDC1 190 -#define CLK_GOUT_GDC_SCSC 191 +#define CLK_GOUT_CMU_BUS0_BOOST 151 +#define CLK_GOUT_CMU_BUS1_BOOST 152 +#define CLK_GOUT_CMU_BUS2_BOOST 153 +#define CLK_GOUT_CMU_CORE_BOOST 154 +#define CLK_GOUT_CMU_CPUCL0_BOOST 155 +#define CLK_GOUT_CMU_CPUCL1_BOOST 156 +#define CLK_GOUT_CMU_CPUCL2_BOOST 157 +#define CLK_GOUT_CMU_MIF_BOOST 158 +#define CLK_GOUT_CMU_MIF_SWITCH 159 +#define CLK_GOUT_CMU_BO_BUS 160 +#define CLK_GOUT_CMU_BUS0_BUS 161 +#define CLK_GOUT_CMU_BUS1_BUS 162 +#define CLK_GOUT_CMU_BUS2_BUS 163 +#define CLK_GOUT_CMU_CIS_CLK0 164 +#define CLK_GOUT_CMU_CIS_CLK1 165 +#define CLK_GOUT_CMU_CIS_CLK2 166 +#define CLK_GOUT_CMU_CIS_CLK3 167 +#define CLK_GOUT_CMU_CIS_CLK4 168 +#define CLK_GOUT_CMU_CIS_CLK5 169 +#define CLK_GOUT_CMU_CIS_CLK6 170 +#define CLK_GOUT_CMU_CIS_CLK7 171 +#define CLK_GOUT_CMU_CMU_BOOST 172 +#define CLK_GOUT_CMU_CORE_BUS 173 +#define CLK_GOUT_CMU_CPUCL0_DBG 174 +#define CLK_GOUT_CMU_CPUCL0_SWITCH 175 +#define CLK_GOUT_CMU_CPUCL1_SWITCH 176 +#define CLK_GOUT_CMU_CPUCL2_SWITCH 177 +#define CLK_GOUT_CMU_CSIS_BUS 178 +#define CLK_GOUT_CMU_DISP_BUS 179 +#define CLK_GOUT_CMU_DNS_BUS 180 +#define CLK_GOUT_CMU_DPU_BUS 181 +#define CLK_GOUT_CMU_EH_BUS 182 +#define CLK_GOUT_CMU_G2D_G2D 183 +#define CLK_GOUT_CMU_G2D_MSCL 184 +#define CLK_GOUT_CMU_G3AA_G3AA 185 +#define CLK_GOUT_CMU_G3D_BUSD 186 +#define CLK_GOUT_CMU_G3D_GLB 187 +#define CLK_GOUT_CMU_G3D_SWITCH 188 +#define CLK_GOUT_CMU_GDC_GDC0 189 +#define CLK_GOUT_CMU_GDC_GDC1 190 +#define CLK_GOUT_CMU_GDC_SCSC 191 #define CLK_GOUT_CMU_HPM 192 -#define CLK_GOUT_HSI0_BUS 193 -#define CLK_GOUT_HSI0_DPGTC 194 -#define CLK_GOUT_HSI0_USB31DRD 195 -#define CLK_GOUT_HSI0_USBDPDBG 196 -#define CLK_GOUT_HSI1_BUS 197 -#define CLK_GOUT_HSI1_PCIE 198 -#define CLK_GOUT_HSI2_BUS 199 -#define CLK_GOUT_HSI2_MMC_CARD 200 -#define CLK_GOUT_HSI2_PCIE 201 -#define CLK_GOUT_HSI2_UFS_EMBD 202 -#define CLK_GOUT_IPP_BUS 203 -#define CLK_GOUT_ITP_BUS 204 -#define CLK_GOUT_MCSC_ITSC 205 -#define CLK_GOUT_MCSC_MCSC 206 -#define CLK_GOUT_MFC_MFC 207 -#define CLK_GOUT_MIF_BUSP 208 -#define CLK_GOUT_MISC_BUS 209 -#define CLK_GOUT_MISC_SSS 210 -#define CLK_GOUT_PDP_BUS 211 -#define CLK_GOUT_PDP_VRA 212 -#define CLK_GOUT_G3AA 213 -#define CLK_GOUT_PERIC0_BUS 214 -#define CLK_GOUT_PERIC0_IP 215 -#define CLK_GOUT_PERIC1_BUS 216 -#define CLK_GOUT_PERIC1_IP 217 -#define CLK_GOUT_TNR_BUS 218 -#define CLK_GOUT_TOP_CMUREF 219 -#define CLK_GOUT_TPU_BUS 220 -#define CLK_GOUT_TPU_TPU 221 -#define CLK_GOUT_TPU_TPUCTL 222 -#define CLK_GOUT_TPU_UART 223 +#define CLK_GOUT_CMU_HSI0_BUS 193 +#define CLK_GOUT_CMU_HSI0_DPGTC 194 +#define CLK_GOUT_CMU_HSI0_USB31DRD 195 +#define CLK_GOUT_CMU_HSI0_USBDPDBG 196 +#define CLK_GOUT_CMU_HSI1_BUS 197 +#define CLK_GOUT_CMU_HSI1_PCIE 198 +#define CLK_GOUT_CMU_HSI2_BUS 199 +#define CLK_GOUT_CMU_HSI2_MMC_CARD 200 +#define CLK_GOUT_CMU_HSI2_PCIE 201 +#define CLK_GOUT_CMU_HSI2_UFS_EMBD 202 +#define CLK_GOUT_CMU_IPP_BUS 203 +#define CLK_GOUT_CMU_ITP_BUS 204 +#define CLK_GOUT_CMU_MCSC_ITSC 205 +#define CLK_GOUT_CMU_MCSC_MCSC 206 +#define CLK_GOUT_CMU_MFC_MFC 207 +#define CLK_GOUT_CMU_MIF_BUSP 208 +#define CLK_GOUT_CMU_MISC_BUS 209 +#define CLK_GOUT_CMU_MISC_SSS 210 +#define CLK_GOUT_CMU_PDP_BUS 211 +#define CLK_GOUT_CMU_PDP_VRA 212 +#define CLK_GOUT_CMU_G3AA 213 +#define CLK_GOUT_CMU_PERIC0_BUS 214 +#define CLK_GOUT_CMU_PERIC0_IP 215 +#define CLK_GOUT_CMU_PERIC1_BUS 216 +#define CLK_GOUT_CMU_PERIC1_IP 217 +#define CLK_GOUT_CMU_TNR_BUS 218 +#define CLK_GOUT_CMU_TOP_CMUREF 219 +#define CLK_GOUT_CMU_TPU_BUS 220 +#define CLK_GOUT_CMU_TPU_TPU 221 +#define CLK_GOUT_CMU_TPU_TPUCTL 222 +#define CLK_GOUT_CMU_TPU_UART 223 /* CMU_APM */ #define CLK_MOUT_APM_FUNC 1