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drm/amd/display: Add dcn42b_soc_bb to DML2
[Why & How] Add bounding box for dcn42b Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Matthew Stewart <matthew.stewart2@amd.com> Signed-off-by: Ray Wu <ray.wu@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Matthew Stewart
Alex Deucher
parent
a3d3758b2e
commit
eb778d928b
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// SPDX-License-Identifier: MIT
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//
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// Copyright 2026 Advanced Micro Devices, Inc.
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#ifndef __DML_DML_DCN42B_SOC_BB__
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#define __DML_DML_DCN42B_SOC_BB__
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#include "dml_top_soc_parameter_types.h"
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/* DCN42B Bounding Box values */
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static const struct dml2_soc_qos_parameters dml_dcn42b_variant_a_soc_qos_params = {
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.derate_table = {
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.system_active_urgent = {
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.dram_derate_percent_pixel = 65,
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.dram_derate_percent_vm = 30,
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.dram_derate_percent_pixel_and_vm = 60,
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.fclk_derate_percent = 80,
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.dcfclk_derate_percent = 80,
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},
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.system_active_average = {
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.dram_derate_percent_pixel = 30,
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.dram_derate_percent_vm = 30,
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.dram_derate_percent_pixel_and_vm = 30,
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.fclk_derate_percent = 60,
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.dcfclk_derate_percent = 60,
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},
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.dcn_mall_prefetch_urgent = {
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.dram_derate_percent_pixel = 65,
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.dram_derate_percent_vm = 30,
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.dram_derate_percent_pixel_and_vm = 60,
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.fclk_derate_percent = 80,
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.dcfclk_derate_percent = 80,
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},
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.dcn_mall_prefetch_average = {
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.dram_derate_percent_pixel = 30,
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.dram_derate_percent_vm = 30,
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.dram_derate_percent_pixel_and_vm = 30,
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.fclk_derate_percent = 60,
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.dcfclk_derate_percent = 60,
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},
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.system_idle_average = {
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.dram_derate_percent_pixel = 30,
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.dram_derate_percent_vm = 30,
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.dram_derate_percent_pixel_and_vm = 30,
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.fclk_derate_percent = 60,
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.dcfclk_derate_percent = 60,
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},
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},
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.writeback = {
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.base_latency_us = 12,
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.scaling_factor_us = 0,
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.scaling_factor_mhz = 0,
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},
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.qos_params = {
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.dcn32x = {
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.loaded_round_trip_latency_fclk_cycles = 106,
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.urgent_latency_us = {
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.base_latency_us = 4,
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.base_latency_pixel_vm_us = 4,
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.base_latency_vm_us = 4,
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.scaling_factor_fclk_us = 0,
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.scaling_factor_mhz = 0,
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},
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.urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096,
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.urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096,
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.urgent_out_of_order_return_per_channel_vm_only_bytes = 4096,
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},
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},
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.qos_type = dml2_qos_param_type_dcn3,
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};
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static const struct dml2_soc_bb dml2_socbb_dcn42b = {
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.clk_table = {
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.wck_ratio = {
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.clk_values_khz = {2},
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},
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.uclk = {
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.clk_values_khz = {400000},
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.num_clk_values = 1,
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},
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.fclk = {
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.clk_values_khz = {1600000},
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.num_clk_values = 1,
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},
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.dcfclk = {
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.clk_values_khz = {800000},
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.num_clk_values = 1,
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},
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.dispclk = {
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.clk_values_khz = {1200000},
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.num_clk_values = 1,
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},
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.dppclk = {
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.clk_values_khz = {1200000},
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.num_clk_values = 1,
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},
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.dtbclk = {
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.clk_values_khz = {0},
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.num_clk_values = 0,
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},
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.phyclk = {
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.clk_values_khz = {810000},
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.num_clk_values = 1,
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},
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.socclk = {
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.clk_values_khz = {1600000},
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.num_clk_values = 1,
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},
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.dscclk = {
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.clk_values_khz = {400000},
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.num_clk_values = 1,
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},
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.phyclk_d18 = {
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.clk_values_khz = {667000},
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.num_clk_values = 1,
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},
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.phyclk_d32 = {
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.clk_values_khz = {625000},
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.num_clk_values = 1,
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},
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.dram_config = {
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.channel_width_bytes = 4,
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.channel_count = 4,
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.alt_clock_bw_conversion = true,
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},
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},
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.qos_parameters = {
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.derate_table = {
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.system_active_urgent = {
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.dram_derate_percent_pixel = 65,
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.dram_derate_percent_vm = 30,
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.dram_derate_percent_pixel_and_vm = 60,
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.fclk_derate_percent = 80,
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.dcfclk_derate_percent = 80,
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},
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.system_active_average = {
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.dram_derate_percent_pixel = 30,
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.dram_derate_percent_vm = 30,
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.dram_derate_percent_pixel_and_vm = 30,
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.fclk_derate_percent = 60,
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.dcfclk_derate_percent = 60,
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},
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.dcn_mall_prefetch_urgent = {
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.dram_derate_percent_pixel = 65,
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.dram_derate_percent_vm = 30,
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.dram_derate_percent_pixel_and_vm = 60,
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.fclk_derate_percent = 80,
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.dcfclk_derate_percent = 80,
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},
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.dcn_mall_prefetch_average = {
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.dram_derate_percent_pixel = 30,
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.dram_derate_percent_vm = 30,
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.dram_derate_percent_pixel_and_vm = 30,
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.fclk_derate_percent = 60,
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.dcfclk_derate_percent = 60,
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},
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.system_idle_average = {
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.dram_derate_percent_pixel = 30,
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.dram_derate_percent_vm = 30,
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.dram_derate_percent_pixel_and_vm = 30,
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.fclk_derate_percent = 60,
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.dcfclk_derate_percent = 60,
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},
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},
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.writeback = {
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.base_latency_us = 12,
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.scaling_factor_us = 0,
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.scaling_factor_mhz = 0,
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},
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.qos_params = {
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.dcn32x = {
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.loaded_round_trip_latency_fclk_cycles = 106,
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.urgent_latency_us = {
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.base_latency_us = 4,
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.base_latency_pixel_vm_us = 4,
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.base_latency_vm_us = 4,
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.scaling_factor_fclk_us = 0,
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.scaling_factor_mhz = 0,
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},
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.urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096,
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.urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096,
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.urgent_out_of_order_return_per_channel_vm_only_bytes = 4096,
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},
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},
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.qos_type = dml2_qos_param_type_dcn3,
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},
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/* Reuse of DCN42 params for LPDDR5/LPCAMM2 */
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.power_management_parameters = {
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.dram_clk_change_blackout_us = 36,
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.fclk_change_blackout_us = 0,
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.g7_ppt_blackout_us = 0,
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.stutter_enter_plus_exit_latency_us = 14,
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.stutter_exit_latency_us = 12,
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.z8_stutter_enter_plus_exit_latency_us = 300,
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.z8_stutter_exit_latency_us = 200,
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},
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.vmin_limit = {
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.dispclk_khz = 632 * 1000,
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},
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.dprefclk_mhz = 600,
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.xtalclk_mhz = 24,
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.pcie_refclk_mhz = 100,
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.dchub_refclk_mhz = 50,
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.mall_allocated_for_dcn_mbytes = 64,
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.max_outstanding_reqs = 256,
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.fabric_datapath_to_dcn_data_return_bytes = 32,
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.return_bus_width_bytes = 64,
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.hostvm_min_page_size_kbytes = 4,
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.gpuvm_min_page_size_kbytes = 256,
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.gpuvm_max_page_table_levels = 1,
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.hostvm_max_non_cached_page_table_levels = 2,
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.phy_downspread_percent = 0.38,
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.dcn_downspread_percent = 0.38,
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.dispclk_dppclk_vco_speed_mhz = 3000,
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.do_urgent_latency_adjustment = 0,
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.mem_word_bytes = 0,
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.num_dcc_mcaches = 0,
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.mcache_size_bytes = 0,
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.mcache_line_size_bytes = 0,
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.max_fclk_for_uclk_dpm_khz = 2200 * 1000,
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};
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#endif
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