Reset controller updates for v6.5

Use devm_platform_ioremap_resource() instead of platform_get_resource()
 and devm_ioremap_resource() in various drivers, simplify the stih407
 Kconfig and use regmap_field_read_poll_timeout() instead of open-coded
 waiting, and use dev_err_probe() in the meson-audio-arb reset driver.
 With its platform gone, remove the now obsolete oxnas reset driver.
 Drop depends on the non-user-visible CONFIG_AUXILIARY_BUS symbol.
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Merge tag 'reset-for-v6.5' of git://git.pengutronix.de/pza/linux into soc/drivers

Reset controller updates for v6.5

Use devm_platform_ioremap_resource() instead of platform_get_resource()
and devm_ioremap_resource() in various drivers, simplify the stih407
Kconfig and use regmap_field_read_poll_timeout() instead of open-coded
waiting, and use dev_err_probe() in the meson-audio-arb reset driver.
With its platform gone, remove the now obsolete oxnas reset driver.
Drop depends on the non-user-visible CONFIG_AUXILIARY_BUS symbol.

* tag 'reset-for-v6.5' of git://git.pengutronix.de/pza/linux:
  reset: mpfs: select AUXILIARY_BUS
  reset: starfive: select AUXILIARY_BUS
  reset: oxnas: remove obsolete reset driver
  reset: sti: simplify driver's config and build
  reset: meson-audio-arb: Use dev_err_probe()
  reset: sti: rely on regmap_field_read_poll_timeout for ack wait
  reset: brcmstb-rescal: Use devm_platform_ioremap_resource()
  reset: meson: Use devm_platform_ioremap_resource()
  reset: reset-hsdk: Use devm_platform_ioremap_resource()
  reset: lpc18xx: Use devm_platform_ioremap_resource()
  reset: axs10x: Use devm_platform_ioremap_resource()
  reset: ath79: Use devm_platform_ioremap_resource()

Link: https://lore.kernel.org/r/20230511133235.874566-1-p.zabel@pengutronix.de
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2023-05-26 13:42:50 +02:00
commit eaae5a8977
15 changed files with 18 additions and 198 deletions

View File

@ -1,32 +0,0 @@
Oxford Semiconductor OXNAS SoC Family RESET Controller
================================================
Please also refer to reset.txt in this directory for common reset
controller binding usage.
Required properties:
- compatible: For OX810SE, should be "oxsemi,ox810se-reset"
For OX820, should be "oxsemi,ox820-reset"
- #reset-cells: 1, see below
Parent node should have the following properties :
- compatible: For OX810SE, should be :
"oxsemi,ox810se-sys-ctrl", "syscon", "simple-mfd"
For OX820, should be :
"oxsemi,ox820-sys-ctrl", "syscon", "simple-mfd"
Reset indices are in dt-bindings include files :
- For OX810SE: include/dt-bindings/reset/oxsemi,ox810se.h
- For OX820: include/dt-bindings/reset/oxsemi,ox820.h
example:
sys: sys-ctrl@000000 {
compatible = "oxsemi,ox810se-sys-ctrl", "syscon", "simple-mfd";
reg = <0x000000 0x100000>;
reset: reset-controller {
compatible = "oxsemi,ox810se-reset";
#reset-cells = <1>;
};
};

View File

@ -143,9 +143,6 @@ config RESET_NPCM
This enables the reset controller driver for Nuvoton NPCM
BMC SoCs.
config RESET_OXNAS
bool
config RESET_PISTACHIO
bool "Pistachio Reset Driver"
depends on MIPS || COMPILE_TEST
@ -154,7 +151,8 @@ config RESET_PISTACHIO
config RESET_POLARFIRE_SOC
bool "Microchip PolarFire SoC (MPFS) Reset Driver"
depends on AUXILIARY_BUS && MCHP_CLK_MPFS
depends on MCHP_CLK_MPFS
select AUXILIARY_BUS
default MCHP_CLK_MPFS
help
This driver supports peripheral reset for the Microchip PolarFire SoC

View File

@ -21,7 +21,6 @@ obj-$(CONFIG_RESET_MCHP_SPARX5) += reset-microchip-sparx5.o
obj-$(CONFIG_RESET_MESON) += reset-meson.o
obj-$(CONFIG_RESET_MESON_AUDIO_ARB) += reset-meson-audio-arb.o
obj-$(CONFIG_RESET_NPCM) += reset-npcm.o
obj-$(CONFIG_RESET_OXNAS) += reset-oxnas.o
obj-$(CONFIG_RESET_PISTACHIO) += reset-pistachio.o
obj-$(CONFIG_RESET_POLARFIRE_SOC) += reset-mpfs.o
obj-$(CONFIG_RESET_QCOM_AOSS) += reset-qcom-aoss.o

View File

@ -86,7 +86,6 @@ static int ath79_reset_restart_handler(struct notifier_block *nb,
static int ath79_reset_probe(struct platform_device *pdev)
{
struct ath79_reset *ath79_reset;
struct resource *res;
int err;
ath79_reset = devm_kzalloc(&pdev->dev,
@ -96,8 +95,7 @@ static int ath79_reset_probe(struct platform_device *pdev)
platform_set_drvdata(pdev, ath79_reset);
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
ath79_reset->base = devm_ioremap_resource(&pdev->dev, res);
ath79_reset->base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(ath79_reset->base))
return PTR_ERR(ath79_reset->base);

View File

@ -44,14 +44,12 @@ static const struct reset_control_ops axs10x_reset_ops = {
static int axs10x_reset_probe(struct platform_device *pdev)
{
struct axs10x_rst *rst;
struct resource *mem;
rst = devm_kzalloc(&pdev->dev, sizeof(*rst), GFP_KERNEL);
if (!rst)
return -ENOMEM;
mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
rst->regs_rst = devm_ioremap_resource(&pdev->dev, mem);
rst->regs_rst = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(rst->regs_rst))
return PTR_ERR(rst->regs_rst);

View File

@ -66,14 +66,12 @@ static const struct reset_control_ops brcm_rescal_reset_ops = {
static int brcm_rescal_reset_probe(struct platform_device *pdev)
{
struct brcm_rescal_reset *data;
struct resource *res;
data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
if (!data)
return -ENOMEM;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
data->base = devm_ioremap_resource(&pdev->dev, res);
data->base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(data->base))
return PTR_ERR(data->base);

View File

@ -92,19 +92,16 @@ static const struct reset_control_ops hsdk_reset_ops = {
static int hsdk_reset_probe(struct platform_device *pdev)
{
struct hsdk_rst *rst;
struct resource *mem;
rst = devm_kzalloc(&pdev->dev, sizeof(*rst), GFP_KERNEL);
if (!rst)
return -ENOMEM;
mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
rst->regs_ctl = devm_ioremap_resource(&pdev->dev, mem);
rst->regs_ctl = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(rst->regs_ctl))
return PTR_ERR(rst->regs_ctl);
mem = platform_get_resource(pdev, IORESOURCE_MEM, 1);
rst->regs_rst = devm_ioremap_resource(&pdev->dev, mem);
rst->regs_rst = devm_platform_ioremap_resource(pdev, 1);
if (IS_ERR(rst->regs_rst))
return PTR_ERR(rst->regs_rst);

View File

@ -139,7 +139,6 @@ static const struct reset_control_ops lpc18xx_rgu_ops = {
static int lpc18xx_rgu_probe(struct platform_device *pdev)
{
struct lpc18xx_rgu_data *rc;
struct resource *res;
u32 fcclk, firc;
int ret;
@ -147,8 +146,7 @@ static int lpc18xx_rgu_probe(struct platform_device *pdev)
if (!rc)
return -ENOMEM;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
rc->base = devm_ioremap_resource(&pdev->dev, res);
rc->base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(rc->base))
return PTR_ERR(rc->base);

View File

@ -151,11 +151,8 @@ static int meson_audio_arb_probe(struct platform_device *pdev)
platform_set_drvdata(pdev, arb);
arb->clk = devm_clk_get(dev, NULL);
if (IS_ERR(arb->clk)) {
if (PTR_ERR(arb->clk) != -EPROBE_DEFER)
dev_err(dev, "failed to get clock\n");
return PTR_ERR(arb->clk);
}
if (IS_ERR(arb->clk))
return dev_err_probe(dev, PTR_ERR(arb->clk), "failed to get clock\n");
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
arb->regs = devm_ioremap_resource(dev, res);

View File

@ -116,14 +116,12 @@ MODULE_DEVICE_TABLE(of, meson_reset_dt_ids);
static int meson_reset_probe(struct platform_device *pdev)
{
struct meson_reset *data;
struct resource *res;
data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
if (!data)
return -ENOMEM;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
data->reg_base = devm_ioremap_resource(&pdev->dev, res);
data->reg_base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(data->reg_base))
return PTR_ERR(data->reg_base);

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@ -1,114 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Oxford Semiconductor Reset Controller driver
*
* Copyright (C) 2016 Neil Armstrong <narmstrong@baylibre.com>
* Copyright (C) 2014 Ma Haijun <mahaijuns@gmail.com>
* Copyright (C) 2009 Oxford Semiconductor Ltd
*/
#include <linux/err.h>
#include <linux/init.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/reset-controller.h>
#include <linux/slab.h>
#include <linux/delay.h>
#include <linux/types.h>
#include <linux/regmap.h>
#include <linux/mfd/syscon.h>
/* Regmap offsets */
#define RST_SET_REGOFFSET 0x34
#define RST_CLR_REGOFFSET 0x38
struct oxnas_reset {
struct regmap *regmap;
struct reset_controller_dev rcdev;
};
static int oxnas_reset_reset(struct reset_controller_dev *rcdev,
unsigned long id)
{
struct oxnas_reset *data =
container_of(rcdev, struct oxnas_reset, rcdev);
regmap_write(data->regmap, RST_SET_REGOFFSET, BIT(id));
msleep(50);
regmap_write(data->regmap, RST_CLR_REGOFFSET, BIT(id));
return 0;
}
static int oxnas_reset_assert(struct reset_controller_dev *rcdev,
unsigned long id)
{
struct oxnas_reset *data =
container_of(rcdev, struct oxnas_reset, rcdev);
regmap_write(data->regmap, RST_SET_REGOFFSET, BIT(id));
return 0;
}
static int oxnas_reset_deassert(struct reset_controller_dev *rcdev,
unsigned long id)
{
struct oxnas_reset *data =
container_of(rcdev, struct oxnas_reset, rcdev);
regmap_write(data->regmap, RST_CLR_REGOFFSET, BIT(id));
return 0;
}
static const struct reset_control_ops oxnas_reset_ops = {
.reset = oxnas_reset_reset,
.assert = oxnas_reset_assert,
.deassert = oxnas_reset_deassert,
};
static const struct of_device_id oxnas_reset_dt_ids[] = {
{ .compatible = "oxsemi,ox810se-reset", },
{ .compatible = "oxsemi,ox820-reset", },
{ /* sentinel */ },
};
static int oxnas_reset_probe(struct platform_device *pdev)
{
struct oxnas_reset *data;
struct device *parent;
parent = pdev->dev.parent;
if (!parent) {
dev_err(&pdev->dev, "no parent\n");
return -ENODEV;
}
data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
if (!data)
return -ENOMEM;
data->regmap = syscon_node_to_regmap(parent->of_node);
if (IS_ERR(data->regmap)) {
dev_err(&pdev->dev, "failed to get parent regmap\n");
return PTR_ERR(data->regmap);
}
platform_set_drvdata(pdev, data);
data->rcdev.owner = THIS_MODULE;
data->rcdev.nr_resets = 32;
data->rcdev.ops = &oxnas_reset_ops;
data->rcdev.of_node = pdev->dev.of_node;
return devm_reset_controller_register(&pdev->dev, &data->rcdev);
}
static struct platform_driver oxnas_reset_driver = {
.probe = oxnas_reset_probe,
.driver = {
.name = "oxnas-reset",
.of_match_table = oxnas_reset_dt_ids,
},
};
builtin_platform_driver(oxnas_reset_driver);

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@ -13,7 +13,8 @@ config RESET_STARFIVE_JH7100
config RESET_STARFIVE_JH7110
bool "StarFive JH7110 Reset Driver"
depends on AUXILIARY_BUS && CLK_STARFIVE_JH7110_SYS
depends on CLK_STARFIVE_JH7110_SYS
select AUXILIARY_BUS
select RESET_STARFIVE_JH71X0
default ARCH_STARFIVE
help

View File

@ -1,11 +1,7 @@
# SPDX-License-Identifier: GPL-2.0-only
if ARCH_STI
config STI_RESET_SYSCFG
bool
config STIH407_RESET
bool
select STI_RESET_SYSCFG
endif

View File

@ -1,4 +1,2 @@
# SPDX-License-Identifier: GPL-2.0-only
obj-$(CONFIG_STI_RESET_SYSCFG) += reset-syscfg.o
obj-$(CONFIG_STIH407_RESET) += reset-stih407.o
obj-$(CONFIG_STIH407_RESET) += reset-stih407.o reset-syscfg.o

View File

@ -64,22 +64,12 @@ static int syscfg_reset_program_hw(struct reset_controller_dev *rcdev,
return err;
if (ch->ack) {
unsigned long timeout = jiffies + msecs_to_jiffies(1000);
u32 ack_val;
while (true) {
err = regmap_field_read(ch->ack, &ack_val);
if (err)
return err;
if (ack_val == ctrl_val)
break;
if (time_after(jiffies, timeout))
return -ETIME;
cpu_relax();
}
err = regmap_field_read_poll_timeout(ch->ack, ack_val, (ack_val == ctrl_val),
100, USEC_PER_SEC);
if (err)
return err;
}
return 0;