Renesas driver updates for v6.5

- Enable watchdog reset support on R-Car V3U.
 -----BEGIN PGP SIGNATURE-----
 
 iHUEABYIAB0WIQQ9qaHoIs/1I4cXmEiKwlD9ZEnxcAUCZHB7hQAKCRCKwlD9ZEnx
 cKdlAP0VjCU7cPjrtpRjzJy12fdZvwf4vQdTIileHeb28JDFawD/edRTza24wBGW
 tA5E/nj+U6rAfrf6MtFrTTmQjJSlmAw=
 =rLVq
 -----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCgAdFiEEiK/NIGsWEZVxh/FrYKtH/8kJUicFAmRwmt4ACgkQYKtH/8kJ
 UicvOg/8DfO30l9t8KaDNeNVTRDrOd0PP0uBG6cheAEdXy9sM+JleiWBJFdJgmGO
 KLGyLZVXuUTn1RD2xJKAgBLDd7jhQvoATf46orWtVrxun3PUI5NSJDcDChPP2pPj
 exdqMy7Gz+U+TlzqBZGDKjABNOKSwYUG+6wPidGvQ6LLQpyqO0E7rCl4f5KRYCDj
 U2qLmHNwTRP2KlOyhniEz7a9uk1mHxDNkmfvLZKWdh0TVeC9mDeAW9sURHaxVe/q
 /n7LvJtfjGIJQiz7ScSS4e3+K7fPOQ3na+lchk3PX9Dg31qYytl5bbpS6JpRTW8o
 c/33snSyOp9zuh+p315npd55c5BvKZHqJBPtMmxMtmsevixfpT7+FX5JZmQ7Z+ND
 PpJ1BgJ/9cOTff16oUk36Zr9RuFJqriefL4GeOUnUYblnz19yLYCnTP2a5q0eZNB
 8d/jvEQ5zM2umGyB9BxnsMyxC75KZ1QjnFge0q+qAXAVUpa72P3rltFT32ZW4B/Y
 ht+FnNa1wZhKtDOIEwFyDFhP1d7pN5ozDI0DfTDRL332hToNZ1nbm+QKb/hrRsSp
 MMtSqvSXh55sT1I7r5iYjkRc7lv0zu/cm5up3qU8ybvfchjlVIMh1n9oPq1+8sUE
 IhrrjE+LiX8dJGnvaIAx99W12BKPXsv4zj1CUEaD2fa+v/pC/BI=
 =YGZn
 -----END PGP SIGNATURE-----

Merge tag 'renesas-drivers-for-v6.5-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/drivers

Renesas driver updates for v6.5

  - Enable watchdog reset support on R-Car V3U.

* tag 'renesas-drivers-for-v6.5-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel:
  soc: renesas: rcar-rst: Allow WDT reset on R-Car V3U

Link: https://lore.kernel.org/r/cover.1685094242.git.geert+renesas@glider.be
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2023-05-26 13:41:18 +02:00
commit 2336ce7f45

View File

@ -12,6 +12,7 @@
#define WDTRSTCR_RESET 0xA55A0002
#define WDTRSTCR 0x0054
#define GEN4_WDTRSTCR 0x0010
#define CR7BAR 0x0070
#define CR7BAREN BIT(4)
@ -27,6 +28,12 @@ static int rcar_rst_enable_wdt_reset(void __iomem *base)
return 0;
}
static int rcar_rst_v3u_enable_wdt_reset(void __iomem *base)
{
iowrite32(WDTRSTCR_RESET, base + GEN4_WDTRSTCR);
return 0;
}
/*
* Most of the R-Car Gen3 SoCs have an ARM Realtime Core.
* Firmware boot address has to be set in CR7BAR before
@ -66,6 +73,12 @@ static const struct rst_config rcar_rst_gen3 __initconst = {
.set_rproc_boot_addr = rcar_rst_set_gen3_rproc_boot_addr,
};
/* V3U firmware doesn't enable WDT reset and there won't be updates anymore */
static const struct rst_config rcar_rst_v3u __initconst = {
.modemr = 0x00, /* MODEMR0 and it has CPG related bits */
.configure = rcar_rst_v3u_enable_wdt_reset,
};
static const struct rst_config rcar_rst_gen4 __initconst = {
.modemr = 0x00, /* MODEMR0 and it has CPG related bits */
};
@ -101,7 +114,7 @@ static const struct of_device_id rcar_rst_matches[] __initconst = {
{ .compatible = "renesas,r8a77990-rst", .data = &rcar_rst_gen3 },
{ .compatible = "renesas,r8a77995-rst", .data = &rcar_rst_gen3 },
/* R-Car Gen4 */
{ .compatible = "renesas,r8a779a0-rst", .data = &rcar_rst_gen4 },
{ .compatible = "renesas,r8a779a0-rst", .data = &rcar_rst_v3u },
{ .compatible = "renesas,r8a779f0-rst", .data = &rcar_rst_gen4 },
{ .compatible = "renesas,r8a779g0-rst", .data = &rcar_rst_gen4 },
{ /* sentinel */ }