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clk: rockchip: rk3308: Add some new clocks
Add clock for pwm1, pwm2, can, owire. Change-Id: Id9a9330da359c3d2c53ae0f0f2e41cf4ff495cc4 Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
This commit is contained in:
Finley Xiao
Tao Huang
parent
726122dc14
commit
ea0d7ad774
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@ -609,7 +609,7 @@ pwm0: pwm@ff180000 {
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#pwm-cells = <3>;
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pinctrl-names = "active";
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pinctrl-0 = <&pwm0_pin>;
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clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
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clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
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clock-names = "pwm", "pclk";
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status = "disabled";
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};
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@ -620,7 +620,7 @@ pwm1: pwm@ff180010 {
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#pwm-cells = <3>;
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pinctrl-names = "active";
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pinctrl-0 = <&pwm1_pin>;
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clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
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clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
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clock-names = "pwm", "pclk";
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status = "disabled";
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};
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@ -631,7 +631,7 @@ pwm2: pwm@ff180020 {
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#pwm-cells = <3>;
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pinctrl-names = "active";
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pinctrl-0 = <&pwm2_pin>;
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clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
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clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
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clock-names = "pwm", "pclk";
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status = "disabled";
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};
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@ -642,7 +642,7 @@ pwm3: pwm@ff180030 {
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#pwm-cells = <3>;
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pinctrl-names = "active";
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pinctrl-0 = <&pwm3_pin>;
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clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
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clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
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clock-names = "pwm", "pclk";
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status = "disabled";
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};
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@ -403,9 +403,15 @@ static struct rockchip_clk_branch rk3308_clk_branches[] __initdata = {
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RK3308_CLKSEL_CON(28), 14, 2, MFLAGS, 0, 7, DFLAGS,
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RK3308_CLKGATE_CON(3), 0, GFLAGS),
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COMPOSITE(SCLK_PWM, "clk_pwm", mux_dpll_vpll0_xin24m_p, 0,
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COMPOSITE(SCLK_PWM0, "clk_pwm0", mux_dpll_vpll0_xin24m_p, 0,
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RK3308_CLKSEL_CON(29), 14, 2, MFLAGS, 0, 7, DFLAGS,
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RK3308_CLKGATE_CON(3), 1, GFLAGS),
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COMPOSITE(SCLK_PWM1, "clk_pwm1", mux_dpll_vpll0_xin24m_p, 0,
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RK3308_CLKSEL_CON(74), 14, 2, MFLAGS, 0, 7, DFLAGS,
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RK3308_CLKGATE_CON(15), 0, GFLAGS),
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COMPOSITE(SCLK_PWM2, "clk_pwm2", mux_dpll_vpll0_xin24m_p, 0,
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RK3308_CLKSEL_CON(75), 14, 2, MFLAGS, 0, 7, DFLAGS,
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RK3308_CLKGATE_CON(15), 1, GFLAGS),
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COMPOSITE(SCLK_SPI0, "clk_isp0", mux_dpll_vpll0_xin24m_p, 0,
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RK3308_CLKSEL_CON(30), 14, 2, MFLAGS, 0, 7, DFLAGS,
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@ -548,6 +554,10 @@ static struct rockchip_clk_branch rk3308_clk_branches[] __initdata = {
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MUX(SCLK_MAC_RMII, "clk_mac_rmii_sel", mux_mac_rmii_sel_p, CLK_SET_RATE_PARENT,
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RK3308_CLKSEL_CON(43), 15, 1, MFLAGS),
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COMPOSITE(SCLK_OWIRE, "clk_owire", mux_dpll_vpll0_xin24m_p, 0,
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RK3308_CLKSEL_CON(44), 14, 2, MFLAGS, 8, 6, DFLAGS,
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RK3308_CLKGATE_CON(8), 15, GFLAGS),
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/*
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* Clock-Architecture Diagram 5
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*/
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@ -864,7 +874,7 @@ static struct rockchip_clk_branch rk3308_clk_branches[] __initdata = {
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GATE(PCLK_I2C1, "pclk_i2c1", "pclk_bus", 0, RK3308_CLKGATE_CON(6), 0, GFLAGS),
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GATE(PCLK_I2C2, "pclk_i2c2", "pclk_bus", 0, RK3308_CLKGATE_CON(6), 1, GFLAGS),
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GATE(PCLK_I2C3, "pclk_i2c3", "pclk_bus", 0, RK3308_CLKGATE_CON(6), 2, GFLAGS),
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GATE(PCLK_PWM, "pclk_pwm", "pclk_bus", 0, RK3308_CLKGATE_CON(6), 3, GFLAGS),
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GATE(PCLK_PWM0, "pclk_pwm0", "pclk_bus", 0, RK3308_CLKGATE_CON(6), 3, GFLAGS),
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GATE(PCLK_SPI0, "pclk_spi0", "pclk_bus", 0, RK3308_CLKGATE_CON(6), 4, GFLAGS),
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GATE(PCLK_SPI1, "pclk_spi1", "pclk_bus", 0, RK3308_CLKGATE_CON(6), 5, GFLAGS),
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GATE(PCLK_SPI2, "pclk_spi2", "pclk_bus", 0, RK3308_CLKGATE_CON(6), 6, GFLAGS),
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@ -888,6 +898,10 @@ static struct rockchip_clk_branch rk3308_clk_branches[] __initdata = {
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GATE(PCLK_CRU, "pclk_cru", "pclk_bus", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(7), 9, GFLAGS),
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GATE(PCLK_OTP_PHY, "pclk_otp_phy", "pclk_bus", 0, RK3308_CLKGATE_CON(7), 10, GFLAGS),
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GATE(PCLK_CPU_BOOST, "pclk_cpu_boost", "pclk_bus", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(7), 11, GFLAGS),
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GATE(PCLK_PWM1, "pclk_pwm1", "pclk_bus", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(7), 12, GFLAGS),
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GATE(PCLK_PWM2, "pclk_pwm2", "pclk_bus", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(7), 13, GFLAGS),
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GATE(PCLK_CAN, "pclk_can", "pclk_bus", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(7), 14, GFLAGS),
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GATE(PCLK_OWIRE, "pclk_owire", "pclk_bus", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(7), 15, GFLAGS),
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};
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static const char *const rk3308_critical_clocks[] __initconst = {
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@ -36,7 +36,7 @@
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#define SCLK_I2C1 23
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#define SCLK_I2C2 24
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#define SCLK_I2C3 25
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#define SCLK_PWM 26
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#define SCLK_PWM0 26
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#define SCLK_SPI0 27
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#define SCLK_SPI1 28
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#define SCLK_SPI2 29
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@ -130,9 +130,12 @@
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#define SCLK_I2S3_8CH_RX_SRC 117
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#define SCLK_I2S0_2CH_SRC 118
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#define SCLK_I2S1_2CH_SRC 119
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#define SCLK_PWM1 120
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#define SCLK_PWM2 121
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#define SCLK_OWIRE 122
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/* dclk */
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#define DCLK_VOP 120
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#define DCLK_VOP 125
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/* aclk */
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#define ACLK_BUS_SRC 130
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@ -188,7 +191,7 @@
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#define PCLK_I2C1 203
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#define PCLK_I2C2 204
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#define PCLK_I2C3 205
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#define PCLK_PWM 206
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#define PCLK_PWM0 206
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#define PCLK_SPI0 207
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#define PCLK_SPI1 208
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#define PCLK_SPI2 209
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@ -213,8 +216,12 @@
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#define PCLK_CRU 228
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#define PCLK_OTP_PHY 229
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#define PCLK_CPU_BOOST 230
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#define PCLK_PWM1 231
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#define PCLK_PWM2 232
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#define PCLK_CAN 233
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#define PCLK_OWIRE 234
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#define CLK_NR_CLKS (PCLK_CPU_BOOST + 1)
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#define CLK_NR_CLKS (PCLK_OWIRE + 1)
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/* soft-reset indices */
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@ -284,8 +291,8 @@
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#define SRST_I2C2 59
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#define SRST_I2C3_P 60
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#define SRST_I2C3 61
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#define SRST_PWM_P 62
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#define SRST_PWM 63
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#define SRST_PWM0_P 62
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#define SRST_PWM0 63
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/* cru_softrst_con4 */
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#define SRST_SPI0_P 64
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@ -325,6 +332,10 @@
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/* cru_softrst_con6 */
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#define SRST_CPU_BOOST 96
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#define SRST_CPU_BOOST_P 97
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#define SRST_PWM1_P 98
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#define SRST_PWM1 99
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#define SRST_PWM2_P 100
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#define SRST_PWM2 101
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#define SRST_PERI_NIU_A 104
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#define SRST_PERI_NIU_H 105
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#define SRST_PERI_NIU_p 106
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@ -349,6 +360,8 @@
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#define SRST_NANDC_H 123
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#define SRST_NANDC_N 124
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#define SRST_MAC_A 125
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#define SRST_CAN_P 126
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#define SRST_OWIRE_P 127
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/* cru_softrst_con8 */
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#define SRST_AUDIO_NIU_H 128
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