From ea0d7ad774679593f5badb594577359f407aa7f4 Mon Sep 17 00:00:00 2001 From: Finley Xiao Date: Tue, 28 Aug 2018 14:56:41 +0800 Subject: [PATCH] clk: rockchip: rk3308: Add some new clocks Add clock for pwm1, pwm2, can, owire. Change-Id: Id9a9330da359c3d2c53ae0f0f2e41cf4ff495cc4 Signed-off-by: Finley Xiao --- arch/arm64/boot/dts/rockchip/rk3308.dtsi | 8 ++++---- drivers/clk/rockchip/clk-rk3308.c | 18 +++++++++++++++-- include/dt-bindings/clock/rk3308-cru.h | 25 ++++++++++++++++++------ 3 files changed, 39 insertions(+), 12 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3308.dtsi b/arch/arm64/boot/dts/rockchip/rk3308.dtsi index 030ef4932ede..61d6d06f169b 100644 --- a/arch/arm64/boot/dts/rockchip/rk3308.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3308.dtsi @@ -609,7 +609,7 @@ pwm0: pwm@ff180000 { #pwm-cells = <3>; pinctrl-names = "active"; pinctrl-0 = <&pwm0_pin>; - clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; + clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; clock-names = "pwm", "pclk"; status = "disabled"; }; @@ -620,7 +620,7 @@ pwm1: pwm@ff180010 { #pwm-cells = <3>; pinctrl-names = "active"; pinctrl-0 = <&pwm1_pin>; - clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; + clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; clock-names = "pwm", "pclk"; status = "disabled"; }; @@ -631,7 +631,7 @@ pwm2: pwm@ff180020 { #pwm-cells = <3>; pinctrl-names = "active"; pinctrl-0 = <&pwm2_pin>; - clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; + clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; clock-names = "pwm", "pclk"; status = "disabled"; }; @@ -642,7 +642,7 @@ pwm3: pwm@ff180030 { #pwm-cells = <3>; pinctrl-names = "active"; pinctrl-0 = <&pwm3_pin>; - clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; + clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; clock-names = "pwm", "pclk"; status = "disabled"; }; diff --git a/drivers/clk/rockchip/clk-rk3308.c b/drivers/clk/rockchip/clk-rk3308.c index 0cd2928ee94f..bb6cf8e006bc 100644 --- a/drivers/clk/rockchip/clk-rk3308.c +++ b/drivers/clk/rockchip/clk-rk3308.c @@ -403,9 +403,15 @@ static struct rockchip_clk_branch rk3308_clk_branches[] __initdata = { RK3308_CLKSEL_CON(28), 14, 2, MFLAGS, 0, 7, DFLAGS, RK3308_CLKGATE_CON(3), 0, GFLAGS), - COMPOSITE(SCLK_PWM, "clk_pwm", mux_dpll_vpll0_xin24m_p, 0, + COMPOSITE(SCLK_PWM0, "clk_pwm0", mux_dpll_vpll0_xin24m_p, 0, RK3308_CLKSEL_CON(29), 14, 2, MFLAGS, 0, 7, DFLAGS, RK3308_CLKGATE_CON(3), 1, GFLAGS), + COMPOSITE(SCLK_PWM1, "clk_pwm1", mux_dpll_vpll0_xin24m_p, 0, + RK3308_CLKSEL_CON(74), 14, 2, MFLAGS, 0, 7, DFLAGS, + RK3308_CLKGATE_CON(15), 0, GFLAGS), + COMPOSITE(SCLK_PWM2, "clk_pwm2", mux_dpll_vpll0_xin24m_p, 0, + RK3308_CLKSEL_CON(75), 14, 2, MFLAGS, 0, 7, DFLAGS, + RK3308_CLKGATE_CON(15), 1, GFLAGS), COMPOSITE(SCLK_SPI0, "clk_isp0", mux_dpll_vpll0_xin24m_p, 0, RK3308_CLKSEL_CON(30), 14, 2, MFLAGS, 0, 7, DFLAGS, @@ -548,6 +554,10 @@ static struct rockchip_clk_branch rk3308_clk_branches[] __initdata = { MUX(SCLK_MAC_RMII, "clk_mac_rmii_sel", mux_mac_rmii_sel_p, CLK_SET_RATE_PARENT, RK3308_CLKSEL_CON(43), 15, 1, MFLAGS), + COMPOSITE(SCLK_OWIRE, "clk_owire", mux_dpll_vpll0_xin24m_p, 0, + RK3308_CLKSEL_CON(44), 14, 2, MFLAGS, 8, 6, DFLAGS, + RK3308_CLKGATE_CON(8), 15, GFLAGS), + /* * Clock-Architecture Diagram 5 */ @@ -864,7 +874,7 @@ static struct rockchip_clk_branch rk3308_clk_branches[] __initdata = { GATE(PCLK_I2C1, "pclk_i2c1", "pclk_bus", 0, RK3308_CLKGATE_CON(6), 0, GFLAGS), GATE(PCLK_I2C2, "pclk_i2c2", "pclk_bus", 0, RK3308_CLKGATE_CON(6), 1, GFLAGS), GATE(PCLK_I2C3, "pclk_i2c3", "pclk_bus", 0, RK3308_CLKGATE_CON(6), 2, GFLAGS), - GATE(PCLK_PWM, "pclk_pwm", "pclk_bus", 0, RK3308_CLKGATE_CON(6), 3, GFLAGS), + GATE(PCLK_PWM0, "pclk_pwm0", "pclk_bus", 0, RK3308_CLKGATE_CON(6), 3, GFLAGS), GATE(PCLK_SPI0, "pclk_spi0", "pclk_bus", 0, RK3308_CLKGATE_CON(6), 4, GFLAGS), GATE(PCLK_SPI1, "pclk_spi1", "pclk_bus", 0, RK3308_CLKGATE_CON(6), 5, GFLAGS), GATE(PCLK_SPI2, "pclk_spi2", "pclk_bus", 0, RK3308_CLKGATE_CON(6), 6, GFLAGS), @@ -888,6 +898,10 @@ static struct rockchip_clk_branch rk3308_clk_branches[] __initdata = { GATE(PCLK_CRU, "pclk_cru", "pclk_bus", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(7), 9, GFLAGS), GATE(PCLK_OTP_PHY, "pclk_otp_phy", "pclk_bus", 0, RK3308_CLKGATE_CON(7), 10, GFLAGS), GATE(PCLK_CPU_BOOST, "pclk_cpu_boost", "pclk_bus", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(7), 11, GFLAGS), + GATE(PCLK_PWM1, "pclk_pwm1", "pclk_bus", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(7), 12, GFLAGS), + GATE(PCLK_PWM2, "pclk_pwm2", "pclk_bus", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(7), 13, GFLAGS), + GATE(PCLK_CAN, "pclk_can", "pclk_bus", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(7), 14, GFLAGS), + GATE(PCLK_OWIRE, "pclk_owire", "pclk_bus", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(7), 15, GFLAGS), }; static const char *const rk3308_critical_clocks[] __initconst = { diff --git a/include/dt-bindings/clock/rk3308-cru.h b/include/dt-bindings/clock/rk3308-cru.h index 7ba1b86ccd69..5088a0f6fb02 100644 --- a/include/dt-bindings/clock/rk3308-cru.h +++ b/include/dt-bindings/clock/rk3308-cru.h @@ -36,7 +36,7 @@ #define SCLK_I2C1 23 #define SCLK_I2C2 24 #define SCLK_I2C3 25 -#define SCLK_PWM 26 +#define SCLK_PWM0 26 #define SCLK_SPI0 27 #define SCLK_SPI1 28 #define SCLK_SPI2 29 @@ -130,9 +130,12 @@ #define SCLK_I2S3_8CH_RX_SRC 117 #define SCLK_I2S0_2CH_SRC 118 #define SCLK_I2S1_2CH_SRC 119 +#define SCLK_PWM1 120 +#define SCLK_PWM2 121 +#define SCLK_OWIRE 122 /* dclk */ -#define DCLK_VOP 120 +#define DCLK_VOP 125 /* aclk */ #define ACLK_BUS_SRC 130 @@ -188,7 +191,7 @@ #define PCLK_I2C1 203 #define PCLK_I2C2 204 #define PCLK_I2C3 205 -#define PCLK_PWM 206 +#define PCLK_PWM0 206 #define PCLK_SPI0 207 #define PCLK_SPI1 208 #define PCLK_SPI2 209 @@ -213,8 +216,12 @@ #define PCLK_CRU 228 #define PCLK_OTP_PHY 229 #define PCLK_CPU_BOOST 230 +#define PCLK_PWM1 231 +#define PCLK_PWM2 232 +#define PCLK_CAN 233 +#define PCLK_OWIRE 234 -#define CLK_NR_CLKS (PCLK_CPU_BOOST + 1) +#define CLK_NR_CLKS (PCLK_OWIRE + 1) /* soft-reset indices */ @@ -284,8 +291,8 @@ #define SRST_I2C2 59 #define SRST_I2C3_P 60 #define SRST_I2C3 61 -#define SRST_PWM_P 62 -#define SRST_PWM 63 +#define SRST_PWM0_P 62 +#define SRST_PWM0 63 /* cru_softrst_con4 */ #define SRST_SPI0_P 64 @@ -325,6 +332,10 @@ /* cru_softrst_con6 */ #define SRST_CPU_BOOST 96 #define SRST_CPU_BOOST_P 97 +#define SRST_PWM1_P 98 +#define SRST_PWM1 99 +#define SRST_PWM2_P 100 +#define SRST_PWM2 101 #define SRST_PERI_NIU_A 104 #define SRST_PERI_NIU_H 105 #define SRST_PERI_NIU_p 106 @@ -349,6 +360,8 @@ #define SRST_NANDC_H 123 #define SRST_NANDC_N 124 #define SRST_MAC_A 125 +#define SRST_CAN_P 126 +#define SRST_OWIRE_P 127 /* cru_softrst_con8 */ #define SRST_AUDIO_NIU_H 128