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ARM: dts: imx: remove redundant intermediate node in pinmux hierarchy

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Remove the redundant intermediate node between the pinmux and group nodes,
and add the missing "grp" suffix to the group node names.

Fix below CHECK_DTBS warnings:
arm/boot/dts/nxp/imx/imx27-apf27dev.dtb: iomuxc@10015000 (fsl,imx27-iomuxc): Unevaluated properties are not allowed ('imx27-apf27', 'imx27-apf27dev' were unexpected)
        from schema $id: http://devicetree.org/schemas/pinctrl/fsl,imx27-iomuxc.yaml

Signed-off-by: Frank Li <Frank.Li@nxp.com>
This commit is contained in:
Frank Li 2026-02-11 16:00:03 -05:00
parent 81469ef61c
commit e948cbdc41
15 changed files with 974 additions and 1004 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
arch/arm/boot/dts/nxp/imx/imx1-ads.dts
View File

@ -76,7 +76,6 @@ nor: flash@0,0 {
}; };
&iomuxc { &iomuxc {
imx1-ads {
pinctrl_cspi1: cspi1grp { pinctrl_cspi1: cspi1grp {
fsl,pins = < fsl,pins = <
MX1_PAD_SPI1_MISO__SPI1_MISO 0x0 MX1_PAD_SPI1_MISO__SPI1_MISO 0x0
@ -132,4 +131,3 @@ MX1_PAD_LBA__LBA 0x0
>; >;
}; };
}; };
};

2
arch/arm/boot/dts/nxp/imx/imx1-apf9328.dts
View File

@ -67,7 +67,6 @@ eth: ethernet@4,c00000 {
}; };
&iomuxc { &iomuxc {
imx1-apf9328 {
pinctrl_eth: ethgrp { pinctrl_eth: ethgrp {
fsl,pins = < fsl,pins = <
MX1_PAD_SIM_SVEN__GPIO2_14 0x0 MX1_PAD_SIM_SVEN__GPIO2_14 0x0
@ -119,4 +118,3 @@ MX1_PAD_LBA__LBA 0x0
>; >;
}; };
}; };
};

2
arch/arm/boot/dts/nxp/imx/imx25-eukrea-cpuimx25.dtsi
View File

@ -34,7 +34,6 @@ rtc@51 {
}; };
&iomuxc { &iomuxc {
imx25-eukrea-cpuimx25 {
pinctrl_fec: fecgrp { pinctrl_fec: fecgrp {
fsl,pins = < fsl,pins = <
MX25_PAD_FEC_MDC__FEC_MDC 0x80000000 MX25_PAD_FEC_MDC__FEC_MDC 0x80000000
@ -56,7 +55,6 @@ MX25_PAD_I2C1_DAT__I2C1_DAT 0x80000000
>; >;
}; };
}; };
};
&nfc { &nfc {
nand-bus-width = <8>; nand-bus-width = <8>;

4
arch/arm/boot/dts/nxp/imx/imx25-eukrea-mbimxsd25-baseboard-cmo-qvga.dts
View File

@ -43,12 +43,10 @@ reg_lcd_3v3: regulator-0 {
}; };
&iomuxc { &iomuxc {
imx25-eukrea-mbimxsd25-baseboard-cmo-qvga { pinctrl_reg_lcd_3v3: reg_lcd_3v3grp {
pinctrl_reg_lcd_3v3: reg_lcd_3v3 {
fsl,pins = <MX25_PAD_PWM__GPIO_1_26 0x80000000>; fsl,pins = <MX25_PAD_PWM__GPIO_1_26 0x80000000>;
}; };
}; };
};
&lcdc { &lcdc {
display = <&cmo_qvga>; display = <&cmo_qvga>;

2
arch/arm/boot/dts/nxp/imx/imx25-eukrea-mbimxsd25-baseboard.dts
View File

@ -68,7 +68,6 @@ tlv320aic23: codec@1a {
}; };
&iomuxc { &iomuxc {
imx25-eukrea-mbimxsd25-baseboard {
pinctrl_audmux: audmuxgrp { pinctrl_audmux: audmuxgrp {
fsl,pins = < fsl,pins = <
MX25_PAD_KPP_COL3__AUD5_TXFS 0xe0 MX25_PAD_KPP_COL3__AUD5_TXFS 0xe0
@ -143,7 +142,6 @@ MX25_PAD_UART2_CTS__UART2_CTS 0x80000000
>; >;
}; };
}; };
};
&ssi1 { &ssi1 {
codec-handle = <&tlv320aic23>; codec-handle = <&tlv320aic23>;

2
arch/arm/boot/dts/nxp/imx/imx25-pdk.dts
View File

@ -130,7 +130,6 @@ codec: sgtl5000@a {
}; };
&iomuxc { &iomuxc {
imx25-pdk {
pinctrl_audmux: audmuxgrp { pinctrl_audmux: audmuxgrp {
fsl,pins = < fsl,pins = <
MX25_PAD_RW__AUD4_TXFS 0xe0 MX25_PAD_RW__AUD4_TXFS 0xe0
@ -234,7 +233,6 @@ MX25_PAD_UART1_RXD__UART1_RXD 0xc0
>; >;
}; };
}; };
};
&lcdc { &lcdc {
display = <&wvga>; display = <&wvga>;

2
arch/arm/boot/dts/nxp/imx/imx27-apf27.dts
View File

@ -24,7 +24,6 @@ &clk_osc26m {
}; };
&iomuxc { &iomuxc {
imx27-apf27 {
pinctrl_fec1: fec1grp { pinctrl_fec1: fec1grp {
fsl,pins = < fsl,pins = <
MX27_PAD_SD3_CMD__FEC_TXD0 0x0 MX27_PAD_SD3_CMD__FEC_TXD0 0x0
@ -55,7 +54,6 @@ MX27_PAD_UART1_RXD__UART1_RXD 0x0
>; >;
}; };
}; };
};
&uart1 { &uart1 {
pinctrl-names = "default"; pinctrl-names = "default";

4
arch/arm/boot/dts/nxp/imx/imx27-apf27dev.dts
View File

@ -122,7 +122,6 @@ &i2c2 {
}; };
&iomuxc { &iomuxc {
imx27-apf27dev {
pinctrl_cspi1: cspi1grp { pinctrl_cspi1: cspi1grp {
fsl,pins = < fsl,pins = <
MX27_PAD_CSPI1_MISO__CSPI1_MISO 0x0 MX27_PAD_CSPI1_MISO__CSPI1_MISO 0x0
@ -205,7 +204,7 @@ MX27_PAD_I2C2_SCL__I2C2_SCL 0x0
>; >;
}; };
pinctrl_max1027: max1027 { pinctrl_max1027: max1027grp {
fsl,pins = < fsl,pins = <
MX27_PAD_UART1_CTS__GPIO5_14 0x0 /* CNVST */ MX27_PAD_UART1_CTS__GPIO5_14 0x0 /* CNVST */
MX27_PAD_UART1_RTS__GPIO5_15 0x0 /* EOC */ MX27_PAD_UART1_RTS__GPIO5_15 0x0 /* EOC */
@ -233,7 +232,6 @@ pinctrl_sdhc2_cd: sdhc2cdgrp {
fsl,pins = <MX27_PAD_TOUT__GPIO3_14 0x0>; fsl,pins = <MX27_PAD_TOUT__GPIO3_14 0x0>;
}; };
}; };
};
&sdhci2 { &sdhci2 {
bus-width = <4>; bus-width = <4>;

2
arch/arm/boot/dts/nxp/imx/imx27-eukrea-cpuimx27.dtsi
View File

@ -154,7 +154,6 @@ uart8250@3,1000000 {
}; };
&iomuxc { &iomuxc {
imx27-eukrea-cpuimx27 {
pinctrl_fec: fecgrp { pinctrl_fec: fecgrp {
fsl,pins = < fsl,pins = <
MX27_PAD_SD3_CMD__FEC_TXD0 0x0 MX27_PAD_SD3_CMD__FEC_TXD0 0x0
@ -281,4 +280,3 @@ MX27_PAD_USBOTG_DATA7__USBOTG_DATA7 0x0
>; >;
}; };
}; };
};

2
arch/arm/boot/dts/nxp/imx/imx27-eukrea-mbimxsd27-baseboard.dts
View File

@ -147,7 +147,6 @@ &uart3 {
}; };
&iomuxc { &iomuxc {
imx27-eukrea-cpuimx27-baseboard {
pinctrl_cspi1: cspi1grp { pinctrl_cspi1: cspi1grp {
fsl,pins = < fsl,pins = <
MX27_PAD_CSPI1_MISO__CSPI1_MISO 0x0 MX27_PAD_CSPI1_MISO__CSPI1_MISO 0x0
@ -256,4 +255,3 @@ MX27_PAD_UART3_RTS__UART3_RTS 0x0
>; >;
}; };
}; };
};

2
arch/arm/boot/dts/nxp/imx/imx27-pdk.dts
View File

@ -110,7 +110,6 @@ &usbotg {
}; };
&iomuxc { &iomuxc {
imx27-pdk {
pinctrl_cspi2: cspi2grp { pinctrl_cspi2: cspi2grp {
fsl,pins = < fsl,pins = <
MX27_PAD_CSPI2_MISO__CSPI2_MISO 0x0 MX27_PAD_CSPI2_MISO__CSPI2_MISO 0x0
@ -182,4 +181,3 @@ MX27_PAD_USBOTG_DATA7__USBOTG_DATA7 0x0
>; >;
}; };
}; };
};

2
arch/arm/boot/dts/nxp/imx/imx27-phytec-phycard-s-rdk.dts
View File

@ -65,7 +65,6 @@ adc@64 {
}; };
&iomuxc { &iomuxc {
imx27-phycard-s-rdk {
pinctrl_i2c1: i2c1grp { pinctrl_i2c1: i2c1grp {
fsl,pins = < fsl,pins = <
MX27_PAD_I2C_DATA__I2C_DATA 0x0 MX27_PAD_I2C_DATA__I2C_DATA 0x0
@ -118,7 +117,6 @@ MX27_PAD_UART3_RTS__UART3_RTS 0x0
>; >;
}; };
}; };
};
&owire { &owire {
pinctrl-names = "default"; pinctrl-names = "default";

2
arch/arm/boot/dts/nxp/imx/imx27-phytec-phycard-s-som.dtsi
View File

@ -58,7 +58,6 @@ eeprom@52 {
}; };
&iomuxc { &iomuxc {
imx27-phycard-s-som {
pinctrl_fec1: fec1grp { pinctrl_fec1: fec1grp {
fsl,pins = < fsl,pins = <
MX27_PAD_SD3_CMD__FEC_TXD0 0x0 MX27_PAD_SD3_CMD__FEC_TXD0 0x0
@ -147,7 +146,6 @@ MX27_PAD_USBH2_DATA7__USBH2_DATA7 0x0
>; >;
}; };
}; };
};
&nfc { &nfc {
pinctrl-names = "default"; pinctrl-names = "default";

2
arch/arm/boot/dts/nxp/imx/imx27-phytec-phycore-rdk.dts
View File

@ -89,7 +89,6 @@ camgpio: pca9536@41 {
}; };
&iomuxc { &iomuxc {
imx27_phycore_rdk {
pinctrl_csien: csiengrp { pinctrl_csien: csiengrp {
fsl,pins = < fsl,pins = <
MX27_PAD_USB_OC_B__GPIO2_24 0x0 MX27_PAD_USB_OC_B__GPIO2_24 0x0
@ -203,7 +202,6 @@ MX27_PAD_SD1_D1__GPIO5_19 0x0 /* CAN IRQ */
>; >;
}; };
}; };
};
&owire { &owire {
pinctrl-names = "default"; pinctrl-names = "default";

2
arch/arm/boot/dts/nxp/imx/imx27-phytec-phycore-som.dtsi
View File

@ -192,7 +192,6 @@ lm75@4a {
}; };
&iomuxc { &iomuxc {
imx27_phycore_som {
pinctrl_cspi1: cspi1grp { pinctrl_cspi1: cspi1grp {
fsl,pins = < fsl,pins = <
MX27_PAD_CSPI1_MISO__CSPI1_MISO 0x0 MX27_PAD_CSPI1_MISO__CSPI1_MISO 0x0
@ -277,7 +276,6 @@ MX27_PAD_USBOTG_DATA7__USBOTG_DATA7 0x0
>; >;
}; };
}; };
};
&nfc { &nfc {
pinctrl-names = "default"; pinctrl-names = "default";