diff --git a/arch/arm/boot/dts/nxp/imx/imx1-ads.dts b/arch/arm/boot/dts/nxp/imx/imx1-ads.dts
index 2c817c4a4c68..823e7c42910b 100644
--- a/arch/arm/boot/dts/nxp/imx/imx1-ads.dts
+++ b/arch/arm/boot/dts/nxp/imx/imx1-ads.dts
@@ -76,60 +76,58 @@ nor: flash@0,0 {
 };
 
 &iomuxc {
-	imx1-ads {
-		pinctrl_cspi1: cspi1grp {
-			fsl,pins = <
-				MX1_PAD_SPI1_MISO__SPI1_MISO	0x0
-				MX1_PAD_SPI1_MOSI__SPI1_MOSI	0x0
-				MX1_PAD_SPI1_RDY__SPI1_RDY	0x0
-				MX1_PAD_SPI1_SCLK__SPI1_SCLK	0x0
-				MX1_PAD_SPI1_SS__GPIO3_15	0x0
-			>;
-		};
+	pinctrl_cspi1: cspi1grp {
+		fsl,pins = <
+			MX1_PAD_SPI1_MISO__SPI1_MISO	0x0
+			MX1_PAD_SPI1_MOSI__SPI1_MOSI	0x0
+			MX1_PAD_SPI1_RDY__SPI1_RDY	0x0
+			MX1_PAD_SPI1_SCLK__SPI1_SCLK	0x0
+			MX1_PAD_SPI1_SS__GPIO3_15	0x0
+		>;
+	};
 
-		pinctrl_i2c: i2cgrp {
-			fsl,pins = <
-				MX1_PAD_I2C_SCL__I2C_SCL	0x0
-				MX1_PAD_I2C_SDA__I2C_SDA	0x0
-			>;
-		};
+	pinctrl_i2c: i2cgrp {
+		fsl,pins = <
+			MX1_PAD_I2C_SCL__I2C_SCL	0x0
+			MX1_PAD_I2C_SDA__I2C_SDA	0x0
+		>;
+	};
 
-		pinctrl_uart1: uart1grp {
-			fsl,pins = <
-				MX1_PAD_UART1_TXD__UART1_TXD	0x0
-				MX1_PAD_UART1_RXD__UART1_RXD	0x0
-				MX1_PAD_UART1_CTS__UART1_CTS	0x0
-				MX1_PAD_UART1_RTS__UART1_RTS	0x0
-			>;
-		};
+	pinctrl_uart1: uart1grp {
+		fsl,pins = <
+			MX1_PAD_UART1_TXD__UART1_TXD	0x0
+			MX1_PAD_UART1_RXD__UART1_RXD	0x0
+			MX1_PAD_UART1_CTS__UART1_CTS	0x0
+			MX1_PAD_UART1_RTS__UART1_RTS	0x0
+		>;
+	};
 
-		pinctrl_uart2: uart2grp {
-			fsl,pins = <
-				MX1_PAD_UART2_TXD__UART2_TXD	0x0
-				MX1_PAD_UART2_RXD__UART2_RXD	0x0
-				MX1_PAD_UART2_CTS__UART2_CTS	0x0
-				MX1_PAD_UART2_RTS__UART2_RTS	0x0
-			>;
-		};
+	pinctrl_uart2: uart2grp {
+		fsl,pins = <
+			MX1_PAD_UART2_TXD__UART2_TXD	0x0
+			MX1_PAD_UART2_RXD__UART2_RXD	0x0
+			MX1_PAD_UART2_CTS__UART2_CTS	0x0
+			MX1_PAD_UART2_RTS__UART2_RTS	0x0
+		>;
+	};
 
-		pinctrl_weim: weimgrp {
-			fsl,pins = <
-				MX1_PAD_A0__A0			0x0
-				MX1_PAD_A16__A16		0x0
-				MX1_PAD_A17__A17		0x0
-				MX1_PAD_A18__A18		0x0
-				MX1_PAD_A19__A19		0x0
-				MX1_PAD_A20__A20		0x0
-				MX1_PAD_A21__A21		0x0
-				MX1_PAD_A22__A22		0x0
-				MX1_PAD_A23__A23		0x0
-				MX1_PAD_A24__A24		0x0
-				MX1_PAD_BCLK__BCLK		0x0
-				MX1_PAD_CS4__CS4		0x0
-				MX1_PAD_DTACK__DTACK		0x0
-				MX1_PAD_ECB__ECB		0x0
-				MX1_PAD_LBA__LBA		0x0
-			>;
-		};
+	pinctrl_weim: weimgrp {
+		fsl,pins = <
+			MX1_PAD_A0__A0			0x0
+			MX1_PAD_A16__A16		0x0
+			MX1_PAD_A17__A17		0x0
+			MX1_PAD_A18__A18		0x0
+			MX1_PAD_A19__A19		0x0
+			MX1_PAD_A20__A20		0x0
+			MX1_PAD_A21__A21		0x0
+			MX1_PAD_A22__A22		0x0
+			MX1_PAD_A23__A23		0x0
+			MX1_PAD_A24__A24		0x0
+			MX1_PAD_BCLK__BCLK		0x0
+			MX1_PAD_CS4__CS4		0x0
+			MX1_PAD_DTACK__DTACK		0x0
+			MX1_PAD_ECB__ECB		0x0
+			MX1_PAD_LBA__LBA		0x0
+		>;
 	};
 };
diff --git a/arch/arm/boot/dts/nxp/imx/imx1-apf9328.dts b/arch/arm/boot/dts/nxp/imx/imx1-apf9328.dts
index 058e9435524f..794e5bfee367 100644
--- a/arch/arm/boot/dts/nxp/imx/imx1-apf9328.dts
+++ b/arch/arm/boot/dts/nxp/imx/imx1-apf9328.dts
@@ -67,56 +67,54 @@ eth: ethernet@4,c00000 {
 };
 
 &iomuxc {
-	imx1-apf9328 {
-		pinctrl_eth: ethgrp {
-			fsl,pins = <
-				MX1_PAD_SIM_SVEN__GPIO2_14	0x0
-			>;
-		};
+	pinctrl_eth: ethgrp {
+		fsl,pins = <
+			MX1_PAD_SIM_SVEN__GPIO2_14	0x0
+		>;
+	};
 
-		pinctrl_i2c: i2cgrp {
-			fsl,pins = <
-				MX1_PAD_I2C_SCL__I2C_SCL	0x0
-				MX1_PAD_I2C_SDA__I2C_SDA	0x0
-			>;
-		};
+	pinctrl_i2c: i2cgrp {
+		fsl,pins = <
+			MX1_PAD_I2C_SCL__I2C_SCL	0x0
+			MX1_PAD_I2C_SDA__I2C_SDA	0x0
+		>;
+	};
 
-		pinctrl_uart1: uart1grp {
-			fsl,pins = <
-				MX1_PAD_UART1_TXD__UART1_TXD	0x0
-				MX1_PAD_UART1_RXD__UART1_RXD	0x0
-				MX1_PAD_UART1_CTS__UART1_CTS	0x0
-				MX1_PAD_UART1_RTS__UART1_RTS	0x0
-			>;
-		};
+	pinctrl_uart1: uart1grp {
+		fsl,pins = <
+			MX1_PAD_UART1_TXD__UART1_TXD	0x0
+			MX1_PAD_UART1_RXD__UART1_RXD	0x0
+			MX1_PAD_UART1_CTS__UART1_CTS	0x0
+			MX1_PAD_UART1_RTS__UART1_RTS	0x0
+		>;
+	};
 
-		pinctrl_uart2: uart2grp {
-			fsl,pins = <
-				MX1_PAD_UART2_TXD__UART2_TXD	0x0
-				MX1_PAD_UART2_RXD__UART2_RXD	0x0
-				MX1_PAD_UART2_CTS__UART2_CTS	0x0
-				MX1_PAD_UART2_RTS__UART2_RTS	0x0
-			>;
-		};
+	pinctrl_uart2: uart2grp {
+		fsl,pins = <
+			MX1_PAD_UART2_TXD__UART2_TXD	0x0
+			MX1_PAD_UART2_RXD__UART2_RXD	0x0
+			MX1_PAD_UART2_CTS__UART2_CTS	0x0
+			MX1_PAD_UART2_RTS__UART2_RTS	0x0
+		>;
+	};
 
-		pinctrl_weim: weimgrp {
-			fsl,pins = <
-				MX1_PAD_A0__A0			0x0
-				MX1_PAD_A16__A16		0x0
-				MX1_PAD_A17__A17		0x0
-				MX1_PAD_A18__A18		0x0
-				MX1_PAD_A19__A19		0x0
-				MX1_PAD_A20__A20		0x0
-				MX1_PAD_A21__A21		0x0
-				MX1_PAD_A22__A22		0x0
-				MX1_PAD_A23__A23		0x0
-				MX1_PAD_A24__A24		0x0
-				MX1_PAD_BCLK__BCLK		0x0
-				MX1_PAD_CS4__CS4		0x0
-				MX1_PAD_DTACK__DTACK		0x0
-				MX1_PAD_ECB__ECB		0x0
-				MX1_PAD_LBA__LBA		0x0
-			>;
-		};
+	pinctrl_weim: weimgrp {
+		fsl,pins = <
+			MX1_PAD_A0__A0			0x0
+			MX1_PAD_A16__A16		0x0
+			MX1_PAD_A17__A17		0x0
+			MX1_PAD_A18__A18		0x0
+			MX1_PAD_A19__A19		0x0
+			MX1_PAD_A20__A20		0x0
+			MX1_PAD_A21__A21		0x0
+			MX1_PAD_A22__A22		0x0
+			MX1_PAD_A23__A23		0x0
+			MX1_PAD_A24__A24		0x0
+			MX1_PAD_BCLK__BCLK		0x0
+			MX1_PAD_CS4__CS4		0x0
+			MX1_PAD_DTACK__DTACK		0x0
+			MX1_PAD_ECB__ECB		0x0
+			MX1_PAD_LBA__LBA		0x0
+		>;
 	};
 };
diff --git a/arch/arm/boot/dts/nxp/imx/imx25-eukrea-cpuimx25.dtsi b/arch/arm/boot/dts/nxp/imx/imx25-eukrea-cpuimx25.dtsi
index 93a6e4e680b4..31dc2a640362 100644
--- a/arch/arm/boot/dts/nxp/imx/imx25-eukrea-cpuimx25.dtsi
+++ b/arch/arm/boot/dts/nxp/imx/imx25-eukrea-cpuimx25.dtsi
@@ -34,27 +34,25 @@ rtc@51 {
 };
 
 &iomuxc {
-	imx25-eukrea-cpuimx25 {
-		pinctrl_fec: fecgrp {
-			fsl,pins = <
-				MX25_PAD_FEC_MDC__FEC_MDC		0x80000000
-				MX25_PAD_FEC_MDIO__FEC_MDIO		0x400001e0
-				MX25_PAD_FEC_TDATA0__FEC_TDATA0		0x80000000
-				MX25_PAD_FEC_TDATA1__FEC_TDATA1		0x80000000
-				MX25_PAD_FEC_TX_EN__FEC_TX_EN		0x80000000
-				MX25_PAD_FEC_RDATA0__FEC_RDATA0		0x80000000
-				MX25_PAD_FEC_RDATA1__FEC_RDATA1		0x80000000
-				MX25_PAD_FEC_RX_DV__FEC_RX_DV		0x80000000
-				MX25_PAD_FEC_TX_CLK__FEC_TX_CLK		0x1c0
-			>;
-		};
+	pinctrl_fec: fecgrp {
+		fsl,pins = <
+			MX25_PAD_FEC_MDC__FEC_MDC		0x80000000
+			MX25_PAD_FEC_MDIO__FEC_MDIO		0x400001e0
+			MX25_PAD_FEC_TDATA0__FEC_TDATA0		0x80000000
+			MX25_PAD_FEC_TDATA1__FEC_TDATA1		0x80000000
+			MX25_PAD_FEC_TX_EN__FEC_TX_EN		0x80000000
+			MX25_PAD_FEC_RDATA0__FEC_RDATA0		0x80000000
+			MX25_PAD_FEC_RDATA1__FEC_RDATA1		0x80000000
+			MX25_PAD_FEC_RX_DV__FEC_RX_DV		0x80000000
+			MX25_PAD_FEC_TX_CLK__FEC_TX_CLK		0x1c0
+		>;
+	};
 
-		pinctrl_i2c1: i2c1grp {
-			fsl,pins = <
-				MX25_PAD_I2C1_CLK__I2C1_CLK		0x80000000
-				MX25_PAD_I2C1_DAT__I2C1_DAT		0x80000000
-			>;
-		};
+	pinctrl_i2c1: i2c1grp {
+		fsl,pins = <
+			MX25_PAD_I2C1_CLK__I2C1_CLK		0x80000000
+			MX25_PAD_I2C1_DAT__I2C1_DAT		0x80000000
+		>;
 	};
 };
 
diff --git a/arch/arm/boot/dts/nxp/imx/imx25-eukrea-mbimxsd25-baseboard-cmo-qvga.dts b/arch/arm/boot/dts/nxp/imx/imx25-eukrea-mbimxsd25-baseboard-cmo-qvga.dts
index 6cddb2cc36fe..e08fcbfef4d5 100644
--- a/arch/arm/boot/dts/nxp/imx/imx25-eukrea-mbimxsd25-baseboard-cmo-qvga.dts
+++ b/arch/arm/boot/dts/nxp/imx/imx25-eukrea-mbimxsd25-baseboard-cmo-qvga.dts
@@ -43,10 +43,8 @@ reg_lcd_3v3: regulator-0 {
 };
 
 &iomuxc {
-	imx25-eukrea-mbimxsd25-baseboard-cmo-qvga {
-		pinctrl_reg_lcd_3v3: reg_lcd_3v3 {
-			fsl,pins = <MX25_PAD_PWM__GPIO_1_26 0x80000000>;
-		};
+	pinctrl_reg_lcd_3v3: reg_lcd_3v3grp {
+		fsl,pins = <MX25_PAD_PWM__GPIO_1_26 0x80000000>;
 	};
 };
 
diff --git a/arch/arm/boot/dts/nxp/imx/imx25-eukrea-mbimxsd25-baseboard.dts b/arch/arm/boot/dts/nxp/imx/imx25-eukrea-mbimxsd25-baseboard.dts
index c7207ea437c4..cf127e00793e 100644
--- a/arch/arm/boot/dts/nxp/imx/imx25-eukrea-mbimxsd25-baseboard.dts
+++ b/arch/arm/boot/dts/nxp/imx/imx25-eukrea-mbimxsd25-baseboard.dts
@@ -68,80 +68,78 @@ tlv320aic23: codec@1a {
 };
 
 &iomuxc {
-	imx25-eukrea-mbimxsd25-baseboard {
-		pinctrl_audmux: audmuxgrp {
-			fsl,pins = <
-				MX25_PAD_KPP_COL3__AUD5_TXFS		0xe0
-				MX25_PAD_KPP_COL2__AUD5_TXC		0xe0
-				MX25_PAD_KPP_COL1__AUD5_RXD		0xe0
-				MX25_PAD_KPP_COL0__AUD5_TXD		0xe0
-			>;
-		};
+	pinctrl_audmux: audmuxgrp {
+		fsl,pins = <
+			MX25_PAD_KPP_COL3__AUD5_TXFS		0xe0
+			MX25_PAD_KPP_COL2__AUD5_TXC		0xe0
+			MX25_PAD_KPP_COL1__AUD5_RXD		0xe0
+			MX25_PAD_KPP_COL0__AUD5_TXD		0xe0
+		>;
+	};
 
-		pinctrl_esdhc1: esdhc1grp {
-			fsl,pins = <
-				MX25_PAD_SD1_CMD__ESDHC1_CMD		0x400000c0
-				MX25_PAD_SD1_CLK__ESDHC1_CLK		0x400000c0
-				MX25_PAD_SD1_DATA0__ESDHC1_DAT0		0x400000c0
-				MX25_PAD_SD1_DATA1__ESDHC1_DAT1		0x400000c0
-				MX25_PAD_SD1_DATA2__ESDHC1_DAT2		0x400000c0
-				MX25_PAD_SD1_DATA3__ESDHC1_DAT3		0x400000c0
-			>;
-		};
+	pinctrl_esdhc1: esdhc1grp {
+		fsl,pins = <
+			MX25_PAD_SD1_CMD__ESDHC1_CMD		0x400000c0
+			MX25_PAD_SD1_CLK__ESDHC1_CLK		0x400000c0
+			MX25_PAD_SD1_DATA0__ESDHC1_DAT0		0x400000c0
+			MX25_PAD_SD1_DATA1__ESDHC1_DAT1		0x400000c0
+			MX25_PAD_SD1_DATA2__ESDHC1_DAT2		0x400000c0
+			MX25_PAD_SD1_DATA3__ESDHC1_DAT3		0x400000c0
+		>;
+	};
 
-		pinctrl_gpiokeys: gpiokeysgrp {
-			fsl,pins = <MX25_PAD_VSTBY_ACK__GPIO_3_18 0x80000000>;
-		};
+	pinctrl_gpiokeys: gpiokeysgrp {
+		fsl,pins = <MX25_PAD_VSTBY_ACK__GPIO_3_18 0x80000000>;
+	};
 
-		pinctrl_gpioled: gpioledgrp {
-			fsl,pins = <MX25_PAD_POWER_FAIL__GPIO_3_19 0x80000000>;
-		};
+	pinctrl_gpioled: gpioledgrp {
+		fsl,pins = <MX25_PAD_POWER_FAIL__GPIO_3_19 0x80000000>;
+	};
 
-		pinctrl_lcdc: lcdcgrp {
-			fsl,pins = <
-				MX25_PAD_LD0__LD0			0x1
-				MX25_PAD_LD1__LD1			0x1
-				MX25_PAD_LD2__LD2			0x1
-				MX25_PAD_LD3__LD3			0x1
-				MX25_PAD_LD4__LD4			0x1
-				MX25_PAD_LD5__LD5			0x1
-				MX25_PAD_LD6__LD6			0x1
-				MX25_PAD_LD7__LD7			0x1
-				MX25_PAD_LD8__LD8			0x1
-				MX25_PAD_LD9__LD9			0x1
-				MX25_PAD_LD10__LD10			0x1
-				MX25_PAD_LD11__LD11			0x1
-				MX25_PAD_LD12__LD12			0x1
-				MX25_PAD_LD13__LD13			0x1
-				MX25_PAD_LD14__LD14			0x1
-				MX25_PAD_LD15__LD15			0x1
-				MX25_PAD_GPIO_E__LD16			0x1
-				MX25_PAD_GPIO_F__LD17			0x1
-				MX25_PAD_HSYNC__HSYNC			0x80000000
-				MX25_PAD_VSYNC__VSYNC			0x80000000
-				MX25_PAD_LSCLK__LSCLK			0x80000000
-				MX25_PAD_OE_ACD__OE_ACD			0x80000000
-				MX25_PAD_CONTRAST__CONTRAST		0x80000000
-			>;
-		};
+	pinctrl_lcdc: lcdcgrp {
+		fsl,pins = <
+			MX25_PAD_LD0__LD0			0x1
+			MX25_PAD_LD1__LD1			0x1
+			MX25_PAD_LD2__LD2			0x1
+			MX25_PAD_LD3__LD3			0x1
+			MX25_PAD_LD4__LD4			0x1
+			MX25_PAD_LD5__LD5			0x1
+			MX25_PAD_LD6__LD6			0x1
+			MX25_PAD_LD7__LD7			0x1
+			MX25_PAD_LD8__LD8			0x1
+			MX25_PAD_LD9__LD9			0x1
+			MX25_PAD_LD10__LD10			0x1
+			MX25_PAD_LD11__LD11			0x1
+			MX25_PAD_LD12__LD12			0x1
+			MX25_PAD_LD13__LD13			0x1
+			MX25_PAD_LD14__LD14			0x1
+			MX25_PAD_LD15__LD15			0x1
+			MX25_PAD_GPIO_E__LD16			0x1
+			MX25_PAD_GPIO_F__LD17			0x1
+			MX25_PAD_HSYNC__HSYNC			0x80000000
+			MX25_PAD_VSYNC__VSYNC			0x80000000
+			MX25_PAD_LSCLK__LSCLK			0x80000000
+			MX25_PAD_OE_ACD__OE_ACD			0x80000000
+			MX25_PAD_CONTRAST__CONTRAST		0x80000000
+		>;
+	};
 
-		pinctrl_uart1: uart1grp {
-			fsl,pins = <
-				MX25_PAD_UART1_RTS__UART1_RTS		0xe0
-				MX25_PAD_UART1_CTS__UART1_CTS		0xe0
-				MX25_PAD_UART1_TXD__UART1_TXD		0x80000000
-				MX25_PAD_UART1_RXD__UART1_RXD		0xc0
-			>;
-		};
+	pinctrl_uart1: uart1grp {
+		fsl,pins = <
+			MX25_PAD_UART1_RTS__UART1_RTS		0xe0
+			MX25_PAD_UART1_CTS__UART1_CTS		0xe0
+			MX25_PAD_UART1_TXD__UART1_TXD		0x80000000
+			MX25_PAD_UART1_RXD__UART1_RXD		0xc0
+		>;
+	};
 
-		pinctrl_uart2: uart2grp {
-			fsl,pins = <
-				MX25_PAD_UART2_RXD__UART2_RXD		0x80000000
-				MX25_PAD_UART2_TXD__UART2_TXD		0x80000000
-				MX25_PAD_UART2_RTS__UART2_RTS		0x80000000
-				MX25_PAD_UART2_CTS__UART2_CTS		0x80000000
-			>;
-		};
+	pinctrl_uart2: uart2grp {
+		fsl,pins = <
+			MX25_PAD_UART2_RXD__UART2_RXD		0x80000000
+			MX25_PAD_UART2_TXD__UART2_TXD		0x80000000
+			MX25_PAD_UART2_RTS__UART2_RTS		0x80000000
+			MX25_PAD_UART2_CTS__UART2_CTS		0x80000000
+		>;
 	};
 };
 
diff --git a/arch/arm/boot/dts/nxp/imx/imx25-pdk.dts b/arch/arm/boot/dts/nxp/imx/imx25-pdk.dts
index dd176fb54e58..a35778ba6ffa 100644
--- a/arch/arm/boot/dts/nxp/imx/imx25-pdk.dts
+++ b/arch/arm/boot/dts/nxp/imx/imx25-pdk.dts
@@ -130,109 +130,107 @@ codec: sgtl5000@a {
 };
 
 &iomuxc {
-	imx25-pdk {
-		pinctrl_audmux: audmuxgrp {
-			fsl,pins = <
-				MX25_PAD_RW__AUD4_TXFS			0xe0
-				MX25_PAD_OE__AUD4_TXC			0xe0
-				MX25_PAD_EB0__AUD4_TXD			0xe0
-				MX25_PAD_EB1__AUD4_RXD			0xe0
-			>;
-		};
+	pinctrl_audmux: audmuxgrp {
+		fsl,pins = <
+			MX25_PAD_RW__AUD4_TXFS			0xe0
+			MX25_PAD_OE__AUD4_TXC			0xe0
+			MX25_PAD_EB0__AUD4_TXD			0xe0
+			MX25_PAD_EB1__AUD4_RXD			0xe0
+		>;
+	};
 
-		pinctrl_can1: can1grp {
-			fsl,pins = <
-				MX25_PAD_GPIO_A__CAN1_TX		0x0
-				MX25_PAD_GPIO_B__CAN1_RX		0x0
-				MX25_PAD_D14__GPIO_4_6 			0x80000000
-			>;
-		};
+	pinctrl_can1: can1grp {
+		fsl,pins = <
+			MX25_PAD_GPIO_A__CAN1_TX		0x0
+			MX25_PAD_GPIO_B__CAN1_RX		0x0
+			MX25_PAD_D14__GPIO_4_6			0x80000000
+		>;
+	};
 
-		pinctrl_esdhc1: esdhc1grp {
-			fsl,pins = <
-				MX25_PAD_SD1_CMD__ESDHC1_CMD		0x80000000
-				MX25_PAD_SD1_CLK__ESDHC1_CLK		0x80000000
-				MX25_PAD_SD1_DATA0__ESDHC1_DAT0		0x80000000
-				MX25_PAD_SD1_DATA1__ESDHC1_DAT1		0x80000000
-				MX25_PAD_SD1_DATA2__ESDHC1_DAT2		0x80000000
-				MX25_PAD_SD1_DATA3__ESDHC1_DAT3		0x80000000
-				MX25_PAD_A14__GPIO_2_0			0x80000000
-				MX25_PAD_A15__GPIO_2_1			0x80000000
-			>;
-		};
+	pinctrl_esdhc1: esdhc1grp {
+		fsl,pins = <
+			MX25_PAD_SD1_CMD__ESDHC1_CMD		0x80000000
+			MX25_PAD_SD1_CLK__ESDHC1_CLK		0x80000000
+			MX25_PAD_SD1_DATA0__ESDHC1_DAT0		0x80000000
+			MX25_PAD_SD1_DATA1__ESDHC1_DAT1		0x80000000
+			MX25_PAD_SD1_DATA2__ESDHC1_DAT2		0x80000000
+			MX25_PAD_SD1_DATA3__ESDHC1_DAT3		0x80000000
+			MX25_PAD_A14__GPIO_2_0			0x80000000
+			MX25_PAD_A15__GPIO_2_1			0x80000000
+		>;
+	};
 
-		pinctrl_fec: fecgrp {
-			fsl,pins = <
-				MX25_PAD_FEC_MDC__FEC_MDC		0x80000000
-				MX25_PAD_FEC_MDIO__FEC_MDIO		0x400001e0
-				MX25_PAD_FEC_TDATA0__FEC_TDATA0		0x80000000
-				MX25_PAD_FEC_TDATA1__FEC_TDATA1		0x80000000
-				MX25_PAD_FEC_TX_EN__FEC_TX_EN		0x80000000
-				MX25_PAD_FEC_RDATA0__FEC_RDATA0		0x80000000
-				MX25_PAD_FEC_RDATA1__FEC_RDATA1		0x80000000
-				MX25_PAD_FEC_RX_DV__FEC_RX_DV		0x80000000
-				MX25_PAD_FEC_TX_CLK__FEC_TX_CLK		0x1c0
-				MX25_PAD_A17__GPIO_2_3			0x80000000
-				MX25_PAD_D12__GPIO_4_8			0x80000000
-			>;
-		};
+	pinctrl_fec: fecgrp {
+		fsl,pins = <
+			MX25_PAD_FEC_MDC__FEC_MDC		0x80000000
+			MX25_PAD_FEC_MDIO__FEC_MDIO		0x400001e0
+			MX25_PAD_FEC_TDATA0__FEC_TDATA0		0x80000000
+			MX25_PAD_FEC_TDATA1__FEC_TDATA1		0x80000000
+			MX25_PAD_FEC_TX_EN__FEC_TX_EN		0x80000000
+			MX25_PAD_FEC_RDATA0__FEC_RDATA0		0x80000000
+			MX25_PAD_FEC_RDATA1__FEC_RDATA1		0x80000000
+			MX25_PAD_FEC_RX_DV__FEC_RX_DV		0x80000000
+			MX25_PAD_FEC_TX_CLK__FEC_TX_CLK		0x1c0
+			MX25_PAD_A17__GPIO_2_3			0x80000000
+			MX25_PAD_D12__GPIO_4_8			0x80000000
+		>;
+	};
 
-		pinctrl_i2c1: i2c1grp {
-			fsl,pins = <
-				MX25_PAD_I2C1_CLK__I2C1_CLK		0x80000000
-				MX25_PAD_I2C1_DAT__I2C1_DAT		0x80000000
-			>;
-		};
+	pinctrl_i2c1: i2c1grp {
+		fsl,pins = <
+			MX25_PAD_I2C1_CLK__I2C1_CLK		0x80000000
+			MX25_PAD_I2C1_DAT__I2C1_DAT		0x80000000
+		>;
+	};
 
-		pinctrl_kpp: kppgrp {
-			fsl,pins = <
-				MX25_PAD_KPP_ROW0__KPP_ROW0	0x80000000
-				MX25_PAD_KPP_ROW1__KPP_ROW1	0x80000000
-				MX25_PAD_KPP_ROW2__KPP_ROW2	0x80000000
-				MX25_PAD_KPP_ROW3__KPP_ROW3	0x80000000
-				MX25_PAD_KPP_COL0__KPP_COL0	0x80000000
-				MX25_PAD_KPP_COL1__KPP_COL1	0x80000000
-				MX25_PAD_KPP_COL2__KPP_COL2	0x80000000
-				MX25_PAD_KPP_COL3__KPP_COL3	0x80000000
-			>;
-		};
+	pinctrl_kpp: kppgrp {
+		fsl,pins = <
+			MX25_PAD_KPP_ROW0__KPP_ROW0	0x80000000
+			MX25_PAD_KPP_ROW1__KPP_ROW1	0x80000000
+			MX25_PAD_KPP_ROW2__KPP_ROW2	0x80000000
+			MX25_PAD_KPP_ROW3__KPP_ROW3	0x80000000
+			MX25_PAD_KPP_COL0__KPP_COL0	0x80000000
+			MX25_PAD_KPP_COL1__KPP_COL1	0x80000000
+			MX25_PAD_KPP_COL2__KPP_COL2	0x80000000
+			MX25_PAD_KPP_COL3__KPP_COL3	0x80000000
+		>;
+	};
 
-		pinctrl_lcd: lcdgrp {
-			fsl,pins = <
-				MX25_PAD_LD0__LD0		0xe0
-				MX25_PAD_LD1__LD1		0xe0
-				MX25_PAD_LD2__LD2		0xe0
-				MX25_PAD_LD3__LD3		0xe0
-				MX25_PAD_LD4__LD4		0xe0
-				MX25_PAD_LD5__LD5		0xe0
-				MX25_PAD_LD6__LD6		0xe0
-				MX25_PAD_LD7__LD7		0xe0
-				MX25_PAD_LD8__LD8		0xe0
-				MX25_PAD_LD9__LD9		0xe0
-				MX25_PAD_LD10__LD10		0xe0
-				MX25_PAD_LD11__LD11		0xe0
-				MX25_PAD_LD12__LD12		0xe0
-				MX25_PAD_LD13__LD13		0xe0
-				MX25_PAD_LD14__LD14		0xe0
-				MX25_PAD_LD15__LD15		0xe0
-				MX25_PAD_GPIO_E__LD16		0xe0
-				MX25_PAD_GPIO_F__LD17		0xe0
-				MX25_PAD_HSYNC__HSYNC		0xe0
-				MX25_PAD_VSYNC__VSYNC		0xe0
-				MX25_PAD_LSCLK__LSCLK		0xe0
-				MX25_PAD_OE_ACD__OE_ACD		0xe0
-				MX25_PAD_CONTRAST__CONTRAST	0xe0
-			>;
-		};
+	pinctrl_lcd: lcdgrp {
+		fsl,pins = <
+			MX25_PAD_LD0__LD0		0xe0
+			MX25_PAD_LD1__LD1		0xe0
+			MX25_PAD_LD2__LD2		0xe0
+			MX25_PAD_LD3__LD3		0xe0
+			MX25_PAD_LD4__LD4		0xe0
+			MX25_PAD_LD5__LD5		0xe0
+			MX25_PAD_LD6__LD6		0xe0
+			MX25_PAD_LD7__LD7		0xe0
+			MX25_PAD_LD8__LD8		0xe0
+			MX25_PAD_LD9__LD9		0xe0
+			MX25_PAD_LD10__LD10		0xe0
+			MX25_PAD_LD11__LD11		0xe0
+			MX25_PAD_LD12__LD12		0xe0
+			MX25_PAD_LD13__LD13		0xe0
+			MX25_PAD_LD14__LD14		0xe0
+			MX25_PAD_LD15__LD15		0xe0
+			MX25_PAD_GPIO_E__LD16		0xe0
+			MX25_PAD_GPIO_F__LD17		0xe0
+			MX25_PAD_HSYNC__HSYNC		0xe0
+			MX25_PAD_VSYNC__VSYNC		0xe0
+			MX25_PAD_LSCLK__LSCLK		0xe0
+			MX25_PAD_OE_ACD__OE_ACD		0xe0
+			MX25_PAD_CONTRAST__CONTRAST	0xe0
+		>;
+	};
 
-		pinctrl_uart1: uart1grp {
-			fsl,pins = <
-				MX25_PAD_UART1_RTS__UART1_RTS		0xe0
-				MX25_PAD_UART1_CTS__UART1_CTS		0xe0
-				MX25_PAD_UART1_TXD__UART1_TXD		0x80000000
-				MX25_PAD_UART1_RXD__UART1_RXD		0xc0
-			>;
-		};
+	pinctrl_uart1: uart1grp {
+		fsl,pins = <
+			MX25_PAD_UART1_RTS__UART1_RTS		0xe0
+			MX25_PAD_UART1_CTS__UART1_CTS		0xe0
+			MX25_PAD_UART1_TXD__UART1_TXD		0x80000000
+			MX25_PAD_UART1_RXD__UART1_RXD		0xc0
+		>;
 	};
 };
 
diff --git a/arch/arm/boot/dts/nxp/imx/imx27-apf27.dts b/arch/arm/boot/dts/nxp/imx/imx27-apf27.dts
index 745d5d409952..b67bb21af3de 100644
--- a/arch/arm/boot/dts/nxp/imx/imx27-apf27.dts
+++ b/arch/arm/boot/dts/nxp/imx/imx27-apf27.dts
@@ -24,36 +24,34 @@ &clk_osc26m {
 };
 
 &iomuxc {
-	imx27-apf27 {
-		pinctrl_fec1: fec1grp {
-			fsl,pins = <
-				MX27_PAD_SD3_CMD__FEC_TXD0 0x0
-				MX27_PAD_SD3_CLK__FEC_TXD1 0x0
-				MX27_PAD_ATA_DATA0__FEC_TXD2 0x0
-				MX27_PAD_ATA_DATA1__FEC_TXD3 0x0
-				MX27_PAD_ATA_DATA2__FEC_RX_ER 0x0
-				MX27_PAD_ATA_DATA3__FEC_RXD1 0x0
-				MX27_PAD_ATA_DATA4__FEC_RXD2 0x0
-				MX27_PAD_ATA_DATA5__FEC_RXD3 0x0
-				MX27_PAD_ATA_DATA6__FEC_MDIO 0x0
-				MX27_PAD_ATA_DATA7__FEC_MDC 0x0
-				MX27_PAD_ATA_DATA8__FEC_CRS 0x0
-				MX27_PAD_ATA_DATA9__FEC_TX_CLK 0x0
-				MX27_PAD_ATA_DATA10__FEC_RXD0 0x0
-				MX27_PAD_ATA_DATA11__FEC_RX_DV 0x0
-				MX27_PAD_ATA_DATA12__FEC_RX_CLK 0x0
-				MX27_PAD_ATA_DATA13__FEC_COL 0x0
-				MX27_PAD_ATA_DATA14__FEC_TX_ER 0x0
-				MX27_PAD_ATA_DATA15__FEC_TX_EN 0x0
-			>;
-		};
+	pinctrl_fec1: fec1grp {
+		fsl,pins = <
+			MX27_PAD_SD3_CMD__FEC_TXD0 0x0
+			MX27_PAD_SD3_CLK__FEC_TXD1 0x0
+			MX27_PAD_ATA_DATA0__FEC_TXD2 0x0
+			MX27_PAD_ATA_DATA1__FEC_TXD3 0x0
+			MX27_PAD_ATA_DATA2__FEC_RX_ER 0x0
+			MX27_PAD_ATA_DATA3__FEC_RXD1 0x0
+			MX27_PAD_ATA_DATA4__FEC_RXD2 0x0
+			MX27_PAD_ATA_DATA5__FEC_RXD3 0x0
+			MX27_PAD_ATA_DATA6__FEC_MDIO 0x0
+			MX27_PAD_ATA_DATA7__FEC_MDC 0x0
+			MX27_PAD_ATA_DATA8__FEC_CRS 0x0
+			MX27_PAD_ATA_DATA9__FEC_TX_CLK 0x0
+			MX27_PAD_ATA_DATA10__FEC_RXD0 0x0
+			MX27_PAD_ATA_DATA11__FEC_RX_DV 0x0
+			MX27_PAD_ATA_DATA12__FEC_RX_CLK 0x0
+			MX27_PAD_ATA_DATA13__FEC_COL 0x0
+			MX27_PAD_ATA_DATA14__FEC_TX_ER 0x0
+			MX27_PAD_ATA_DATA15__FEC_TX_EN 0x0
+		>;
+	};
 
-		pinctrl_uart1: uart1grp {
-			fsl,pins = <
-				MX27_PAD_UART1_TXD__UART1_TXD 0x0
-				MX27_PAD_UART1_RXD__UART1_RXD 0x0
-			>;
-		};
+	pinctrl_uart1: uart1grp {
+		fsl,pins = <
+			MX27_PAD_UART1_TXD__UART1_TXD 0x0
+			MX27_PAD_UART1_RXD__UART1_RXD 0x0
+		>;
 	};
 };
 
diff --git a/arch/arm/boot/dts/nxp/imx/imx27-apf27dev.dts b/arch/arm/boot/dts/nxp/imx/imx27-apf27dev.dts
index 849306cb4532..dba97912cfd7 100644
--- a/arch/arm/boot/dts/nxp/imx/imx27-apf27dev.dts
+++ b/arch/arm/boot/dts/nxp/imx/imx27-apf27dev.dts
@@ -122,116 +122,114 @@ &i2c2 {
 };
 
 &iomuxc {
-	imx27-apf27dev {
-		pinctrl_cspi1: cspi1grp {
-			fsl,pins = <
-				MX27_PAD_CSPI1_MISO__CSPI1_MISO 0x0
-				MX27_PAD_CSPI1_MOSI__CSPI1_MOSI 0x0
-				MX27_PAD_CSPI1_SCLK__CSPI1_SCLK 0x0
-			>;
-		};
+	pinctrl_cspi1: cspi1grp {
+		fsl,pins = <
+			MX27_PAD_CSPI1_MISO__CSPI1_MISO 0x0
+			MX27_PAD_CSPI1_MOSI__CSPI1_MOSI 0x0
+			MX27_PAD_CSPI1_SCLK__CSPI1_SCLK 0x0
+		>;
+	};
 
-		pinctrl_cspi1_cs: cspi1csgrp {
-			fsl,pins = <MX27_PAD_CSPI1_SS0__GPIO4_28 0x0>;
-		};
+	pinctrl_cspi1_cs: cspi1csgrp {
+		fsl,pins = <MX27_PAD_CSPI1_SS0__GPIO4_28 0x0>;
+	};
 
-		pinctrl_cspi2: cspi2grp {
-			fsl,pins = <
-				MX27_PAD_CSPI2_MISO__CSPI2_MISO 0x0
-				MX27_PAD_CSPI2_MOSI__CSPI2_MOSI 0x0
-				MX27_PAD_CSPI2_SCLK__CSPI2_SCLK 0x0
-			>;
-		};
+	pinctrl_cspi2: cspi2grp {
+		fsl,pins = <
+			MX27_PAD_CSPI2_MISO__CSPI2_MISO 0x0
+			MX27_PAD_CSPI2_MOSI__CSPI2_MOSI 0x0
+			MX27_PAD_CSPI2_SCLK__CSPI2_SCLK 0x0
+		>;
+	};
 
-		pinctrl_cspi2_cs: cspi2csgrp {
-			fsl,pins = <
-				MX27_PAD_CSI_D5__GPIO2_17 0x0
-				MX27_PAD_CSPI2_SS0__GPIO4_21 0x0
-				MX27_PAD_CSPI1_SS1__GPIO4_27 0x0
-			>;
-		};
+	pinctrl_cspi2_cs: cspi2csgrp {
+		fsl,pins = <
+			MX27_PAD_CSI_D5__GPIO2_17 0x0
+			MX27_PAD_CSPI2_SS0__GPIO4_21 0x0
+			MX27_PAD_CSPI1_SS1__GPIO4_27 0x0
+		>;
+	};
 
-		pinctrl_gpio_leds: gpioledsgrp {
-			fsl,pins = <MX27_PAD_PC_VS1__GPIO6_14 0x0>;
-		};
+	pinctrl_gpio_leds: gpioledsgrp {
+		fsl,pins = <MX27_PAD_PC_VS1__GPIO6_14 0x0>;
+	};
 
-		pinctrl_gpio_keys: gpiokeysgrp {
-			fsl,pins = <MX27_PAD_PC_VS2__GPIO6_13 0x0>;
-		};
+	pinctrl_gpio_keys: gpiokeysgrp {
+		fsl,pins = <MX27_PAD_PC_VS2__GPIO6_13 0x0>;
+	};
 
-		pinctrl_imxfb1: imxfbgrp {
-			fsl,pins = <
-				MX27_PAD_CLS__CLS 0x0
-				MX27_PAD_CONTRAST__CONTRAST 0x0
-				MX27_PAD_LD0__LD0 0x0
-				MX27_PAD_LD1__LD1 0x0
-				MX27_PAD_LD2__LD2 0x0
-				MX27_PAD_LD3__LD3 0x0
-				MX27_PAD_LD4__LD4 0x0
-				MX27_PAD_LD5__LD5 0x0
-				MX27_PAD_LD6__LD6 0x0
-				MX27_PAD_LD7__LD7 0x0
-				MX27_PAD_LD8__LD8 0x0
-				MX27_PAD_LD9__LD9 0x0
-				MX27_PAD_LD10__LD10 0x0
-				MX27_PAD_LD11__LD11 0x0
-				MX27_PAD_LD12__LD12 0x0
-				MX27_PAD_LD13__LD13 0x0
-				MX27_PAD_LD14__LD14 0x0
-				MX27_PAD_LD15__LD15 0x0
-				MX27_PAD_LD16__LD16 0x0
-				MX27_PAD_LD17__LD17 0x0
-				MX27_PAD_LSCLK__LSCLK 0x0
-				MX27_PAD_OE_ACD__OE_ACD 0x0
-				MX27_PAD_PS__PS 0x0
-				MX27_PAD_REV__REV 0x0
-				MX27_PAD_SPL_SPR__SPL_SPR 0x0
-				MX27_PAD_HSYNC__HSYNC 0x0
-				MX27_PAD_VSYNC__VSYNC 0x0
-			>;
-		};
+	pinctrl_imxfb1: imxfbgrp {
+		fsl,pins = <
+			MX27_PAD_CLS__CLS 0x0
+			MX27_PAD_CONTRAST__CONTRAST 0x0
+			MX27_PAD_LD0__LD0 0x0
+			MX27_PAD_LD1__LD1 0x0
+			MX27_PAD_LD2__LD2 0x0
+			MX27_PAD_LD3__LD3 0x0
+			MX27_PAD_LD4__LD4 0x0
+			MX27_PAD_LD5__LD5 0x0
+			MX27_PAD_LD6__LD6 0x0
+			MX27_PAD_LD7__LD7 0x0
+			MX27_PAD_LD8__LD8 0x0
+			MX27_PAD_LD9__LD9 0x0
+			MX27_PAD_LD10__LD10 0x0
+			MX27_PAD_LD11__LD11 0x0
+			MX27_PAD_LD12__LD12 0x0
+			MX27_PAD_LD13__LD13 0x0
+			MX27_PAD_LD14__LD14 0x0
+			MX27_PAD_LD15__LD15 0x0
+			MX27_PAD_LD16__LD16 0x0
+			MX27_PAD_LD17__LD17 0x0
+			MX27_PAD_LSCLK__LSCLK 0x0
+			MX27_PAD_OE_ACD__OE_ACD 0x0
+			MX27_PAD_PS__PS 0x0
+			MX27_PAD_REV__REV 0x0
+			MX27_PAD_SPL_SPR__SPL_SPR 0x0
+			MX27_PAD_HSYNC__HSYNC 0x0
+			MX27_PAD_VSYNC__VSYNC 0x0
+		>;
+	};
 
-		pinctrl_i2c1: i2c1grp {
-			fsl,pins = <
-				MX27_PAD_I2C_DATA__I2C_DATA 0x0
-				MX27_PAD_I2C_CLK__I2C_CLK 0x0
-			>;
-		};
+	pinctrl_i2c1: i2c1grp {
+		fsl,pins = <
+			MX27_PAD_I2C_DATA__I2C_DATA 0x0
+			MX27_PAD_I2C_CLK__I2C_CLK 0x0
+		>;
+	};
 
-		pinctrl_i2c2: i2c2grp {
-			fsl,pins = <
-				MX27_PAD_I2C2_SDA__I2C2_SDA 0x0
-				MX27_PAD_I2C2_SCL__I2C2_SCL 0x0
-			>;
-		};
+	pinctrl_i2c2: i2c2grp {
+		fsl,pins = <
+			MX27_PAD_I2C2_SDA__I2C2_SDA 0x0
+			MX27_PAD_I2C2_SCL__I2C2_SCL 0x0
+		>;
+	};
 
-		pinctrl_max1027: max1027 {
-			 fsl,pins = <
-				 MX27_PAD_UART1_CTS__GPIO5_14 0x0 /* CNVST */
-				 MX27_PAD_UART1_RTS__GPIO5_15 0x0 /* EOC */
-			>;
-		};
+	pinctrl_max1027: max1027grp {
+		 fsl,pins = <
+			 MX27_PAD_UART1_CTS__GPIO5_14 0x0 /* CNVST */
+			 MX27_PAD_UART1_RTS__GPIO5_15 0x0 /* EOC */
+		>;
+	};
 
-		pinctrl_pwm: pwmgrp {
-			fsl,pins = <
-				MX27_PAD_PWMO__PWMO 0x0
-			>;
-		};
+	pinctrl_pwm: pwmgrp {
+		fsl,pins = <
+			MX27_PAD_PWMO__PWMO 0x0
+		>;
+	};
 
-		pinctrl_sdhc2: sdhc2grp {
-			fsl,pins = <
-				MX27_PAD_SD2_CLK__SD2_CLK 0x0
-				MX27_PAD_SD2_CMD__SD2_CMD 0x0
-				MX27_PAD_SD2_D0__SD2_D0 0x0
-				MX27_PAD_SD2_D1__SD2_D1 0x0
-				MX27_PAD_SD2_D2__SD2_D2 0x0
-				MX27_PAD_SD2_D3__SD2_D3 0x0
-			>;
-		};
+	pinctrl_sdhc2: sdhc2grp {
+		fsl,pins = <
+			MX27_PAD_SD2_CLK__SD2_CLK 0x0
+			MX27_PAD_SD2_CMD__SD2_CMD 0x0
+			MX27_PAD_SD2_D0__SD2_D0 0x0
+			MX27_PAD_SD2_D1__SD2_D1 0x0
+			MX27_PAD_SD2_D2__SD2_D2 0x0
+			MX27_PAD_SD2_D3__SD2_D3 0x0
+		>;
+	};
 
-		pinctrl_sdhc2_cd: sdhc2cdgrp {
-			fsl,pins = <MX27_PAD_TOUT__GPIO3_14 0x0>;
-		};
+	pinctrl_sdhc2_cd: sdhc2cdgrp {
+		fsl,pins = <MX27_PAD_TOUT__GPIO3_14 0x0>;
 	};
 };
 
diff --git a/arch/arm/boot/dts/nxp/imx/imx27-eukrea-cpuimx27.dtsi b/arch/arm/boot/dts/nxp/imx/imx27-eukrea-cpuimx27.dtsi
index c7e923584878..3df70ed6056c 100644
--- a/arch/arm/boot/dts/nxp/imx/imx27-eukrea-cpuimx27.dtsi
+++ b/arch/arm/boot/dts/nxp/imx/imx27-eukrea-cpuimx27.dtsi
@@ -154,131 +154,129 @@ uart8250@3,1000000 {
 };
 
 &iomuxc {
-	imx27-eukrea-cpuimx27 {
-		pinctrl_fec: fecgrp {
-			fsl,pins = <
-				MX27_PAD_SD3_CMD__FEC_TXD0		0x0
-				MX27_PAD_SD3_CLK__FEC_TXD1		0x0
-				MX27_PAD_ATA_DATA0__FEC_TXD2		0x0
-				MX27_PAD_ATA_DATA1__FEC_TXD3		0x0
-				MX27_PAD_ATA_DATA2__FEC_RX_ER		0x0
-				MX27_PAD_ATA_DATA3__FEC_RXD1		0x0
-				MX27_PAD_ATA_DATA4__FEC_RXD2		0x0
-				MX27_PAD_ATA_DATA5__FEC_RXD3		0x0
-				MX27_PAD_ATA_DATA6__FEC_MDIO		0x0
-				MX27_PAD_ATA_DATA7__FEC_MDC		0x0
-				MX27_PAD_ATA_DATA8__FEC_CRS		0x0
-				MX27_PAD_ATA_DATA9__FEC_TX_CLK		0x0
-				MX27_PAD_ATA_DATA10__FEC_RXD0		0x0
-				MX27_PAD_ATA_DATA11__FEC_RX_DV		0x0
-				MX27_PAD_ATA_DATA12__FEC_RX_CLK		0x0
-				MX27_PAD_ATA_DATA13__FEC_COL		0x0
-				MX27_PAD_ATA_DATA14__FEC_TX_ER		0x0
-				MX27_PAD_ATA_DATA15__FEC_TX_EN		0x0
-			>;
-		};
+	pinctrl_fec: fecgrp {
+		fsl,pins = <
+			MX27_PAD_SD3_CMD__FEC_TXD0		0x0
+			MX27_PAD_SD3_CLK__FEC_TXD1		0x0
+			MX27_PAD_ATA_DATA0__FEC_TXD2		0x0
+			MX27_PAD_ATA_DATA1__FEC_TXD3		0x0
+			MX27_PAD_ATA_DATA2__FEC_RX_ER		0x0
+			MX27_PAD_ATA_DATA3__FEC_RXD1		0x0
+			MX27_PAD_ATA_DATA4__FEC_RXD2		0x0
+			MX27_PAD_ATA_DATA5__FEC_RXD3		0x0
+			MX27_PAD_ATA_DATA6__FEC_MDIO		0x0
+			MX27_PAD_ATA_DATA7__FEC_MDC		0x0
+			MX27_PAD_ATA_DATA8__FEC_CRS		0x0
+			MX27_PAD_ATA_DATA9__FEC_TX_CLK		0x0
+			MX27_PAD_ATA_DATA10__FEC_RXD0		0x0
+			MX27_PAD_ATA_DATA11__FEC_RX_DV		0x0
+			MX27_PAD_ATA_DATA12__FEC_RX_CLK		0x0
+			MX27_PAD_ATA_DATA13__FEC_COL		0x0
+			MX27_PAD_ATA_DATA14__FEC_TX_ER		0x0
+			MX27_PAD_ATA_DATA15__FEC_TX_EN		0x0
+		>;
+	};
 
-		pinctrl_i2c1: i2c1grp {
-			fsl,pins = <
-				MX27_PAD_I2C_DATA__I2C_DATA		0x0
-				MX27_PAD_I2C_CLK__I2C_CLK		0x0
-			>;
-		};
+	pinctrl_i2c1: i2c1grp {
+		fsl,pins = <
+			MX27_PAD_I2C_DATA__I2C_DATA		0x0
+			MX27_PAD_I2C_CLK__I2C_CLK		0x0
+		>;
+	};
 
-		pinctrl_nfc: nfcgrp {
-			fsl,pins = <
-				MX27_PAD_NFRB__NFRB			0x0
-				MX27_PAD_NFCLE__NFCLE			0x0
-				MX27_PAD_NFWP_B__NFWP_B			0x0
-				MX27_PAD_NFCE_B__NFCE_B			0x0
-				MX27_PAD_NFALE__NFALE			0x0
-				MX27_PAD_NFRE_B__NFRE_B			0x0
-				MX27_PAD_NFWE_B__NFWE_B			0x0
-			>;
-		};
+	pinctrl_nfc: nfcgrp {
+		fsl,pins = <
+			MX27_PAD_NFRB__NFRB			0x0
+			MX27_PAD_NFCLE__NFCLE			0x0
+			MX27_PAD_NFWP_B__NFWP_B			0x0
+			MX27_PAD_NFCE_B__NFCE_B			0x0
+			MX27_PAD_NFALE__NFALE			0x0
+			MX27_PAD_NFRE_B__NFRE_B			0x0
+			MX27_PAD_NFWE_B__NFWE_B			0x0
+		>;
+	};
 
-		pinctrl_owire: owiregrp {
-			fsl,pins = <
-				MX27_PAD_RTCK__OWIRE			0x0
-			>;
-		};
+	pinctrl_owire: owiregrp {
+		fsl,pins = <
+			MX27_PAD_RTCK__OWIRE			0x0
+		>;
+	};
 
-		pinctrl_sdhc2: sdhc2grp {
-			fsl,pins = <
-				MX27_PAD_SD2_CLK__SD2_CLK		0x0
-				MX27_PAD_SD2_CMD__SD2_CMD		0x0
-				MX27_PAD_SD2_D0__SD2_D0			0x0
-				MX27_PAD_SD2_D1__SD2_D1			0x0
-				MX27_PAD_SD2_D2__SD2_D2			0x0
-				MX27_PAD_SD2_D3__SD2_D3			0x0
-			>;
-		};
+	pinctrl_sdhc2: sdhc2grp {
+		fsl,pins = <
+			MX27_PAD_SD2_CLK__SD2_CLK		0x0
+			MX27_PAD_SD2_CMD__SD2_CMD		0x0
+			MX27_PAD_SD2_D0__SD2_D0			0x0
+			MX27_PAD_SD2_D1__SD2_D1			0x0
+			MX27_PAD_SD2_D2__SD2_D2			0x0
+			MX27_PAD_SD2_D3__SD2_D3			0x0
+		>;
+	};
 
-		pinctrl_uart4: uart4grp {
-			fsl,pins = <
-				MX27_PAD_USBH1_TXDM__UART4_TXD		0x0
-				MX27_PAD_USBH1_RXDP__UART4_RXD		0x0
-				MX27_PAD_USBH1_TXDP__UART4_CTS		0x0
-				MX27_PAD_USBH1_FS__UART4_RTS		0x0
-			>;
-		};
+	pinctrl_uart4: uart4grp {
+		fsl,pins = <
+			MX27_PAD_USBH1_TXDM__UART4_TXD		0x0
+			MX27_PAD_USBH1_RXDP__UART4_RXD		0x0
+			MX27_PAD_USBH1_TXDP__UART4_CTS		0x0
+			MX27_PAD_USBH1_FS__UART4_RTS		0x0
+		>;
+	};
 
-		pinctrl_uart8250_1: uart82501grp {
-			fsl,pins = <
-				MX27_PAD_USB_PWR__GPIO2_23		0x0
-			>;
-		};
+	pinctrl_uart8250_1: uart82501grp {
+		fsl,pins = <
+			MX27_PAD_USB_PWR__GPIO2_23		0x0
+		>;
+	};
 
-		pinctrl_uart8250_2: uart82502grp {
-			fsl,pins = <
-				MX27_PAD_USBH1_SUSP__GPIO2_22		0x0
-			>;
-		};
+	pinctrl_uart8250_2: uart82502grp {
+		fsl,pins = <
+			MX27_PAD_USBH1_SUSP__GPIO2_22		0x0
+		>;
+	};
 
-		pinctrl_uart8250_3: uart82503grp {
-			fsl,pins = <
-				MX27_PAD_USBH1_OE_B__GPIO2_27		0x0
-			>;
-		};
+	pinctrl_uart8250_3: uart82503grp {
+		fsl,pins = <
+			MX27_PAD_USBH1_OE_B__GPIO2_27		0x0
+		>;
+	};
 
-		pinctrl_uart8250_4: uart82504grp {
-			fsl,pins = <
-				MX27_PAD_USBH1_RXDM__GPIO2_30		0x0
-			>;
-		};
+	pinctrl_uart8250_4: uart82504grp {
+		fsl,pins = <
+			MX27_PAD_USBH1_RXDM__GPIO2_30		0x0
+		>;
+	};
 
-		pinctrl_usbh2: usbh2grp {
-			fsl,pins = <
-				MX27_PAD_USBH2_CLK__USBH2_CLK		0x0
-				MX27_PAD_USBH2_DIR__USBH2_DIR		0x0
-				MX27_PAD_USBH2_NXT__USBH2_NXT		0x0
-				MX27_PAD_USBH2_STP__USBH2_STP		0x0
-				MX27_PAD_CSPI2_SCLK__USBH2_DATA0	0x0
-				MX27_PAD_CSPI2_MOSI__USBH2_DATA1	0x0
-				MX27_PAD_CSPI2_MISO__USBH2_DATA2	0x0
-				MX27_PAD_CSPI2_SS1__USBH2_DATA3		0x0
-				MX27_PAD_CSPI2_SS2__USBH2_DATA4		0x0
-				MX27_PAD_CSPI1_SS2__USBH2_DATA5		0x0
-				MX27_PAD_CSPI2_SS0__USBH2_DATA6		0x0
-				MX27_PAD_USBH2_DATA7__USBH2_DATA7	0x0
-			>;
-		};
+	pinctrl_usbh2: usbh2grp {
+		fsl,pins = <
+			MX27_PAD_USBH2_CLK__USBH2_CLK		0x0
+			MX27_PAD_USBH2_DIR__USBH2_DIR		0x0
+			MX27_PAD_USBH2_NXT__USBH2_NXT		0x0
+			MX27_PAD_USBH2_STP__USBH2_STP		0x0
+			MX27_PAD_CSPI2_SCLK__USBH2_DATA0	0x0
+			MX27_PAD_CSPI2_MOSI__USBH2_DATA1	0x0
+			MX27_PAD_CSPI2_MISO__USBH2_DATA2	0x0
+			MX27_PAD_CSPI2_SS1__USBH2_DATA3		0x0
+			MX27_PAD_CSPI2_SS2__USBH2_DATA4		0x0
+			MX27_PAD_CSPI1_SS2__USBH2_DATA5		0x0
+			MX27_PAD_CSPI2_SS0__USBH2_DATA6		0x0
+			MX27_PAD_USBH2_DATA7__USBH2_DATA7	0x0
+		>;
+	};
 
-		pinctrl_usbotg: usbotggrp {
-			fsl,pins = <
-				MX27_PAD_USBOTG_CLK__USBOTG_CLK		0x0
-				MX27_PAD_USBOTG_DIR__USBOTG_DIR		0x0
-				MX27_PAD_USBOTG_NXT__USBOTG_NXT		0x0
-				MX27_PAD_USBOTG_STP__USBOTG_STP		0x0
-				MX27_PAD_USBOTG_DATA0__USBOTG_DATA0	0x0
-				MX27_PAD_USBOTG_DATA1__USBOTG_DATA1	0x0
-				MX27_PAD_USBOTG_DATA2__USBOTG_DATA2	0x0
-				MX27_PAD_USBOTG_DATA3__USBOTG_DATA3	0x0
-				MX27_PAD_USBOTG_DATA4__USBOTG_DATA4	0x0
-				MX27_PAD_USBOTG_DATA5__USBOTG_DATA5	0x0
-				MX27_PAD_USBOTG_DATA6__USBOTG_DATA6	0x0
-				MX27_PAD_USBOTG_DATA7__USBOTG_DATA7	0x0
-			>;
-		};
+	pinctrl_usbotg: usbotggrp {
+		fsl,pins = <
+			MX27_PAD_USBOTG_CLK__USBOTG_CLK		0x0
+			MX27_PAD_USBOTG_DIR__USBOTG_DIR		0x0
+			MX27_PAD_USBOTG_NXT__USBOTG_NXT		0x0
+			MX27_PAD_USBOTG_STP__USBOTG_STP		0x0
+			MX27_PAD_USBOTG_DATA0__USBOTG_DATA0	0x0
+			MX27_PAD_USBOTG_DATA1__USBOTG_DATA1	0x0
+			MX27_PAD_USBOTG_DATA2__USBOTG_DATA2	0x0
+			MX27_PAD_USBOTG_DATA3__USBOTG_DATA3	0x0
+			MX27_PAD_USBOTG_DATA4__USBOTG_DATA4	0x0
+			MX27_PAD_USBOTG_DATA5__USBOTG_DATA5	0x0
+			MX27_PAD_USBOTG_DATA6__USBOTG_DATA6	0x0
+			MX27_PAD_USBOTG_DATA7__USBOTG_DATA7	0x0
+		>;
 	};
 };
diff --git a/arch/arm/boot/dts/nxp/imx/imx27-eukrea-mbimxsd27-baseboard.dts b/arch/arm/boot/dts/nxp/imx/imx27-eukrea-mbimxsd27-baseboard.dts
index d78793601306..1c834f2f5068 100644
--- a/arch/arm/boot/dts/nxp/imx/imx27-eukrea-mbimxsd27-baseboard.dts
+++ b/arch/arm/boot/dts/nxp/imx/imx27-eukrea-mbimxsd27-baseboard.dts
@@ -147,113 +147,111 @@ &uart3 {
 };
 
 &iomuxc {
-	imx27-eukrea-cpuimx27-baseboard {
-		pinctrl_cspi1: cspi1grp {
-			fsl,pins = <
-				MX27_PAD_CSPI1_MISO__CSPI1_MISO	0x0
-				MX27_PAD_CSPI1_MOSI__CSPI1_MOSI	0x0
-				MX27_PAD_CSPI1_SCLK__CSPI1_SCLK	0x0
-				MX27_PAD_CSPI1_SS0__GPIO4_28	0x0 /* CS0 */
-			>;
-		};
+	pinctrl_cspi1: cspi1grp {
+		fsl,pins = <
+			MX27_PAD_CSPI1_MISO__CSPI1_MISO	0x0
+			MX27_PAD_CSPI1_MOSI__CSPI1_MOSI	0x0
+			MX27_PAD_CSPI1_SCLK__CSPI1_SCLK	0x0
+			MX27_PAD_CSPI1_SS0__GPIO4_28	0x0 /* CS0 */
+		>;
+	};
 
-		pinctrl_backlight: backlightgrp {
-			fsl,pins = <
-				MX27_PAD_PWMO__GPIO5_5		0x0
-			>;
-		};
+	pinctrl_backlight: backlightgrp {
+		fsl,pins = <
+			MX27_PAD_PWMO__GPIO5_5		0x0
+		>;
+	};
 
-		pinctrl_gpioleds: gpioledsgrp {
-			fsl,pins = <
-				MX27_PAD_PC_PWRON__GPIO6_16	0x0
-				MX27_PAD_PC_CD2_B__GPIO6_19	0x0
-			>;
-		};
+	pinctrl_gpioleds: gpioledsgrp {
+		fsl,pins = <
+			MX27_PAD_PC_PWRON__GPIO6_16	0x0
+			MX27_PAD_PC_CD2_B__GPIO6_19	0x0
+		>;
+	};
 
-		pinctrl_imxfb: imxfbgrp {
-			fsl,pins = <
-				MX27_PAD_LD0__LD0		0x0
-				MX27_PAD_LD1__LD1		0x0
-				MX27_PAD_LD2__LD2		0x0
-				MX27_PAD_LD3__LD3		0x0
-				MX27_PAD_LD4__LD4		0x0
-				MX27_PAD_LD5__LD5		0x0
-				MX27_PAD_LD6__LD6		0x0
-				MX27_PAD_LD7__LD7		0x0
-				MX27_PAD_LD8__LD8		0x0
-				MX27_PAD_LD9__LD9		0x0
-				MX27_PAD_LD10__LD10		0x0
-				MX27_PAD_LD11__LD11		0x0
-				MX27_PAD_LD12__LD12		0x0
-				MX27_PAD_LD13__LD13		0x0
-				MX27_PAD_LD14__LD14		0x0
-				MX27_PAD_LD15__LD15		0x0
-				MX27_PAD_LD16__LD16		0x0
-				MX27_PAD_LD17__LD17		0x0
-				MX27_PAD_CONTRAST__CONTRAST	0x0
-				MX27_PAD_OE_ACD__OE_ACD		0x0
-				MX27_PAD_HSYNC__HSYNC		0x0
-				MX27_PAD_VSYNC__VSYNC		0x0
-			>;
-		};
+	pinctrl_imxfb: imxfbgrp {
+		fsl,pins = <
+			MX27_PAD_LD0__LD0		0x0
+			MX27_PAD_LD1__LD1		0x0
+			MX27_PAD_LD2__LD2		0x0
+			MX27_PAD_LD3__LD3		0x0
+			MX27_PAD_LD4__LD4		0x0
+			MX27_PAD_LD5__LD5		0x0
+			MX27_PAD_LD6__LD6		0x0
+			MX27_PAD_LD7__LD7		0x0
+			MX27_PAD_LD8__LD8		0x0
+			MX27_PAD_LD9__LD9		0x0
+			MX27_PAD_LD10__LD10		0x0
+			MX27_PAD_LD11__LD11		0x0
+			MX27_PAD_LD12__LD12		0x0
+			MX27_PAD_LD13__LD13		0x0
+			MX27_PAD_LD14__LD14		0x0
+			MX27_PAD_LD15__LD15		0x0
+			MX27_PAD_LD16__LD16		0x0
+			MX27_PAD_LD17__LD17		0x0
+			MX27_PAD_CONTRAST__CONTRAST	0x0
+			MX27_PAD_OE_ACD__OE_ACD		0x0
+			MX27_PAD_HSYNC__HSYNC		0x0
+			MX27_PAD_VSYNC__VSYNC		0x0
+		>;
+	};
 
-		pinctrl_lcdreg: lcdreggrp {
-			fsl,pins = <
-				MX27_PAD_CLS__GPIO1_25		0x0
-			>;
-		};
+	pinctrl_lcdreg: lcdreggrp {
+		fsl,pins = <
+			MX27_PAD_CLS__GPIO1_25		0x0
+		>;
+	};
 
-		pinctrl_sdhc1: sdhc1grp {
-			fsl,pins = <
-				MX27_PAD_SD1_CLK__SD1_CLK	0x0
-				MX27_PAD_SD1_CMD__SD1_CMD	0x0
-				MX27_PAD_SD1_D0__SD1_D0		0x0
-				MX27_PAD_SD1_D1__SD1_D1		0x0
-				MX27_PAD_SD1_D2__SD1_D2		0x0
-				MX27_PAD_SD1_D3__SD1_D3		0x0
-			>;
-		};
+	pinctrl_sdhc1: sdhc1grp {
+		fsl,pins = <
+			MX27_PAD_SD1_CLK__SD1_CLK	0x0
+			MX27_PAD_SD1_CMD__SD1_CMD	0x0
+			MX27_PAD_SD1_D0__SD1_D0		0x0
+			MX27_PAD_SD1_D1__SD1_D1		0x0
+			MX27_PAD_SD1_D2__SD1_D2		0x0
+			MX27_PAD_SD1_D3__SD1_D3		0x0
+		>;
+	};
 
-		pinctrl_ssi1: ssi1grp {
-			fsl,pins = <
-				MX27_PAD_SSI4_CLK__SSI4_CLK	0x0
-				MX27_PAD_SSI4_FS__SSI4_FS	0x0
-				MX27_PAD_SSI4_RXDAT__SSI4_RXDAT	0x1
-				MX27_PAD_SSI4_TXDAT__SSI4_TXDAT	0x1
-			>;
-		};
+	pinctrl_ssi1: ssi1grp {
+		fsl,pins = <
+			MX27_PAD_SSI4_CLK__SSI4_CLK	0x0
+			MX27_PAD_SSI4_FS__SSI4_FS	0x0
+			MX27_PAD_SSI4_RXDAT__SSI4_RXDAT	0x1
+			MX27_PAD_SSI4_TXDAT__SSI4_TXDAT	0x1
+		>;
+	};
 
-		pinctrl_touch: touchgrp {
-			fsl,pins = <
-				MX27_PAD_CSPI1_RDY__GPIO4_25	0x0 /* IRQ */
-			>;
-		};
+	pinctrl_touch: touchgrp {
+		fsl,pins = <
+			MX27_PAD_CSPI1_RDY__GPIO4_25	0x0 /* IRQ */
+		>;
+	};
 
-		pinctrl_uart1: uart1grp {
-			fsl,pins = <
-				MX27_PAD_UART1_TXD__UART1_TXD	0x0
-				MX27_PAD_UART1_RXD__UART1_RXD	0x0
-				MX27_PAD_UART1_CTS__UART1_CTS	0x0
-				MX27_PAD_UART1_RTS__UART1_RTS	0x0
-			>;
-		};
+	pinctrl_uart1: uart1grp {
+		fsl,pins = <
+			MX27_PAD_UART1_TXD__UART1_TXD	0x0
+			MX27_PAD_UART1_RXD__UART1_RXD	0x0
+			MX27_PAD_UART1_CTS__UART1_CTS	0x0
+			MX27_PAD_UART1_RTS__UART1_RTS	0x0
+		>;
+	};
 
-		pinctrl_uart2: uart2grp {
-			fsl,pins = <
-				MX27_PAD_UART2_TXD__UART2_TXD	0x0
-				MX27_PAD_UART2_RXD__UART2_RXD	0x0
-				MX27_PAD_UART2_CTS__UART2_CTS	0x0
-				MX27_PAD_UART2_RTS__UART2_RTS	0x0
-			>;
-		};
+	pinctrl_uart2: uart2grp {
+		fsl,pins = <
+			MX27_PAD_UART2_TXD__UART2_TXD	0x0
+			MX27_PAD_UART2_RXD__UART2_RXD	0x0
+			MX27_PAD_UART2_CTS__UART2_CTS	0x0
+			MX27_PAD_UART2_RTS__UART2_RTS	0x0
+		>;
+	};
 
-		pinctrl_uart3: uart3grp {
-			fsl,pins = <
-				MX27_PAD_UART3_TXD__UART3_TXD	0x0
-				MX27_PAD_UART3_RXD__UART3_RXD	0x0
-				MX27_PAD_UART3_CTS__UART3_CTS	0x0
-				MX27_PAD_UART3_RTS__UART3_RTS	0x0
-			>;
-		};
+	pinctrl_uart3: uart3grp {
+		fsl,pins = <
+			MX27_PAD_UART3_TXD__UART3_TXD	0x0
+			MX27_PAD_UART3_RXD__UART3_RXD	0x0
+			MX27_PAD_UART3_CTS__UART3_CTS	0x0
+			MX27_PAD_UART3_RTS__UART3_RTS	0x0
+		>;
 	};
 };
diff --git a/arch/arm/boot/dts/nxp/imx/imx27-pdk.dts b/arch/arm/boot/dts/nxp/imx/imx27-pdk.dts
index 21d436972aa4..2fc4ea5b9501 100644
--- a/arch/arm/boot/dts/nxp/imx/imx27-pdk.dts
+++ b/arch/arm/boot/dts/nxp/imx/imx27-pdk.dts
@@ -110,76 +110,74 @@ &usbotg {
 };
 
 &iomuxc {
-	imx27-pdk {
-		pinctrl_cspi2: cspi2grp {
-			fsl,pins = <
-				MX27_PAD_CSPI2_MISO__CSPI2_MISO 0x0
-				MX27_PAD_CSPI2_MOSI__CSPI2_MOSI 0x0
-				MX27_PAD_CSPI2_SCLK__CSPI2_SCLK 0x0
-				MX27_PAD_CSPI2_SS0__GPIO4_21	0x0 /* SPI2 CS0 */
-				MX27_PAD_TOUT__GPIO3_14		0x0 /* PMIC IRQ */
-			>;
-		};
+	pinctrl_cspi2: cspi2grp {
+		fsl,pins = <
+			MX27_PAD_CSPI2_MISO__CSPI2_MISO 0x0
+			MX27_PAD_CSPI2_MOSI__CSPI2_MOSI 0x0
+			MX27_PAD_CSPI2_SCLK__CSPI2_SCLK 0x0
+			MX27_PAD_CSPI2_SS0__GPIO4_21	0x0 /* SPI2 CS0 */
+			MX27_PAD_TOUT__GPIO3_14		0x0 /* PMIC IRQ */
+		>;
+	};
 
-		pinctrl_fec: fecgrp {
-			fsl,pins = <
-				MX27_PAD_SD3_CMD__FEC_TXD0 0x0
-				MX27_PAD_SD3_CLK__FEC_TXD1 0x0
-				MX27_PAD_ATA_DATA0__FEC_TXD2 0x0
-				MX27_PAD_ATA_DATA1__FEC_TXD3 0x0
-				MX27_PAD_ATA_DATA2__FEC_RX_ER 0x0
-				MX27_PAD_ATA_DATA3__FEC_RXD1 0x0
-				MX27_PAD_ATA_DATA4__FEC_RXD2 0x0
-				MX27_PAD_ATA_DATA5__FEC_RXD3 0x0
-				MX27_PAD_ATA_DATA6__FEC_MDIO 0x0
-				MX27_PAD_ATA_DATA7__FEC_MDC 0x0
-				MX27_PAD_ATA_DATA8__FEC_CRS 0x0
-				MX27_PAD_ATA_DATA9__FEC_TX_CLK 0x0
-				MX27_PAD_ATA_DATA10__FEC_RXD0 0x0
-				MX27_PAD_ATA_DATA11__FEC_RX_DV 0x0
-				MX27_PAD_ATA_DATA12__FEC_RX_CLK 0x0
-				MX27_PAD_ATA_DATA13__FEC_COL 0x0
-				MX27_PAD_ATA_DATA14__FEC_TX_ER 0x0
-				MX27_PAD_ATA_DATA15__FEC_TX_EN 0x0
-			>;
-		};
+	pinctrl_fec: fecgrp {
+		fsl,pins = <
+			MX27_PAD_SD3_CMD__FEC_TXD0 0x0
+			MX27_PAD_SD3_CLK__FEC_TXD1 0x0
+			MX27_PAD_ATA_DATA0__FEC_TXD2 0x0
+			MX27_PAD_ATA_DATA1__FEC_TXD3 0x0
+			MX27_PAD_ATA_DATA2__FEC_RX_ER 0x0
+			MX27_PAD_ATA_DATA3__FEC_RXD1 0x0
+			MX27_PAD_ATA_DATA4__FEC_RXD2 0x0
+			MX27_PAD_ATA_DATA5__FEC_RXD3 0x0
+			MX27_PAD_ATA_DATA6__FEC_MDIO 0x0
+			MX27_PAD_ATA_DATA7__FEC_MDC 0x0
+			MX27_PAD_ATA_DATA8__FEC_CRS 0x0
+			MX27_PAD_ATA_DATA9__FEC_TX_CLK 0x0
+			MX27_PAD_ATA_DATA10__FEC_RXD0 0x0
+			MX27_PAD_ATA_DATA11__FEC_RX_DV 0x0
+			MX27_PAD_ATA_DATA12__FEC_RX_CLK 0x0
+			MX27_PAD_ATA_DATA13__FEC_COL 0x0
+			MX27_PAD_ATA_DATA14__FEC_TX_ER 0x0
+			MX27_PAD_ATA_DATA15__FEC_TX_EN 0x0
+		>;
+	};
 
-		pinctrl_nand: nandgrp {
-			fsl,pins = <
-				MX27_PAD_NFRB__NFRB	0x0
-				MX27_PAD_NFCLE__NFCLE	0x0
-				MX27_PAD_NFWP_B__NFWP_B	0x0
-				MX27_PAD_NFCE_B__NFCE_B	0x0
-				MX27_PAD_NFALE__NFALE	0x0
-				MX27_PAD_NFRE_B__NFRE_B	0x0
-				MX27_PAD_NFWE_B__NFWE_B	0x0
-			>;
-		};
+	pinctrl_nand: nandgrp {
+		fsl,pins = <
+			MX27_PAD_NFRB__NFRB	0x0
+			MX27_PAD_NFCLE__NFCLE	0x0
+			MX27_PAD_NFWP_B__NFWP_B	0x0
+			MX27_PAD_NFCE_B__NFCE_B	0x0
+			MX27_PAD_NFALE__NFALE	0x0
+			MX27_PAD_NFRE_B__NFRE_B	0x0
+			MX27_PAD_NFWE_B__NFWE_B	0x0
+		>;
+	};
 
-		pinctrl_uart1: uart1grp {
-			fsl,pins = <
-				MX27_PAD_UART1_TXD__UART1_TXD 0x0
-				MX27_PAD_UART1_RXD__UART1_RXD 0x0
-				MX27_PAD_UART1_CTS__UART1_CTS 0x0
-				MX27_PAD_UART1_RTS__UART1_RTS 0x0
-			>;
-		};
+	pinctrl_uart1: uart1grp {
+		fsl,pins = <
+			MX27_PAD_UART1_TXD__UART1_TXD 0x0
+			MX27_PAD_UART1_RXD__UART1_RXD 0x0
+			MX27_PAD_UART1_CTS__UART1_CTS 0x0
+			MX27_PAD_UART1_RTS__UART1_RTS 0x0
+		>;
+	};
 
-		pinctrl_usbotg: usbotggrp {
-			fsl,pins = <
-				MX27_PAD_USBOTG_NXT__USBOTG_NXT 0x0
-				MX27_PAD_USBOTG_STP__USBOTG_STP 0x0
-				MX27_PAD_USBOTG_DIR__USBOTG_DIR 0x0
-				MX27_PAD_USBOTG_CLK__USBOTG_CLK 0x0
-				MX27_PAD_USBOTG_DATA0__USBOTG_DATA0 0x0
-				MX27_PAD_USBOTG_DATA1__USBOTG_DATA1 0x0
-				MX27_PAD_USBOTG_DATA2__USBOTG_DATA2 0x0
-				MX27_PAD_USBOTG_DATA3__USBOTG_DATA3 0x0
-				MX27_PAD_USBOTG_DATA4__USBOTG_DATA4 0x0
-				MX27_PAD_USBOTG_DATA5__USBOTG_DATA5 0x0
-				MX27_PAD_USBOTG_DATA6__USBOTG_DATA6 0x0
-				MX27_PAD_USBOTG_DATA7__USBOTG_DATA7 0x0
-			>;
-		};
+	pinctrl_usbotg: usbotggrp {
+		fsl,pins = <
+			MX27_PAD_USBOTG_NXT__USBOTG_NXT 0x0
+			MX27_PAD_USBOTG_STP__USBOTG_STP 0x0
+			MX27_PAD_USBOTG_DIR__USBOTG_DIR 0x0
+			MX27_PAD_USBOTG_CLK__USBOTG_CLK 0x0
+			MX27_PAD_USBOTG_DATA0__USBOTG_DATA0 0x0
+			MX27_PAD_USBOTG_DATA1__USBOTG_DATA1 0x0
+			MX27_PAD_USBOTG_DATA2__USBOTG_DATA2 0x0
+			MX27_PAD_USBOTG_DATA3__USBOTG_DATA3 0x0
+			MX27_PAD_USBOTG_DATA4__USBOTG_DATA4 0x0
+			MX27_PAD_USBOTG_DATA5__USBOTG_DATA5 0x0
+			MX27_PAD_USBOTG_DATA6__USBOTG_DATA6 0x0
+			MX27_PAD_USBOTG_DATA7__USBOTG_DATA7 0x0
+		>;
 	};
 };
diff --git a/arch/arm/boot/dts/nxp/imx/imx27-phytec-phycard-s-rdk.dts b/arch/arm/boot/dts/nxp/imx/imx27-phytec-phycard-s-rdk.dts
index 27c93b9fe049..2b884cb3e381 100644
--- a/arch/arm/boot/dts/nxp/imx/imx27-phytec-phycard-s-rdk.dts
+++ b/arch/arm/boot/dts/nxp/imx/imx27-phytec-phycard-s-rdk.dts
@@ -65,58 +65,56 @@ adc@64 {
 };
 
 &iomuxc {
-	imx27-phycard-s-rdk {
-		pinctrl_i2c1: i2c1grp {
-			fsl,pins = <
-				MX27_PAD_I2C_DATA__I2C_DATA 0x0
-				MX27_PAD_I2C_CLK__I2C_CLK 0x0
-			>;
-		};
+	pinctrl_i2c1: i2c1grp {
+		fsl,pins = <
+			MX27_PAD_I2C_DATA__I2C_DATA 0x0
+			MX27_PAD_I2C_CLK__I2C_CLK 0x0
+		>;
+	};
 
-		pinctrl_owire1: owire1grp {
-			fsl,pins = <
-				MX27_PAD_RTCK__OWIRE 0x0
-			>;
-		};
+	pinctrl_owire1: owire1grp {
+		fsl,pins = <
+			MX27_PAD_RTCK__OWIRE 0x0
+		>;
+	};
 
-		pinctrl_sdhc2: sdhc2grp {
-			fsl,pins = <
-				MX27_PAD_SD2_CLK__SD2_CLK 0x0
-				MX27_PAD_SD2_CMD__SD2_CMD 0x0
-				MX27_PAD_SD2_D0__SD2_D0 0x0
-				MX27_PAD_SD2_D1__SD2_D1 0x0
-				MX27_PAD_SD2_D2__SD2_D2 0x0
-				MX27_PAD_SD2_D3__SD2_D3 0x0
-				MX27_PAD_SSI3_RXDAT__GPIO3_29 0x0 /* CD */
-			>;
-		};
+	pinctrl_sdhc2: sdhc2grp {
+		fsl,pins = <
+			MX27_PAD_SD2_CLK__SD2_CLK 0x0
+			MX27_PAD_SD2_CMD__SD2_CMD 0x0
+			MX27_PAD_SD2_D0__SD2_D0 0x0
+			MX27_PAD_SD2_D1__SD2_D1 0x0
+			MX27_PAD_SD2_D2__SD2_D2 0x0
+			MX27_PAD_SD2_D3__SD2_D3 0x0
+			MX27_PAD_SSI3_RXDAT__GPIO3_29 0x0 /* CD */
+		>;
+	};
 
-		pinctrl_uart1: uart1grp {
-			fsl,pins = <
-				MX27_PAD_UART1_TXD__UART1_TXD 0x0
-				MX27_PAD_UART1_RXD__UART1_RXD 0x0
-				MX27_PAD_UART1_CTS__UART1_CTS 0x0
-				MX27_PAD_UART1_RTS__UART1_RTS 0x0
-			>;
-		};
+	pinctrl_uart1: uart1grp {
+		fsl,pins = <
+			MX27_PAD_UART1_TXD__UART1_TXD 0x0
+			MX27_PAD_UART1_RXD__UART1_RXD 0x0
+			MX27_PAD_UART1_CTS__UART1_CTS 0x0
+			MX27_PAD_UART1_RTS__UART1_RTS 0x0
+		>;
+	};
 
-		pinctrl_uart2: uart2grp {
-			fsl,pins = <
-				MX27_PAD_UART2_TXD__UART2_TXD 0x0
-				MX27_PAD_UART2_RXD__UART2_RXD 0x0
-				MX27_PAD_UART2_CTS__UART2_CTS 0x0
-				MX27_PAD_UART2_RTS__UART2_RTS 0x0
-			>;
-		};
+	pinctrl_uart2: uart2grp {
+		fsl,pins = <
+			MX27_PAD_UART2_TXD__UART2_TXD 0x0
+			MX27_PAD_UART2_RXD__UART2_RXD 0x0
+			MX27_PAD_UART2_CTS__UART2_CTS 0x0
+			MX27_PAD_UART2_RTS__UART2_RTS 0x0
+		>;
+	};
 
-		pinctrl_uart3: uart3grp {
-			fsl,pins = <
-				MX27_PAD_UART3_TXD__UART3_TXD 0x0
-				MX27_PAD_UART3_RXD__UART3_RXD 0x0
-				MX27_PAD_UART3_CTS__UART3_CTS 0x0
-				MX27_PAD_UART3_RTS__UART3_RTS 0x0
-			>;
-		};
+	pinctrl_uart3: uart3grp {
+		fsl,pins = <
+			MX27_PAD_UART3_TXD__UART3_TXD 0x0
+			MX27_PAD_UART3_RXD__UART3_RXD 0x0
+			MX27_PAD_UART3_CTS__UART3_CTS 0x0
+			MX27_PAD_UART3_RTS__UART3_RTS 0x0
+		>;
 	};
 };
 
diff --git a/arch/arm/boot/dts/nxp/imx/imx27-phytec-phycard-s-som.dtsi b/arch/arm/boot/dts/nxp/imx/imx27-phytec-phycard-s-som.dtsi
index 31b3fc972abb..2f60b3809f39 100644
--- a/arch/arm/boot/dts/nxp/imx/imx27-phytec-phycard-s-som.dtsi
+++ b/arch/arm/boot/dts/nxp/imx/imx27-phytec-phycard-s-som.dtsi
@@ -58,94 +58,92 @@ eeprom@52 {
 };
 
 &iomuxc {
-	imx27-phycard-s-som {
-		pinctrl_fec1: fec1grp {
-			fsl,pins = <
-				MX27_PAD_SD3_CMD__FEC_TXD0 0x0
-				MX27_PAD_SD3_CLK__FEC_TXD1 0x0
-				MX27_PAD_ATA_DATA0__FEC_TXD2 0x0
-				MX27_PAD_ATA_DATA1__FEC_TXD3 0x0
-				MX27_PAD_ATA_DATA2__FEC_RX_ER 0x0
-				MX27_PAD_ATA_DATA3__FEC_RXD1 0x0
-				MX27_PAD_ATA_DATA4__FEC_RXD2 0x0
-				MX27_PAD_ATA_DATA5__FEC_RXD3 0x0
-				MX27_PAD_ATA_DATA6__FEC_MDIO 0x0
-				MX27_PAD_ATA_DATA7__FEC_MDC 0x0
-				MX27_PAD_ATA_DATA8__FEC_CRS 0x0
-				MX27_PAD_ATA_DATA9__FEC_TX_CLK 0x0
-				MX27_PAD_ATA_DATA10__FEC_RXD0 0x0
-				MX27_PAD_ATA_DATA11__FEC_RX_DV 0x0
-				MX27_PAD_ATA_DATA12__FEC_RX_CLK 0x0
-				MX27_PAD_ATA_DATA13__FEC_COL 0x0
-				MX27_PAD_ATA_DATA14__FEC_TX_ER 0x0
-				MX27_PAD_ATA_DATA15__FEC_TX_EN 0x0
-			>;
-		};
+	pinctrl_fec1: fec1grp {
+		fsl,pins = <
+			MX27_PAD_SD3_CMD__FEC_TXD0 0x0
+			MX27_PAD_SD3_CLK__FEC_TXD1 0x0
+			MX27_PAD_ATA_DATA0__FEC_TXD2 0x0
+			MX27_PAD_ATA_DATA1__FEC_TXD3 0x0
+			MX27_PAD_ATA_DATA2__FEC_RX_ER 0x0
+			MX27_PAD_ATA_DATA3__FEC_RXD1 0x0
+			MX27_PAD_ATA_DATA4__FEC_RXD2 0x0
+			MX27_PAD_ATA_DATA5__FEC_RXD3 0x0
+			MX27_PAD_ATA_DATA6__FEC_MDIO 0x0
+			MX27_PAD_ATA_DATA7__FEC_MDC 0x0
+			MX27_PAD_ATA_DATA8__FEC_CRS 0x0
+			MX27_PAD_ATA_DATA9__FEC_TX_CLK 0x0
+			MX27_PAD_ATA_DATA10__FEC_RXD0 0x0
+			MX27_PAD_ATA_DATA11__FEC_RX_DV 0x0
+			MX27_PAD_ATA_DATA12__FEC_RX_CLK 0x0
+			MX27_PAD_ATA_DATA13__FEC_COL 0x0
+			MX27_PAD_ATA_DATA14__FEC_TX_ER 0x0
+			MX27_PAD_ATA_DATA15__FEC_TX_EN 0x0
+		>;
+	};
 
-		pinctrl_i2c2: i2c2grp {
-			fsl,pins = <
-				MX27_PAD_I2C2_SDA__I2C2_SDA 0x0
-				MX27_PAD_I2C2_SCL__I2C2_SCL 0x0
-			>;
-		};
+	pinctrl_i2c2: i2c2grp {
+		fsl,pins = <
+			MX27_PAD_I2C2_SDA__I2C2_SDA 0x0
+			MX27_PAD_I2C2_SCL__I2C2_SCL 0x0
+		>;
+	};
 
-		pinctrl_nfc: nfcgrp {
-			fsl,pins = <
-				MX27_PAD_NFRB__NFRB 0x0
-				MX27_PAD_NFCLE__NFCLE 0x0
-				MX27_PAD_NFWP_B__NFWP_B 0x0
-				MX27_PAD_NFCE_B__NFCE_B 0x0
-				MX27_PAD_NFALE__NFALE 0x0
-				MX27_PAD_NFRE_B__NFRE_B 0x0
-				MX27_PAD_NFWE_B__NFWE_B 0x0
-			>;
-		};
+	pinctrl_nfc: nfcgrp {
+		fsl,pins = <
+			MX27_PAD_NFRB__NFRB 0x0
+			MX27_PAD_NFCLE__NFCLE 0x0
+			MX27_PAD_NFWP_B__NFWP_B 0x0
+			MX27_PAD_NFCE_B__NFCE_B 0x0
+			MX27_PAD_NFALE__NFALE 0x0
+			MX27_PAD_NFRE_B__NFRE_B 0x0
+			MX27_PAD_NFWE_B__NFWE_B 0x0
+		>;
+	};
 
-		pinctrl_usbotgphy: usbotgphygrp {
-			fsl,pins = <
-				MX27_PAD_USBH1_RCV__GPIO2_25		0x1 /* reset gpio */
-			>;
-		};
+	pinctrl_usbotgphy: usbotgphygrp {
+		fsl,pins = <
+			MX27_PAD_USBH1_RCV__GPIO2_25		0x1 /* reset gpio */
+		>;
+	};
 
-		pinctrl_usbotg: usbotggrp {
-			fsl,pins = <
-				MX27_PAD_USBOTG_CLK__USBOTG_CLK		0x0
-				MX27_PAD_USBOTG_DIR__USBOTG_DIR		0x0
-				MX27_PAD_USBOTG_NXT__USBOTG_NXT		0x0
-				MX27_PAD_USBOTG_STP__USBOTG_STP		0x0
-				MX27_PAD_USBOTG_DATA0__USBOTG_DATA0	0x0
-				MX27_PAD_USBOTG_DATA1__USBOTG_DATA1	0x0
-				MX27_PAD_USBOTG_DATA2__USBOTG_DATA2	0x0
-				MX27_PAD_USBOTG_DATA3__USBOTG_DATA3	0x0
-				MX27_PAD_USBOTG_DATA4__USBOTG_DATA4	0x0
-				MX27_PAD_USBOTG_DATA5__USBOTG_DATA5	0x0
-				MX27_PAD_USBOTG_DATA6__USBOTG_DATA6	0x0
-				MX27_PAD_USBOTG_DATA7__USBOTG_DATA7	0x0
-			>;
-		};
+	pinctrl_usbotg: usbotggrp {
+		fsl,pins = <
+			MX27_PAD_USBOTG_CLK__USBOTG_CLK		0x0
+			MX27_PAD_USBOTG_DIR__USBOTG_DIR		0x0
+			MX27_PAD_USBOTG_NXT__USBOTG_NXT		0x0
+			MX27_PAD_USBOTG_STP__USBOTG_STP		0x0
+			MX27_PAD_USBOTG_DATA0__USBOTG_DATA0	0x0
+			MX27_PAD_USBOTG_DATA1__USBOTG_DATA1	0x0
+			MX27_PAD_USBOTG_DATA2__USBOTG_DATA2	0x0
+			MX27_PAD_USBOTG_DATA3__USBOTG_DATA3	0x0
+			MX27_PAD_USBOTG_DATA4__USBOTG_DATA4	0x0
+			MX27_PAD_USBOTG_DATA5__USBOTG_DATA5	0x0
+			MX27_PAD_USBOTG_DATA6__USBOTG_DATA6	0x0
+			MX27_PAD_USBOTG_DATA7__USBOTG_DATA7	0x0
+		>;
+	};
 
-		pinctrl_usbh2phy: usbh2phygrp {
-			fsl,pins = <
-				MX27_PAD_USBH1_SUSP__GPIO2_22		0x0 /* reset gpio */
-			>;
-		};
+	pinctrl_usbh2phy: usbh2phygrp {
+		fsl,pins = <
+			MX27_PAD_USBH1_SUSP__GPIO2_22		0x0 /* reset gpio */
+		>;
+	};
 
-		pinctrl_usbh2: usbh2grp {
-			fsl,pins = <
-				MX27_PAD_USBH2_CLK__USBH2_CLK		0x0
-				MX27_PAD_USBH2_DIR__USBH2_DIR		0x0
-				MX27_PAD_USBH2_NXT__USBH2_NXT		0x0
-				MX27_PAD_USBH2_STP__USBH2_STP		0x0
-				MX27_PAD_CSPI2_SCLK__USBH2_DATA0	0x0
-				MX27_PAD_CSPI2_MOSI__USBH2_DATA1	0x0
-				MX27_PAD_CSPI2_MISO__USBH2_DATA2	0x0
-				MX27_PAD_CSPI2_SS1__USBH2_DATA3		0x0
-				MX27_PAD_CSPI2_SS2__USBH2_DATA4		0x0
-				MX27_PAD_CSPI1_SS2__USBH2_DATA5		0x0
-				MX27_PAD_CSPI2_SS0__USBH2_DATA6		0x0
-				MX27_PAD_USBH2_DATA7__USBH2_DATA7	0x0
-			>;
-		};
+	pinctrl_usbh2: usbh2grp {
+		fsl,pins = <
+			MX27_PAD_USBH2_CLK__USBH2_CLK		0x0
+			MX27_PAD_USBH2_DIR__USBH2_DIR		0x0
+			MX27_PAD_USBH2_NXT__USBH2_NXT		0x0
+			MX27_PAD_USBH2_STP__USBH2_STP		0x0
+			MX27_PAD_CSPI2_SCLK__USBH2_DATA0	0x0
+			MX27_PAD_CSPI2_MOSI__USBH2_DATA1	0x0
+			MX27_PAD_CSPI2_MISO__USBH2_DATA2	0x0
+			MX27_PAD_CSPI2_SS1__USBH2_DATA3		0x0
+			MX27_PAD_CSPI2_SS2__USBH2_DATA4		0x0
+			MX27_PAD_CSPI1_SS2__USBH2_DATA5		0x0
+			MX27_PAD_CSPI2_SS0__USBH2_DATA6		0x0
+			MX27_PAD_USBH2_DATA7__USBH2_DATA7	0x0
+		>;
 	};
 };
 
diff --git a/arch/arm/boot/dts/nxp/imx/imx27-phytec-phycore-rdk.dts b/arch/arm/boot/dts/nxp/imx/imx27-phytec-phycore-rdk.dts
index 5398e9067e60..d7136c399ae2 100644
--- a/arch/arm/boot/dts/nxp/imx/imx27-phytec-phycore-rdk.dts
+++ b/arch/arm/boot/dts/nxp/imx/imx27-phytec-phycore-rdk.dts
@@ -89,119 +89,117 @@ camgpio: pca9536@41 {
 };
 
 &iomuxc {
-	imx27_phycore_rdk {
-		pinctrl_csien: csiengrp {
-			fsl,pins = <
-				MX27_PAD_USB_OC_B__GPIO2_24 0x0
-			>;
-		};
+	pinctrl_csien: csiengrp {
+		fsl,pins = <
+			MX27_PAD_USB_OC_B__GPIO2_24 0x0
+		>;
+	};
 
-		pinctrl_cspi1cs1: cspi1cs1grp {
-			fsl,pins = <
-				MX27_PAD_CSPI1_SS1__GPIO4_27 0x0
-			>;
-		};
+	pinctrl_cspi1cs1: cspi1cs1grp {
+		fsl,pins = <
+			MX27_PAD_CSPI1_SS1__GPIO4_27 0x0
+		>;
+	};
 
-		pinctrl_imxfb1: imxfbgrp {
-			fsl,pins = <
-				MX27_PAD_LD0__LD0 0x0
-				MX27_PAD_LD1__LD1 0x0
-				MX27_PAD_LD2__LD2 0x0
-				MX27_PAD_LD3__LD3 0x0
-				MX27_PAD_LD4__LD4 0x0
-				MX27_PAD_LD5__LD5 0x0
-				MX27_PAD_LD6__LD6 0x0
-				MX27_PAD_LD7__LD7 0x0
-				MX27_PAD_LD8__LD8 0x0
-				MX27_PAD_LD9__LD9 0x0
-				MX27_PAD_LD10__LD10 0x0
-				MX27_PAD_LD11__LD11 0x0
-				MX27_PAD_LD12__LD12 0x0
-				MX27_PAD_LD13__LD13 0x0
-				MX27_PAD_LD14__LD14 0x0
-				MX27_PAD_LD15__LD15 0x0
-				MX27_PAD_LD16__LD16 0x0
-				MX27_PAD_LD17__LD17 0x0
-				MX27_PAD_CLS__CLS 0x0
-				MX27_PAD_CONTRAST__CONTRAST 0x0
-				MX27_PAD_LSCLK__LSCLK 0x0
-				MX27_PAD_OE_ACD__OE_ACD 0x0
-				MX27_PAD_PS__PS 0x0
-				MX27_PAD_REV__REV 0x0
-				MX27_PAD_SPL_SPR__SPL_SPR 0x0
-				MX27_PAD_HSYNC__HSYNC 0x0
-				MX27_PAD_VSYNC__VSYNC 0x0
-			>;
-		};
+	pinctrl_imxfb1: imxfbgrp {
+		fsl,pins = <
+			MX27_PAD_LD0__LD0 0x0
+			MX27_PAD_LD1__LD1 0x0
+			MX27_PAD_LD2__LD2 0x0
+			MX27_PAD_LD3__LD3 0x0
+			MX27_PAD_LD4__LD4 0x0
+			MX27_PAD_LD5__LD5 0x0
+			MX27_PAD_LD6__LD6 0x0
+			MX27_PAD_LD7__LD7 0x0
+			MX27_PAD_LD8__LD8 0x0
+			MX27_PAD_LD9__LD9 0x0
+			MX27_PAD_LD10__LD10 0x0
+			MX27_PAD_LD11__LD11 0x0
+			MX27_PAD_LD12__LD12 0x0
+			MX27_PAD_LD13__LD13 0x0
+			MX27_PAD_LD14__LD14 0x0
+			MX27_PAD_LD15__LD15 0x0
+			MX27_PAD_LD16__LD16 0x0
+			MX27_PAD_LD17__LD17 0x0
+			MX27_PAD_CLS__CLS 0x0
+			MX27_PAD_CONTRAST__CONTRAST 0x0
+			MX27_PAD_LSCLK__LSCLK 0x0
+			MX27_PAD_OE_ACD__OE_ACD 0x0
+			MX27_PAD_PS__PS 0x0
+			MX27_PAD_REV__REV 0x0
+			MX27_PAD_SPL_SPR__SPL_SPR 0x0
+			MX27_PAD_HSYNC__HSYNC 0x0
+			MX27_PAD_VSYNC__VSYNC 0x0
+		>;
+	};
 
-		pinctrl_i2c1: i2c1grp {
-			/* Add pullup to DATA line */
-			fsl,pins = <
-				MX27_PAD_I2C_DATA__I2C_DATA	0x1
-				MX27_PAD_I2C_CLK__I2C_CLK	0x0
-			>;
-		};
+	pinctrl_i2c1: i2c1grp {
+		/* Add pullup to DATA line */
+		fsl,pins = <
+			MX27_PAD_I2C_DATA__I2C_DATA	0x1
+			MX27_PAD_I2C_CLK__I2C_CLK	0x0
+		>;
+	};
 
-		pinctrl_owire1: owire1grp {
-			fsl,pins = <
-				MX27_PAD_RTCK__OWIRE 0x0
-			>;
-		};
+	pinctrl_owire1: owire1grp {
+		fsl,pins = <
+			MX27_PAD_RTCK__OWIRE 0x0
+		>;
+	};
 
-		pinctrl_sdhc2: sdhc2grp {
-			fsl,pins = <
-				MX27_PAD_SD2_CLK__SD2_CLK 0x0
-				MX27_PAD_SD2_CMD__SD2_CMD 0x0
-				MX27_PAD_SD2_D0__SD2_D0 0x0
-				MX27_PAD_SD2_D1__SD2_D1 0x0
-				MX27_PAD_SD2_D2__SD2_D2 0x0
-				MX27_PAD_SD2_D3__SD2_D3 0x0
-				MX27_PAD_SSI3_FS__GPIO3_28	0x0 /* WP */
-				MX27_PAD_SSI3_RXDAT__GPIO3_29	0x0 /* CD */
-			>;
-		};
+	pinctrl_sdhc2: sdhc2grp {
+		fsl,pins = <
+			MX27_PAD_SD2_CLK__SD2_CLK 0x0
+			MX27_PAD_SD2_CMD__SD2_CMD 0x0
+			MX27_PAD_SD2_D0__SD2_D0 0x0
+			MX27_PAD_SD2_D1__SD2_D1 0x0
+			MX27_PAD_SD2_D2__SD2_D2 0x0
+			MX27_PAD_SD2_D3__SD2_D3 0x0
+			MX27_PAD_SSI3_FS__GPIO3_28	0x0 /* WP */
+			MX27_PAD_SSI3_RXDAT__GPIO3_29	0x0 /* CD */
+		>;
+	};
 
-		pinctrl_uart1: uart1grp {
-			fsl,pins = <
-				MX27_PAD_UART1_TXD__UART1_TXD 0x0
-				MX27_PAD_UART1_RXD__UART1_RXD 0x0
-				MX27_PAD_UART1_CTS__UART1_CTS 0x0
-				MX27_PAD_UART1_RTS__UART1_RTS 0x0
-			>;
-		};
+	pinctrl_uart1: uart1grp {
+		fsl,pins = <
+			MX27_PAD_UART1_TXD__UART1_TXD 0x0
+			MX27_PAD_UART1_RXD__UART1_RXD 0x0
+			MX27_PAD_UART1_CTS__UART1_CTS 0x0
+			MX27_PAD_UART1_RTS__UART1_RTS 0x0
+		>;
+	};
 
-		pinctrl_uart2: uart2grp {
-			fsl,pins = <
-				MX27_PAD_UART2_TXD__UART2_TXD 0x0
-				MX27_PAD_UART2_RXD__UART2_RXD 0x0
-				MX27_PAD_UART2_CTS__UART2_CTS 0x0
-				MX27_PAD_UART2_RTS__UART2_RTS 0x0
-			>;
-		};
+	pinctrl_uart2: uart2grp {
+		fsl,pins = <
+			MX27_PAD_UART2_TXD__UART2_TXD 0x0
+			MX27_PAD_UART2_RXD__UART2_RXD 0x0
+			MX27_PAD_UART2_CTS__UART2_CTS 0x0
+			MX27_PAD_UART2_RTS__UART2_RTS 0x0
+		>;
+	};
 
-		pinctrl_usbh2: usbh2grp {
-			fsl,pins = <
-				MX27_PAD_USBH2_CLK__USBH2_CLK 0x0
-				MX27_PAD_USBH2_DIR__USBH2_DIR 0x0
-				MX27_PAD_USBH2_NXT__USBH2_NXT 0x0
-				MX27_PAD_USBH2_STP__USBH2_STP 0x0
-				MX27_PAD_CSPI2_SCLK__USBH2_DATA0 0x0
-				MX27_PAD_CSPI2_MOSI__USBH2_DATA1 0x0
-				MX27_PAD_CSPI2_MISO__USBH2_DATA2 0x0
-				MX27_PAD_CSPI2_SS1__USBH2_DATA3 0x0
-				MX27_PAD_CSPI2_SS2__USBH2_DATA4 0x0
-				MX27_PAD_CSPI1_SS2__USBH2_DATA5 0x0
-				MX27_PAD_CSPI2_SS0__USBH2_DATA6 0x0
-				MX27_PAD_USBH2_DATA7__USBH2_DATA7 0x0
-			>;
-		};
+	pinctrl_usbh2: usbh2grp {
+		fsl,pins = <
+			MX27_PAD_USBH2_CLK__USBH2_CLK 0x0
+			MX27_PAD_USBH2_DIR__USBH2_DIR 0x0
+			MX27_PAD_USBH2_NXT__USBH2_NXT 0x0
+			MX27_PAD_USBH2_STP__USBH2_STP 0x0
+			MX27_PAD_CSPI2_SCLK__USBH2_DATA0 0x0
+			MX27_PAD_CSPI2_MOSI__USBH2_DATA1 0x0
+			MX27_PAD_CSPI2_MISO__USBH2_DATA2 0x0
+			MX27_PAD_CSPI2_SS1__USBH2_DATA3 0x0
+			MX27_PAD_CSPI2_SS2__USBH2_DATA4 0x0
+			MX27_PAD_CSPI1_SS2__USBH2_DATA5 0x0
+			MX27_PAD_CSPI2_SS0__USBH2_DATA6 0x0
+			MX27_PAD_USBH2_DATA7__USBH2_DATA7 0x0
+		>;
+	};
 
-		pinctrl_weim: weimgrp {
-			fsl,pins = <
-				MX27_PAD_CS4_B__CS4_B		0x0 /* CS4 */
-				MX27_PAD_SD1_D1__GPIO5_19	0x0 /* CAN IRQ */
-			>;
-		};
+	pinctrl_weim: weimgrp {
+		fsl,pins = <
+			MX27_PAD_CS4_B__CS4_B		0x0 /* CS4 */
+			MX27_PAD_SD1_D1__GPIO5_19	0x0 /* CAN IRQ */
+		>;
 	};
 };
 
diff --git a/arch/arm/boot/dts/nxp/imx/imx27-phytec-phycore-som.dtsi b/arch/arm/boot/dts/nxp/imx/imx27-phytec-phycore-som.dtsi
index e958d7286ae9..7d5d24c781b9 100644
--- a/arch/arm/boot/dts/nxp/imx/imx27-phytec-phycore-som.dtsi
+++ b/arch/arm/boot/dts/nxp/imx/imx27-phytec-phycore-som.dtsi
@@ -192,90 +192,88 @@ lm75@4a {
 };
 
 &iomuxc {
-	imx27_phycore_som {
-		pinctrl_cspi1: cspi1grp {
-			fsl,pins = <
-				MX27_PAD_CSPI1_MISO__CSPI1_MISO 0x0
-				MX27_PAD_CSPI1_MOSI__CSPI1_MOSI 0x0
-				MX27_PAD_CSPI1_SCLK__CSPI1_SCLK 0x0
-				MX27_PAD_CSPI1_SS0__GPIO4_28	0x0 /* SPI1 CS0 */
-			>;
-		};
+	pinctrl_cspi1: cspi1grp {
+		fsl,pins = <
+			MX27_PAD_CSPI1_MISO__CSPI1_MISO 0x0
+			MX27_PAD_CSPI1_MOSI__CSPI1_MOSI 0x0
+			MX27_PAD_CSPI1_SCLK__CSPI1_SCLK 0x0
+			MX27_PAD_CSPI1_SS0__GPIO4_28	0x0 /* SPI1 CS0 */
+		>;
+	};
 
-		pinctrl_fec1: fec1grp {
-			fsl,pins = <
-				MX27_PAD_SD3_CMD__FEC_TXD0 0x0
-				MX27_PAD_SD3_CLK__FEC_TXD1 0x0
-				MX27_PAD_ATA_DATA0__FEC_TXD2 0x0
-				MX27_PAD_ATA_DATA1__FEC_TXD3 0x0
-				MX27_PAD_ATA_DATA2__FEC_RX_ER 0x0
-				MX27_PAD_ATA_DATA3__FEC_RXD1 0x0
-				MX27_PAD_ATA_DATA4__FEC_RXD2 0x0
-				MX27_PAD_ATA_DATA5__FEC_RXD3 0x0
-				MX27_PAD_ATA_DATA6__FEC_MDIO 0x0
-				MX27_PAD_ATA_DATA7__FEC_MDC 0x0
-				MX27_PAD_ATA_DATA8__FEC_CRS 0x0
-				MX27_PAD_ATA_DATA9__FEC_TX_CLK 0x0
-				MX27_PAD_ATA_DATA10__FEC_RXD0 0x0
-				MX27_PAD_ATA_DATA11__FEC_RX_DV 0x0
-				MX27_PAD_ATA_DATA12__FEC_RX_CLK 0x0
-				MX27_PAD_ATA_DATA13__FEC_COL 0x0
-				MX27_PAD_ATA_DATA14__FEC_TX_ER 0x0
-				MX27_PAD_ATA_DATA15__FEC_TX_EN 0x0
-				MX27_PAD_SSI3_TXDAT__GPIO3_30	0x0 /* FEC RST */
-			>;
-		};
+	pinctrl_fec1: fec1grp {
+		fsl,pins = <
+			MX27_PAD_SD3_CMD__FEC_TXD0 0x0
+			MX27_PAD_SD3_CLK__FEC_TXD1 0x0
+			MX27_PAD_ATA_DATA0__FEC_TXD2 0x0
+			MX27_PAD_ATA_DATA1__FEC_TXD3 0x0
+			MX27_PAD_ATA_DATA2__FEC_RX_ER 0x0
+			MX27_PAD_ATA_DATA3__FEC_RXD1 0x0
+			MX27_PAD_ATA_DATA4__FEC_RXD2 0x0
+			MX27_PAD_ATA_DATA5__FEC_RXD3 0x0
+			MX27_PAD_ATA_DATA6__FEC_MDIO 0x0
+			MX27_PAD_ATA_DATA7__FEC_MDC 0x0
+			MX27_PAD_ATA_DATA8__FEC_CRS 0x0
+			MX27_PAD_ATA_DATA9__FEC_TX_CLK 0x0
+			MX27_PAD_ATA_DATA10__FEC_RXD0 0x0
+			MX27_PAD_ATA_DATA11__FEC_RX_DV 0x0
+			MX27_PAD_ATA_DATA12__FEC_RX_CLK 0x0
+			MX27_PAD_ATA_DATA13__FEC_COL 0x0
+			MX27_PAD_ATA_DATA14__FEC_TX_ER 0x0
+			MX27_PAD_ATA_DATA15__FEC_TX_EN 0x0
+			MX27_PAD_SSI3_TXDAT__GPIO3_30	0x0 /* FEC RST */
+		>;
+	};
 
-		pinctrl_i2c2: i2c2grp {
-			fsl,pins = <
-				MX27_PAD_I2C2_SDA__I2C2_SDA 0x0
-				MX27_PAD_I2C2_SCL__I2C2_SCL 0x0
-			>;
-		};
+	pinctrl_i2c2: i2c2grp {
+		fsl,pins = <
+			MX27_PAD_I2C2_SDA__I2C2_SDA 0x0
+			MX27_PAD_I2C2_SCL__I2C2_SCL 0x0
+		>;
+	};
 
-		pinctrl_nfc: nfcgrp {
-			fsl,pins = <
-				MX27_PAD_NFRB__NFRB 0x0
-				MX27_PAD_NFCLE__NFCLE 0x0
-				MX27_PAD_NFWP_B__NFWP_B 0x0
-				MX27_PAD_NFCE_B__NFCE_B 0x0
-				MX27_PAD_NFALE__NFALE 0x0
-				MX27_PAD_NFRE_B__NFRE_B 0x0
-				MX27_PAD_NFWE_B__NFWE_B 0x0
-			>;
-		};
+	pinctrl_nfc: nfcgrp {
+		fsl,pins = <
+			MX27_PAD_NFRB__NFRB 0x0
+			MX27_PAD_NFCLE__NFCLE 0x0
+			MX27_PAD_NFWP_B__NFWP_B 0x0
+			MX27_PAD_NFCE_B__NFCE_B 0x0
+			MX27_PAD_NFALE__NFALE 0x0
+			MX27_PAD_NFRE_B__NFRE_B 0x0
+			MX27_PAD_NFWE_B__NFWE_B 0x0
+		>;
+	};
 
-		pinctrl_pmic: pmicgrp {
-			fsl,pins = <
-				MX27_PAD_USB_PWR__GPIO2_23	0x0 /* PMIC IRQ */
-			>;
-		};
+	pinctrl_pmic: pmicgrp {
+		fsl,pins = <
+			MX27_PAD_USB_PWR__GPIO2_23	0x0 /* PMIC IRQ */
+		>;
+	};
 
-		pinctrl_ssi1: ssi1grp {
-			fsl,pins = <
-				MX27_PAD_SSI1_FS__SSI1_FS 0x0
-				MX27_PAD_SSI1_RXDAT__SSI1_RXDAT 0x0
-				MX27_PAD_SSI1_TXDAT__SSI1_TXDAT 0x0
-				MX27_PAD_SSI1_CLK__SSI1_CLK 0x0
-			>;
-		};
+	pinctrl_ssi1: ssi1grp {
+		fsl,pins = <
+			MX27_PAD_SSI1_FS__SSI1_FS 0x0
+			MX27_PAD_SSI1_RXDAT__SSI1_RXDAT 0x0
+			MX27_PAD_SSI1_TXDAT__SSI1_TXDAT 0x0
+			MX27_PAD_SSI1_CLK__SSI1_CLK 0x0
+		>;
+	};
 
-		pinctrl_usbotg: usbotggrp {
-			fsl,pins = <
-				MX27_PAD_USBOTG_CLK__USBOTG_CLK 0x0
-				MX27_PAD_USBOTG_DIR__USBOTG_DIR 0x0
-				MX27_PAD_USBOTG_NXT__USBOTG_NXT 0x0
-				MX27_PAD_USBOTG_STP__USBOTG_STP 0x0
-				MX27_PAD_USBOTG_DATA0__USBOTG_DATA0 0x0
-				MX27_PAD_USBOTG_DATA1__USBOTG_DATA1 0x0
-				MX27_PAD_USBOTG_DATA2__USBOTG_DATA2 0x0
-				MX27_PAD_USBOTG_DATA3__USBOTG_DATA3 0x0
-				MX27_PAD_USBOTG_DATA4__USBOTG_DATA4 0x0
-				MX27_PAD_USBOTG_DATA5__USBOTG_DATA5 0x0
-				MX27_PAD_USBOTG_DATA6__USBOTG_DATA6 0x0
-				MX27_PAD_USBOTG_DATA7__USBOTG_DATA7 0x0
-			>;
-		};
+	pinctrl_usbotg: usbotggrp {
+		fsl,pins = <
+			MX27_PAD_USBOTG_CLK__USBOTG_CLK 0x0
+			MX27_PAD_USBOTG_DIR__USBOTG_DIR 0x0
+			MX27_PAD_USBOTG_NXT__USBOTG_NXT 0x0
+			MX27_PAD_USBOTG_STP__USBOTG_STP 0x0
+			MX27_PAD_USBOTG_DATA0__USBOTG_DATA0 0x0
+			MX27_PAD_USBOTG_DATA1__USBOTG_DATA1 0x0
+			MX27_PAD_USBOTG_DATA2__USBOTG_DATA2 0x0
+			MX27_PAD_USBOTG_DATA3__USBOTG_DATA3 0x0
+			MX27_PAD_USBOTG_DATA4__USBOTG_DATA4 0x0
+			MX27_PAD_USBOTG_DATA5__USBOTG_DATA5 0x0
+			MX27_PAD_USBOTG_DATA6__USBOTG_DATA6 0x0
+			MX27_PAD_USBOTG_DATA7__USBOTG_DATA7 0x0
+		>;
 	};
 };