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arm64: dts: imx8mp-phyboard-pollux: Add HDMI support

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The PHYTEC phyBOARD Pollux comes with a HDMI port on the base board.
Add the required device-tree nodes to enable support for it, including
both the video and the audio paths.

Signed-off-by: Paul Kocialkowski <paulk@sys-base.io>
Signed-off-by: Frank Li <Frank.Li@nxp.com>
This commit is contained in:
Paul Kocialkowski 2026-04-02 20:36:26 +02:00 committed by Frank Li
parent eb27f9b9a4
commit e556f564a0
1 changed files with 62 additions and 0 deletions
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62
arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts
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@ -38,6 +38,18 @@ fan0: fan {
#cooling-cells = <2>;
};
hdmi-connector {
compatible = "hdmi-connector";
label = "hdmi";
type = "a";
port {
hdmi_connector_in: endpoint {
remote-endpoint = <&hdmi_tx_out>;
};
};
};
panel_lvds1: panel-lvds1 {
/* compatible panel in overlay */
backlight = <&backlight_lvds1>;
@ -126,6 +138,13 @@ reg_vcc_1v8_exp_con: regulator-vcc-1v8 {
regulator-name = "VCC_1V8_EXP_CON";
};
sound-hdmi {
compatible = "fsl,imx-audio-hdmi";
model = "audio-hdmi";
audio-cpu = <&aud2htx>;
hdmi-out;
};
thermal-zones {
soc-thermal {
trips {
@ -146,6 +165,10 @@ map1 {
};
};
&aud2htx {
status = "okay";
};
/* TPM */
&ecspi1 {
#address-cells = <1>;
@ -201,6 +224,32 @@ &flexcan2 {
status = "okay";
};
&hdmi_pai {
status = "okay";
};
&hdmi_pvi {
status = "okay";
};
&hdmi_tx {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hdmi>;
status = "okay";
ports {
port@1 {
hdmi_tx_out: endpoint {
remote-endpoint = <&hdmi_connector_in>;
};
};
};
};
&hdmi_tx_phy {
status = "okay";
};
&i2c2 {
clock-frequency = <400000>;
pinctrl-names = "default", "gpio";
@ -244,6 +293,10 @@ &i2c3 {
scl-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
};
&lcdif3 {
status = "okay";
};
&ldb_lvds_ch1 {
remote-endpoint = <&panel1_in>;
};
@ -444,6 +497,15 @@ MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21 0x154
>;
};
pinctrl_hdmi: hdmigrp {
fsl,pins = <
MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL 0x1c3
MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA 0x1c3
MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD 0x19
MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC 0x19
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2