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ARM: dts: stm32: phycore-stm32mp15: Disable optional SoM peripherals

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Following peripherals are optional on phyCORE-STM32MP15x following
PHYTEC standard SoM variants: external RTC, EEPROM, SPI NOR.
Also NAND (fmc) can be populated instead of eMMC (sdmmc2).

So disable those peripherals on SoM dtsi file and enable them on board
dts file.
Additionally, enable by default the "DTS" SoC IP on common SoM dtsi file
as it is not an optional IP in STM32MP15x SoC.

Signed-off-by: Christophe Parant <c.parant@phytec.fr>
Link: https://lore.kernel.org/r/20251210101611.27008-10-c.parant@phytec.fr
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
This commit is contained in:
Christophe Parant 2025-12-10 11:16:09 +01:00 committed by Alexandre Torgue
parent d07f9c56d0
commit e4c9cc7388
2 changed files with 8 additions and 9 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
arch/arm/boot/dts/st/stm32mp157c-phyboard-sargas-rdk.dts
View File

@ -22,14 +22,6 @@ &cryp1 {
status = "okay";
};
&dts {
status = "okay";
};
&fmc {
status = "disabled";
};
&gpu {
status = "okay";
};

9
arch/arm/boot/dts/st/stm32mp15xx-phycore-som.dtsi
View File

@ -265,11 +265,13 @@ i2c4_eeprom: eeprom@50 {
compatible = "microchip,24c32",
"atmel,24c32";
reg = <0x50>;
status = "disabled";
};
i2c4_rtc: rtc@52 {
compatible = "microcrystal,rv3028";
reg = <0x52>;
status = "disabled";
};
};
@ -307,7 +309,7 @@ &qspi_bk1_sleep_pins_a
&qspi_cs1_sleep_pins_a>;
reg = <0x58003000 0x1000>,
<0x70000000 0x1000000>;
status = "okay";
status = "disabled";
flash0: flash@0 {
compatible = "winbond,w25q128", "jedec,spi-nor";
@ -328,6 +330,10 @@ &rtc {
status = "okay";
};
&dts {
status = "okay";
};
&sdmmc2 {
pinctrl-names = "default", "opendrain", "sleep";
pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_e>;
@ -341,4 +347,5 @@ &sdmmc2 {
vmmc-supply = <&v3v3>;
vqmmc-supply = <&v3v3>;
mmc-ddr-3_3v;
status = "disabled";
};