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dt-bindings: PCI: fsl,imx6q-pcie: Add reset GPIO in Root Port node
Update fsl,imx6q-pcie.yaml to include the standard reset-gpios property for the Root Port node. The reset-gpios property is already defined in pci-bus-common.yaml for PERST#, so use it instead of the local reset-gpio property. Keep the existing reset-gpio property in the bridge node for backward compatibility, but mark it as deprecated. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Manivannan Sadhasivam <mani@kernel.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Link: https://patch.msgid.link/20260422093549.407022-2-sherry.sun@nxp.com
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@ -66,16 +66,34 @@ properties:
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- const: dma
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reset-gpio:
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deprecated: true
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description: Should specify the GPIO for controlling the PCI bus device
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reset signal. It's not polarity aware and defaults to active-low reset
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sequence (L=reset state, H=operation state) (optional required).
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This property is deprecated, instead of referencing this property from the
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host bridge node, use the reset-gpios property from the root port node.
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reset-gpio-active-high:
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deprecated: true
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description: If present then the reset sequence using the GPIO
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specified in the "reset-gpio" property is reversed (H=reset state,
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L=operation state) (optional required).
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This property is deprecated along with the reset-gpio property above, use
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the reset-gpios property from the root port node.
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type: boolean
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pcie@0:
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description:
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Describe the i.MX6 PCIe Root Port.
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type: object
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$ref: /schemas/pci/pci-pci-bridge.yaml#
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properties:
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reg:
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maxItems: 1
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unevaluatedProperties: false
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required:
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- compatible
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- reg
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@ -236,6 +254,7 @@ unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/clock/imx6qdl-clock.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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pcie: pcie@1ffc000 {
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@ -262,5 +281,18 @@ examples:
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<&clks IMX6QDL_CLK_LVDS1_GATE>,
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<&clks IMX6QDL_CLK_PCIE_REF_125M>;
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clock-names = "pcie", "pcie_bus", "pcie_phy";
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pcie_port0: pcie@0 {
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compatible = "pciclass,0604";
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device_type = "pci";
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reg = <0x0 0x0 0x0 0x0 0x0>;
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bus-range = <0x01 0xff>;
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#address-cells = <3>;
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#size-cells = <2>;
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ranges;
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reset-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>;
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};
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};
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...
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