dt-bindings: PCI: fsl,imx6q-pcie: Add reset GPIO in Root Port node

Update fsl,imx6q-pcie.yaml to include the standard reset-gpios property for
the Root Port node.

The reset-gpios property is already defined in pci-bus-common.yaml for
PERST#, so use it instead of the local reset-gpio property. Keep the
existing reset-gpio property in the bridge node for backward compatibility,
but mark it as deprecated.

Signed-off-by: Sherry Sun <sherry.sun@nxp.com>
Signed-off-by: Manivannan Sadhasivam <mani@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://patch.msgid.link/20260422093549.407022-2-sherry.sun@nxp.com
This commit is contained in:
Sherry Sun 2026-04-22 17:35:38 +08:00 committed by Bjorn Helgaas
parent aad953fb4e
commit e3d334156b

View File

@ -66,16 +66,34 @@ properties:
- const: dma
reset-gpio:
deprecated: true
description: Should specify the GPIO for controlling the PCI bus device
reset signal. It's not polarity aware and defaults to active-low reset
sequence (L=reset state, H=operation state) (optional required).
This property is deprecated, instead of referencing this property from the
host bridge node, use the reset-gpios property from the root port node.
reset-gpio-active-high:
deprecated: true
description: If present then the reset sequence using the GPIO
specified in the "reset-gpio" property is reversed (H=reset state,
L=operation state) (optional required).
This property is deprecated along with the reset-gpio property above, use
the reset-gpios property from the root port node.
type: boolean
pcie@0:
description:
Describe the i.MX6 PCIe Root Port.
type: object
$ref: /schemas/pci/pci-pci-bridge.yaml#
properties:
reg:
maxItems: 1
unevaluatedProperties: false
required:
- compatible
- reg
@ -236,6 +254,7 @@ unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/imx6qdl-clock.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
pcie: pcie@1ffc000 {
@ -262,5 +281,18 @@ examples:
<&clks IMX6QDL_CLK_LVDS1_GATE>,
<&clks IMX6QDL_CLK_PCIE_REF_125M>;
clock-names = "pcie", "pcie_bus", "pcie_phy";
pcie_port0: pcie@0 {
compatible = "pciclass,0604";
device_type = "pci";
reg = <0x0 0x0 0x0 0x0 0x0>;
bus-range = <0x01 0xff>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
reset-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>;
};
};
...