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PCI: imx6: Fix IMX6SX_GPR12_PCIE_TEST_POWERDOWN handling
The IMX6SX_GPR12_PCIE_TEST_POWERDOWN bit does not control the PCIe
reference clock on i.MX6SX. Instead, it is part of i.MX6SX PCIe core
reset sequence.
Move the IMX6SX_GPR12_PCIE_TEST_POWERDOWN assertion/deassertion into
the core reset functions to properly reflect its purpose. Remove the
.enable_ref_clk() callback for i.MX6SX since it was incorrectly
manipulating this bit.
Fixes: e3c06cd063 ("PCI: imx6: Add initial imx6sx support")
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Signed-off-by: Manivannan Sadhasivam <mani@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Cc: stable@vger.kernel.org
Link: https://patch.msgid.link/20260319090844.444987-1-hongxing.zhu@nxp.com
This commit is contained in:
parent
254f49634e
commit
aad953fb4e
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@ -665,14 +665,6 @@ static int imx_pcie_attach_pd(struct device *dev)
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return 0;
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}
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static int imx6sx_pcie_enable_ref_clk(struct imx_pcie *imx_pcie, bool enable)
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{
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regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12,
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IMX6SX_GPR12_PCIE_TEST_POWERDOWN,
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enable ? 0 : IMX6SX_GPR12_PCIE_TEST_POWERDOWN);
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return 0;
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}
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static int imx6q_pcie_enable_ref_clk(struct imx_pcie *imx_pcie, bool enable)
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{
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if (enable) {
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@ -786,6 +778,9 @@ static int imx6sx_pcie_core_reset(struct imx_pcie *imx_pcie, bool assert)
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if (assert)
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regmap_set_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12,
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IMX6SX_GPR12_PCIE_TEST_POWERDOWN);
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else
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regmap_clear_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12,
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IMX6SX_GPR12_PCIE_TEST_POWERDOWN);
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/* Force PCIe PHY reset */
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regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR5, IMX6SX_GPR5_PCIE_BTNRST_RESET,
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@ -1877,7 +1872,6 @@ static const struct imx_pcie_drvdata drvdata[] = {
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.mode_off[0] = IOMUXC_GPR12,
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.mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
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.init_phy = imx6sx_pcie_init_phy,
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.enable_ref_clk = imx6sx_pcie_enable_ref_clk,
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.core_reset = imx6sx_pcie_core_reset,
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.ops = &imx_pcie_host_ops,
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},
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