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igc: refactor TXDCTL macros to use FIELD_PREP and GEN_MASK

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Refactor TXDCTL macro handling to use FIELD_PREP and GENMASK macros.
This prepares the code for adding a new TXDCTL priority field in an
upcoming patch.

Verified that the macro values remain unchanged before and after
refactoring.

Reviewed-by: Simon Horman <horms@kernel.org>
Signed-off-by: Faizal Rahim <faizal.abdul.rahim@linux.intel.com>
Tested-by: Mor Bar-Gabay <morx.bar.gabay@intel.com>
Signed-off-by: Tony Nguyen <anthony.l.nguyen@intel.com>
This commit is contained in:
Faizal Rahim 2025-05-19 03:19:07 -04:00 committed by Tony Nguyen
parent 4cdb4ef8a9
commit e35ba6d3c6
2 changed files with 12 additions and 9 deletions
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15
drivers/net/ethernet/intel/igc/igc.h
View File

@ -493,13 +493,18 @@ static inline u32 igc_rss_type(const union igc_adv_rx_desc *rx_desc)
/* Receive Software Flush */
#define IGC_RXDCTL_SWFLUSH 0x04000000
#define IGC_TXDCTL_PTHRESH 8
#define IGC_TXDCTL_HTHRESH 1
#define IGC_TXDCTL_WTHRESH 16
#define IGC_TXDCTL_PTHRESH_MASK GENMASK(4, 0)
#define IGC_TXDCTL_HTHRESH_MASK GENMASK(12, 8)
#define IGC_TXDCTL_WTHRESH_MASK GENMASK(20, 16)
#define IGC_TXDCTL_QUEUE_ENABLE_MASK GENMASK(25, 25)
#define IGC_TXDCTL_SWFLUSH_MASK GENMASK(26, 26)
#define IGC_TXDCTL_PTHRESH(x) FIELD_PREP(IGC_TXDCTL_PTHRESH_MASK, (x))
#define IGC_TXDCTL_HTHRESH(x) FIELD_PREP(IGC_TXDCTL_HTHRESH_MASK, (x))
#define IGC_TXDCTL_WTHRESH(x) FIELD_PREP(IGC_TXDCTL_WTHRESH_MASK, (x))
/* Ena specific Tx Queue */
#define IGC_TXDCTL_QUEUE_ENABLE 0x02000000
#define IGC_TXDCTL_QUEUE_ENABLE FIELD_PREP(IGC_TXDCTL_QUEUE_ENABLE_MASK, 1)
/* Transmit Software Flush */
#define IGC_TXDCTL_SWFLUSH 0x04000000
#define IGC_TXDCTL_SWFLUSH FIELD_PREP(IGC_TXDCTL_SWFLUSH_MASK, 1)
#define IGC_RX_DMA_ATTR \
(DMA_ATTR_SKIP_CPU_SYNC | DMA_ATTR_WEAK_ORDERING)

6
drivers/net/ethernet/intel/igc/igc_main.c
View File

@ -749,11 +749,9 @@ static void igc_configure_tx_ring(struct igc_adapter *adapter,
wr32(IGC_TDH(reg_idx), 0);
writel(0, ring->tail);
txdctl |= IGC_TXDCTL_PTHRESH;
txdctl |= IGC_TXDCTL_HTHRESH << 8;
txdctl |= IGC_TXDCTL_WTHRESH << 16;
txdctl |= IGC_TXDCTL_PTHRESH(8) | IGC_TXDCTL_HTHRESH(1) |
IGC_TXDCTL_WTHRESH(16) | IGC_TXDCTL_QUEUE_ENABLE;
txdctl |= IGC_TXDCTL_QUEUE_ENABLE;
wr32(IGC_TXDCTL(reg_idx), txdctl);
}