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igc: add DCTL prefix to related macros

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Rename macros to use the DCTL prefix for consistency with existing
macros that reference the same register. This prepares for an upcoming
patch that adds new fields to TXDCTL.

Reviewed-by: Simon Horman <horms@kernel.org>
Signed-off-by: Faizal Rahim <faizal.abdul.rahim@linux.intel.com>
Tested-by: Mor Bar-Gabay <morx.bar.gabay@intel.com>
Signed-off-by: Tony Nguyen <anthony.l.nguyen@intel.com>
This commit is contained in:
Faizal Rahim 2025-05-19 03:19:06 -04:00 committed by Tony Nguyen
parent fe4d9e8394
commit 4cdb4ef8a9
2 changed files with 12 additions and 12 deletions
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12
drivers/net/ethernet/intel/igc/igc.h
View File

@ -485,17 +485,17 @@ static inline u32 igc_rss_type(const union igc_adv_rx_desc *rx_desc)
* descriptors until either it has this many to write back, or the
* ITR timer expires.
*/
#define IGC_RX_PTHRESH 8
#define IGC_RX_HTHRESH 8
#define IGC_RX_WTHRESH 4
#define IGC_RXDCTL_PTHRESH 8
#define IGC_RXDCTL_HTHRESH 8
#define IGC_RXDCTL_WTHRESH 4
/* Ena specific Rx Queue */
#define IGC_RXDCTL_QUEUE_ENABLE 0x02000000
/* Receive Software Flush */
#define IGC_RXDCTL_SWFLUSH 0x04000000
#define IGC_TX_PTHRESH 8
#define IGC_TX_HTHRESH 1
#define IGC_TX_WTHRESH 16
#define IGC_TXDCTL_PTHRESH 8
#define IGC_TXDCTL_HTHRESH 1
#define IGC_TXDCTL_WTHRESH 16
/* Ena specific Tx Queue */
#define IGC_TXDCTL_QUEUE_ENABLE 0x02000000
/* Transmit Software Flush */

12
drivers/net/ethernet/intel/igc/igc_main.c
View File

@ -683,9 +683,9 @@ static void igc_configure_rx_ring(struct igc_adapter *adapter,
wr32(IGC_SRRCTL(reg_idx), srrctl);
rxdctl |= IGC_RX_PTHRESH;
rxdctl |= IGC_RX_HTHRESH << 8;
rxdctl |= IGC_RX_WTHRESH << 16;
rxdctl |= IGC_RXDCTL_PTHRESH;
rxdctl |= IGC_RXDCTL_HTHRESH << 8;
rxdctl |= IGC_RXDCTL_WTHRESH << 16;
/* initialize rx_buffer_info */
memset(ring->rx_buffer_info, 0,
@ -749,9 +749,9 @@ static void igc_configure_tx_ring(struct igc_adapter *adapter,
wr32(IGC_TDH(reg_idx), 0);
writel(0, ring->tail);
txdctl |= IGC_TX_PTHRESH;
txdctl |= IGC_TX_HTHRESH << 8;
txdctl |= IGC_TX_WTHRESH << 16;
txdctl |= IGC_TXDCTL_PTHRESH;
txdctl |= IGC_TXDCTL_HTHRESH << 8;
txdctl |= IGC_TXDCTL_WTHRESH << 16;
txdctl |= IGC_TXDCTL_QUEUE_ENABLE;
wr32(IGC_TXDCTL(reg_idx), txdctl);