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arm64: versal-net: Switch Versal NET to firmware clock interface
Switch Versal NET from using fixed clocks to the firmware-based clock interface (versal-net-clk.dtsi). This enables proper clock management through the platform firmware instead of relying on static fixed-clock definitions. Add DT macro headers for Versal NET and base Versal clocks, power domains and mandatory resets required by the clock dtsi. Link: https://patch.msgid.link/77e6234f6cef3f78fb1c6c97142fa8055982e14e.1783516336.git.michal.simek@amd.com Signed-off-by: Michal Simek <michal.simek@amd.com>
This commit is contained in:
Michal Simek
parent
7dc3776a5f
commit
e1ab33a3b2
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@ -1,72 +1,52 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* dts file for Xilinx Versal NET fixed clock
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* dts file for Xilinx Versal NET with PM
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*
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* (C) Copyright 2022, Xilinx, Inc.
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* (C) Copyright 2022 - 2025, Advanced Micro Devices, Inc.
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* Copyright (C) 2022, Xilinx, Inc.
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* Copyright (C) 2022 - 2026, Advanced Micro Devices, Inc.
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*
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* Michal Simek <michal.simek@amd.com>
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*/
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include "xlnx-versal-net-clk.h"
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#include "xlnx-versal-net-power.h"
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#include "xlnx-versal-net-resets.h"
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/ {
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clk60: clk60 {
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ref_clk: clock-33333333 {
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compatible = "fixed-clock";
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bootph-all;
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clock-frequency = <33333333>;
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clock-output-names = "ref_clk";
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#clock-cells = <0>;
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clock-frequency = <60000000>;
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};
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clk100: clk100 {
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rtc_clk: clock-32768 {
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compatible = "fixed-clock";
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bootph-all;
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clock-frequency = <32768>;
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clock-output-names = "rtc_clk";
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#clock-cells = <0>;
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clock-frequency = <100000000>;
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};
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clk125: clk125 {
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compatible = "fixed-clock";
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can0_clk: can0-clk {
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compatible = "fixed-factor-clock";
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clocks = <&versal_net_clk CAN0_REF_2X>;
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clock-div = <2>;
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clock-mult = <1>;
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clock-output-names = "can0_clk";
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#clock-cells = <0>;
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clock-frequency = <125000000>;
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};
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clk150: clk150 {
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compatible = "fixed-clock";
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can1_clk: can1-clk {
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compatible = "fixed-factor-clock";
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clocks = <&versal_net_clk CAN1_REF_2X>;
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clock-div = <2>;
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clock-mult = <1>;
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clock-output-names = "can1_clk";
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#clock-cells = <0>;
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clock-frequency = <150000000>;
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};
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clk160: clk160 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <160000000>;
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};
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clk200: clk200 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <200000000>;
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};
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clk250: clk250 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <250000000>;
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};
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clk300: clk300 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <300000000>;
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};
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clk450: clk450 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <450000000>;
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};
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clk1200: clk1200 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <1200000000>;
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};
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firmware {
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@ -74,158 +54,325 @@ versal_net_firmware: versal-net-firmware {
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compatible = "xlnx,versal-net-firmware", "xlnx,versal-firmware";
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bootph-all;
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method = "smc";
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#power-domain-cells = <1>;
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versal_net_reset: reset-controller {
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compatible = "xlnx,versal-net-reset";
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#reset-cells = <1>;
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};
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versal_net_clk: clock-controller {
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compatible = "xlnx,versal-net-clk", "xlnx,versal-clk";
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bootph-all;
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clocks = <&ref_clk>, <&ref_clk>, <&ref_clk>;
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clock-names = "ref", "pl_alt_ref", "alt_ref";
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#clock-cells = <1>;
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};
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versal_net_power: power-management {
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compatible = "xlnx,zynqmp-power";
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mboxes = <&ipi_mailbox_pmu1 0>,
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<&ipi_mailbox_pmu1 1>;
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mbox-names = "tx", "rx";
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};
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};
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};
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zynqmp-ipi {
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compatible = "xlnx,zynqmp-ipi-mailbox";
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
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xlnx,ipi-id = <2>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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ipi_mailbox_pmu1: mailbox@eb3f0440 {
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compatible = "xlnx,zynqmp-ipi-dest-mailbox";
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reg = <0 0xeb3f0440 0 0x20>,
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<0 0xeb3f0460 0 0x20>,
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<0 0xeb3f0280 0 0x20>,
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<0 0xeb3f02a0 0 0x20>;
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reg-names = "local_request_region", "local_response_region",
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"remote_request_region", "remote_response_region";
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#mbox-cells = <1>;
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xlnx,ipi-id = <1>;
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};
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};
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};
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&adma0 {
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clocks = <&clk450>, <&clk450>;
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&cpu0 {
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clocks = <&versal_net_clk ACPU_0>;
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};
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&adma1 {
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clocks = <&clk450>, <&clk450>;
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&cpu100 {
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clocks = <&versal_net_clk ACPU_0>;
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};
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&adma2 {
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clocks = <&clk450>, <&clk450>;
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&cpu200 {
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clocks = <&versal_net_clk ACPU_0>;
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};
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&adma3 {
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clocks = <&clk450>, <&clk450>;
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&cpu300 {
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clocks = <&versal_net_clk ACPU_0>;
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};
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&adma4 {
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clocks = <&clk450>, <&clk450>;
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&cpu10000 {
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clocks = <&versal_net_clk ACPU_1>;
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};
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&adma5 {
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clocks = <&clk450>, <&clk450>;
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&cpu10100 {
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clocks = <&versal_net_clk ACPU_1>;
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};
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&adma6 {
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clocks = <&clk450>, <&clk450>;
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&cpu10200 {
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clocks = <&versal_net_clk ACPU_1>;
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};
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&adma7 {
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clocks = <&clk450>, <&clk450>;
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&cpu10300 {
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clocks = <&versal_net_clk ACPU_1>;
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};
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&cpu20000 {
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clocks = <&versal_net_clk ACPU_2>;
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};
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&cpu20100 {
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clocks = <&versal_net_clk ACPU_2>;
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};
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&cpu20200 {
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clocks = <&versal_net_clk ACPU_2>;
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};
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&cpu20300 {
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clocks = <&versal_net_clk ACPU_2>;
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};
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&cpu30000 {
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clocks = <&versal_net_clk ACPU_3>;
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};
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&cpu30100 {
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clocks = <&versal_net_clk ACPU_3>;
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};
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&cpu30200 {
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clocks = <&versal_net_clk ACPU_3>;
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};
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&cpu30300 {
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clocks = <&versal_net_clk ACPU_3>;
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};
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&can0 {
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clocks = <&clk160>, <&clk160>;
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clocks = <&can0_clk>, <&versal_net_clk LPD_LSBUS>;
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power-domains = <&versal_net_firmware PM_DEV_CAN_FD_0>;
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};
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&can1 {
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clocks = <&clk160>, <&clk160>;
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clocks = <&can1_clk>, <&versal_net_clk LPD_LSBUS>;
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power-domains = <&versal_net_firmware PM_DEV_CAN_FD_1>;
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};
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&gem0 {
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clocks = <&clk125>, <&clk125>, <&clk125>, <&clk125>, <&clk250>;
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clocks = <&versal_net_clk LPD_LSBUS>,
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<&versal_net_clk GEM0_REF>, <&versal_net_clk GEM0_TX>,
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<&versal_net_clk GEM0_RX>, <&versal_net_clk GEM_TSU>;
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power-domains = <&versal_net_firmware PM_DEV_GEM_0>;
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};
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&gem1 {
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clocks = <&clk125>, <&clk125>, <&clk125>, <&clk125>, <&clk250>;
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clocks = <&versal_net_clk LPD_LSBUS>,
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<&versal_net_clk GEM1_REF>, <&versal_net_clk GEM1_TX>,
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<&versal_net_clk GEM1_RX>, <&versal_net_clk GEM_TSU>;
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power-domains = <&versal_net_firmware PM_DEV_GEM_1>;
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};
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&gpio0 {
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clocks = <&clk100>;
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clocks = <&versal_net_clk LPD_LSBUS>;
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power-domains = <&versal_net_firmware PM_DEV_GPIO>;
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};
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&gpio1 {
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clocks = <&clk100>;
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clocks = <&versal_net_clk PMC_LSBUS_REF>;
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power-domains = <&versal_net_firmware PM_DEV_GPIO_PMC>;
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};
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&i2c0 {
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clocks = <&clk100>;
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clocks = <&versal_net_clk I3C0_REF>;
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power-domains = <&versal_net_firmware PM_DEV_I2C_0>;
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};
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&i2c1 {
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clocks = <&clk100>;
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clocks = <&versal_net_clk I3C1_REF>;
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power-domains = <&versal_net_firmware PM_DEV_I2C_1>;
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};
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&i3c0 {
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clocks = <&clk100>;
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clocks = <&versal_net_clk I3C0_REF>;
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power-domains = <&versal_net_firmware PM_DEV_I2C_0>;
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};
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&i3c1 {
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clocks = <&clk100>;
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clocks = <&versal_net_clk I3C1_REF>;
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power-domains = <&versal_net_firmware PM_DEV_I2C_1>;
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};
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&ospi {
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clocks = <&clk200>;
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&adma0 {
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clocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>;
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power-domains = <&versal_net_firmware PM_DEV_ADMA_0>;
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};
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&adma1 {
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clocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>;
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power-domains = <&versal_net_firmware PM_DEV_ADMA_1>;
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};
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&adma2 {
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clocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>;
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power-domains = <&versal_net_firmware PM_DEV_ADMA_2>;
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};
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&adma3 {
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clocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>;
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power-domains = <&versal_net_firmware PM_DEV_ADMA_3>;
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};
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&adma4 {
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clocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>;
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power-domains = <&versal_net_firmware PM_DEV_ADMA_4>;
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};
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&adma5 {
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clocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>;
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power-domains = <&versal_net_firmware PM_DEV_ADMA_5>;
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};
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&adma6 {
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clocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>;
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power-domains = <&versal_net_firmware PM_DEV_ADMA_6>;
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};
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&adma7 {
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clocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>;
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power-domains = <&versal_net_firmware PM_DEV_ADMA_7>;
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};
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&qspi {
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clocks = <&clk300>, <&clk300>;
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clocks = <&versal_net_clk QSPI_REF>, <&versal_net_clk LPD_LSBUS>;
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power-domains = <&versal_net_firmware PM_DEV_QSPI>;
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};
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&ospi {
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clocks = <&versal_net_clk OSPI_REF>;
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power-domains = <&versal_net_firmware PM_DEV_OSPI>;
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};
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&rtc {
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/* Nothing */
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};
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&sdhci0 {
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clocks = <&clk200>, <&clk200>, <&clk1200>;
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};
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&sdhci1 {
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clocks = <&clk200>, <&clk200>, <&clk1200>;
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clocks = <&rtc_clk>;
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clock-names = "rtc";
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power-domains = <&versal_net_firmware PM_DEV_RTC>;
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};
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&serial0 {
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clocks = <&clk100>, <&clk100>;
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clocks = <&versal_net_clk UART0_REF>, <&versal_net_clk LPD_LSBUS>;
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power-domains = <&versal_net_firmware PM_DEV_UART_0>;
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};
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&serial1 {
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clocks = <&clk100>, <&clk100>;
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clocks = <&versal_net_clk UART1_REF>, <&versal_net_clk LPD_LSBUS>;
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power-domains = <&versal_net_firmware PM_DEV_UART_1>;
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};
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&sdhci0 {
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clocks = <&versal_net_clk SDIO0_REF>, <&versal_net_clk LPD_LSBUS>,
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<&versal_net_clk SD_DLL_REF>;
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power-domains = <&versal_net_firmware PM_DEV_SDIO_0>;
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};
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&sdhci1 {
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clocks = <&versal_net_clk SDIO1_REF>, <&versal_net_clk LPD_LSBUS>,
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<&versal_net_clk SD_DLL_REF>;
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power-domains = <&versal_net_firmware PM_DEV_SDIO_1>;
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};
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&spi0 {
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clocks = <&clk200>, <&clk200>;
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clocks = <&versal_net_clk SPI0_REF>, <&versal_net_clk LPD_LSBUS>;
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power-domains = <&versal_net_firmware PM_DEV_SPI_0>;
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};
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&spi1 {
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clocks = <&clk200>, <&clk200>;
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clocks = <&versal_net_clk SPI1_REF>, <&versal_net_clk LPD_LSBUS>;
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power-domains = <&versal_net_firmware PM_DEV_SPI_1>;
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};
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&ttc0 {
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clocks = <&clk150>;
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clocks = <&versal_net_clk TTC0>;
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power-domains = <&versal_net_firmware PM_DEV_TTC_0>;
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};
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&ttc1 {
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clocks = <&versal_net_clk TTC1>;
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power-domains = <&versal_net_firmware PM_DEV_TTC_1>;
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};
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&ttc2 {
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clocks = <&versal_net_clk TTC2>;
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power-domains = <&versal_net_firmware PM_DEV_TTC_2>;
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};
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&ttc3 {
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clocks = <&versal_net_clk TTC3>;
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power-domains = <&versal_net_firmware PM_DEV_TTC_3>;
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};
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&usb0 {
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clocks = <&clk60>, <&clk60>;
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clocks = <&versal_net_clk USB0_BUS_REF>, <&versal_net_clk USB0_BUS_REF>;
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power-domains = <&versal_net_firmware PM_DEV_USB_0>;
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resets = <&versal_net_reset VERSAL_RST_USB_0>;
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};
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&dwc3_0 {
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clocks = <&clk60>;
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clocks = <&versal_net_clk USB0_BUS_REF>;
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};
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&usb1 {
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clocks = <&clk60>, <&clk60>;
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clocks = <&versal_net_clk USB1_BUS_REF>, <&versal_net_clk USB1_BUS_REF>;
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power-domains = <&versal_net_firmware PM_DEV_USB_1>;
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resets = <&versal_net_reset VERSAL_RST_USB_1>;
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};
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&dwc3_1 {
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clocks = <&clk60>;
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clocks = <&versal_net_clk USB1_BUS_REF>;
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};
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&wwdt0 {
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clocks = <&clk150>;
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clocks = <&versal_net_clk FPD_WWDT0>;
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power-domains = <&versal_net_firmware PM_DEV_FPD_SWDT_0>;
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};
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&wwdt1 {
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clocks = <&clk150>;
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clocks = <&versal_net_clk FPD_WWDT1>;
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power-domains = <&versal_net_firmware PM_DEV_FPD_SWDT_1>;
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};
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&wwdt2 {
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||||
clocks = <&clk150>;
|
||||
clocks = <&versal_net_clk FPD_WWDT2>;
|
||||
power-domains = <&versal_net_firmware PM_DEV_FPD_SWDT_2>;
|
||||
};
|
||||
|
||||
&wwdt3 {
|
||||
clocks = <&clk150>;
|
||||
clocks = <&versal_net_clk FPD_WWDT3>;
|
||||
power-domains = <&versal_net_firmware PM_DEV_FPD_SWDT_3>;
|
||||
};
|
||||
|
||||
&lpd_wwdt0 {
|
||||
clocks = <&clk150>;
|
||||
clocks = <&versal_net_clk LPD_WWDT0>;
|
||||
power-domains = <&versal_net_firmware PM_DEV_LPD_SWDT_0>;
|
||||
};
|
||||
|
||||
&lpd_wwdt1 {
|
||||
clocks = <&clk150>;
|
||||
clocks = <&versal_net_clk LPD_WWDT1>;
|
||||
power-domains = <&versal_net_firmware PM_DEV_LPD_SWDT_1>;
|
||||
};
|
||||
|
|
|
|||
123
arch/arm64/boot/dts/xilinx/xlnx-versal-clk.h
Normal file
123
arch/arm64/boot/dts/xilinx/xlnx-versal-clk.h
Normal file
|
|
@ -0,0 +1,123 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (C) 2019 - 2022, Xilinx, Inc.
|
||||
* Copyright (C) 2022 - 2026, Advanced Micro Devices, Inc.
|
||||
*/
|
||||
|
||||
#ifndef _XLNX_VERSAL_CLK_H
|
||||
#define _XLNX_VERSAL_CLK_H
|
||||
|
||||
#define PMC_PLL 1
|
||||
#define APU_PLL 2
|
||||
#define RPU_PLL 3
|
||||
#define CPM_PLL 4
|
||||
#define NOC_PLL 5
|
||||
#define PLL_MAX 6
|
||||
#define PMC_PRESRC 7
|
||||
#define PMC_POSTCLK 8
|
||||
#define PMC_PLL_OUT 9
|
||||
#define PPLL 10
|
||||
#define NOC_PRESRC 11
|
||||
#define NOC_POSTCLK 12
|
||||
#define NOC_PLL_OUT 13
|
||||
#define NPLL 14
|
||||
#define APU_PRESRC 15
|
||||
#define APU_POSTCLK 16
|
||||
#define APU_PLL_OUT 17
|
||||
#define APLL 18
|
||||
#define RPU_PRESRC 19
|
||||
#define RPU_POSTCLK 20
|
||||
#define RPU_PLL_OUT 21
|
||||
#define RPLL 22
|
||||
#define CPM_PRESRC 23
|
||||
#define CPM_POSTCLK 24
|
||||
#define CPM_PLL_OUT 25
|
||||
#define CPLL 26
|
||||
#define PPLL_TO_XPD 27
|
||||
#define NPLL_TO_XPD 28
|
||||
#define APLL_TO_XPD 29
|
||||
#define RPLL_TO_XPD 30
|
||||
#define EFUSE_REF 31
|
||||
#define SYSMON_REF 32
|
||||
#define IRO_SUSPEND_REF 33
|
||||
#define USB_SUSPEND 34
|
||||
#define SWITCH_TIMEOUT 35
|
||||
#define RCLK_PMC 36
|
||||
#define RCLK_LPD 37
|
||||
#define WDT 38
|
||||
#define TTC0 39
|
||||
#define TTC1 40
|
||||
#define TTC2 41
|
||||
#define TTC3 42
|
||||
#define GEM_TSU 43
|
||||
#define GEM_TSU_LB 44
|
||||
#define MUXED_IRO_DIV2 45
|
||||
#define MUXED_IRO_DIV4 46
|
||||
#define PSM_REF 47
|
||||
#define GEM0_RX 48
|
||||
#define GEM0_TX 49
|
||||
#define GEM1_RX 50
|
||||
#define GEM1_TX 51
|
||||
#define CPM_CORE_REF 52
|
||||
#define CPM_LSBUS_REF 53
|
||||
#define CPM_DBG_REF 54
|
||||
#define CPM_AUX0_REF 55
|
||||
#define CPM_AUX1_REF 56
|
||||
#define QSPI_REF 57
|
||||
#define OSPI_REF 58
|
||||
#define SDIO0_REF 59
|
||||
#define SDIO1_REF 60
|
||||
#define PMC_LSBUS_REF 61
|
||||
#define I2C_REF 62
|
||||
#define TEST_PATTERN_REF 63
|
||||
#define DFT_OSC_REF 64
|
||||
#define PMC_PL0_REF 65
|
||||
#define PMC_PL1_REF 66
|
||||
#define PMC_PL2_REF 67
|
||||
#define PMC_PL3_REF 68
|
||||
#define CFU_REF 69
|
||||
#define SPARE_REF 70
|
||||
#define NPI_REF 71
|
||||
#define HSM0_REF 72
|
||||
#define HSM1_REF 73
|
||||
#define SD_DLL_REF 74
|
||||
#define FPD_TOP_SWITCH 75
|
||||
#define FPD_LSBUS 76
|
||||
#define ACPU 77
|
||||
#define DBG_TRACE 78
|
||||
#define DBG_FPD 79
|
||||
#define LPD_TOP_SWITCH 80
|
||||
#define ADMA 81
|
||||
#define LPD_LSBUS 82
|
||||
#define CPU_R5 83
|
||||
#define CPU_R5_CORE 84
|
||||
#define CPU_R5_OCM 85
|
||||
#define CPU_R5_OCM2 86
|
||||
#define IOU_SWITCH 87
|
||||
#define GEM0_REF 88
|
||||
#define GEM1_REF 89
|
||||
#define GEM_TSU_REF 90
|
||||
#define USB0_BUS_REF 91
|
||||
#define UART0_REF 92
|
||||
#define UART1_REF 93
|
||||
#define SPI0_REF 94
|
||||
#define SPI1_REF 95
|
||||
#define CAN0_REF 96
|
||||
#define CAN1_REF 97
|
||||
#define I2C0_REF 98
|
||||
#define I2C1_REF 99
|
||||
#define DBG_LPD 100
|
||||
#define TIMESTAMP_REF 101
|
||||
#define DBG_TSTMP 102
|
||||
#define CPM_TOPSW_REF 103
|
||||
#define USB3_DUAL_REF 104
|
||||
#define OUTCLK_MAX 105
|
||||
#define REF_CLK 106
|
||||
#define PL_ALT_REF_CLK 107
|
||||
#define MUXED_IRO 108
|
||||
#define PL_EXT 109
|
||||
#define PL_LB 110
|
||||
#define MIO_50_OR_51 111
|
||||
#define MIO_24_OR_25 112
|
||||
|
||||
#endif
|
||||
74
arch/arm64/boot/dts/xilinx/xlnx-versal-net-clk.h
Normal file
74
arch/arm64/boot/dts/xilinx/xlnx-versal-net-clk.h
Normal file
|
|
@ -0,0 +1,74 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (C) 2022, Xilinx, Inc.
|
||||
* Copyright (C) 2022 - 2026, Advanced Micro Devices, Inc.
|
||||
*/
|
||||
|
||||
#ifndef _XLNX_VERSAL_NET_CLK_H
|
||||
#define _XLNX_VERSAL_NET_CLK_H
|
||||
|
||||
#include "xlnx-versal-clk.h"
|
||||
|
||||
#define CAN0_REF_2X 0x9e
|
||||
#define CAN1_REF_2X 0xac
|
||||
#define FPD_WWDT0 0xb5
|
||||
#define FPD_WWDT1 0xb6
|
||||
#define FPD_WWDT2 0xb7
|
||||
#define FPD_WWDT3 0xb8
|
||||
#define LPD_WWDT0 0xb9
|
||||
#define LPD_WWDT1 0xba
|
||||
#define ACPU_0 0x98
|
||||
#define ACPU_1 0x9b
|
||||
#define ACPU_2 0x9a
|
||||
#define ACPU_3 0x99
|
||||
#define I3C0_REF 0x9d
|
||||
#define I3C1_REF 0x9f
|
||||
#define USB1_BUS_REF 0xae
|
||||
#define LPD_WWDT 0xad
|
||||
|
||||
/* Remove Versal specific node IDs */
|
||||
#undef APU_PLL
|
||||
#undef RPU_PLL
|
||||
#undef CPM_PLL
|
||||
#undef APU_PRESRC
|
||||
#undef APU_POSTCLK
|
||||
#undef APU_PLL_OUT
|
||||
#undef APLL
|
||||
#undef RPU_PRESRC
|
||||
#undef RPU_POSTCLK
|
||||
#undef RPU_PLL_OUT
|
||||
#undef RPLL
|
||||
#undef CPM_PRESRC
|
||||
#undef CPM_POSTCLK
|
||||
#undef CPM_PLL_OUT
|
||||
#undef CPLL
|
||||
#undef APLL_TO_XPD
|
||||
#undef RPLL_TO_XPD
|
||||
#undef RCLK_PMC
|
||||
#undef RCLK_LPD
|
||||
#undef WDT
|
||||
#undef MUXED_IRO_DIV2
|
||||
#undef MUXED_IRO_DIV4
|
||||
#undef PSM_REF
|
||||
#undef CPM_CORE_REF
|
||||
#undef CPM_LSBUS_REF
|
||||
#undef CPM_DBG_REF
|
||||
#undef CPM_AUX0_REF
|
||||
#undef CPM_AUX1_REF
|
||||
#undef CPU_R5
|
||||
#undef CPU_R5_CORE
|
||||
#undef CPU_R5_OCM
|
||||
#undef CPU_R5_OCM2
|
||||
#undef CAN0_REF
|
||||
#undef CAN1_REF
|
||||
#undef I2C0_REF
|
||||
#undef I2C1_REF
|
||||
#undef CPM_TOPSW_REF
|
||||
#undef USB3_DUAL_REF
|
||||
#undef MUXED_IRO
|
||||
#undef PL_EXT
|
||||
#undef PL_LB
|
||||
#undef MIO_50_OR_51
|
||||
#undef MIO_24_OR_25
|
||||
|
||||
#endif
|
||||
38
arch/arm64/boot/dts/xilinx/xlnx-versal-net-power.h
Normal file
38
arch/arm64/boot/dts/xilinx/xlnx-versal-net-power.h
Normal file
|
|
@ -0,0 +1,38 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (C) 2022, Xilinx, Inc.
|
||||
* Copyright (C) 2022 - 2026, Advanced Micro Devices, Inc.
|
||||
*/
|
||||
|
||||
#ifndef _XLNX_VERSAL_NET_POWER_H
|
||||
#define _XLNX_VERSAL_NET_POWER_H
|
||||
|
||||
#include "xlnx-versal-power.h"
|
||||
|
||||
#define PM_DEV_USB_1 (0x182240d7U)
|
||||
#define PM_DEV_FPD_SWDT_0 (0x182240dbU)
|
||||
#define PM_DEV_FPD_SWDT_1 (0x182240dcU)
|
||||
#define PM_DEV_FPD_SWDT_2 (0x182240ddU)
|
||||
#define PM_DEV_FPD_SWDT_3 (0x182240deU)
|
||||
#define PM_DEV_TCM_A_0A (0x183180cbU)
|
||||
#define PM_DEV_TCM_A_0B (0x183180ccU)
|
||||
#define PM_DEV_TCM_A_0C (0x183180cdU)
|
||||
#define PM_DEV_RPU_A_0 (0x181100bfU)
|
||||
#define PM_DEV_LPD_SWDT_0 (0x182240d9U)
|
||||
#define PM_DEV_LPD_SWDT_1 (0x182240daU)
|
||||
|
||||
/* Remove Versal specific node IDs */
|
||||
#undef PM_DEV_RPU0_0
|
||||
#undef PM_DEV_RPU0_1
|
||||
#undef PM_DEV_OCM_0
|
||||
#undef PM_DEV_OCM_1
|
||||
#undef PM_DEV_OCM_2
|
||||
#undef PM_DEV_OCM_3
|
||||
#undef PM_DEV_TCM_0_A
|
||||
#undef PM_DEV_TCM_1_A
|
||||
#undef PM_DEV_TCM_0_B
|
||||
#undef PM_DEV_TCM_1_B
|
||||
#undef PM_DEV_SWDT_FPD
|
||||
#undef PM_DEV_AI
|
||||
|
||||
#endif
|
||||
53
arch/arm64/boot/dts/xilinx/xlnx-versal-net-resets.h
Normal file
53
arch/arm64/boot/dts/xilinx/xlnx-versal-net-resets.h
Normal file
|
|
@ -0,0 +1,53 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (C) 2022, Xilinx, Inc.
|
||||
* Copyright (C) 2022 - 2026, Advanced Micro Devices, Inc.
|
||||
*/
|
||||
|
||||
#ifndef _XLNX_VERSAL_NET_RESETS_H
|
||||
#define _XLNX_VERSAL_NET_RESETS_H
|
||||
|
||||
#include "xlnx-versal-resets.h"
|
||||
|
||||
#define VERSAL_RST_USB_1 (0xc1040c6U)
|
||||
|
||||
/* Remove Versal specific reset IDs */
|
||||
#undef VERSAL_RST_ACPU_0_POR
|
||||
#undef VERSAL_RST_ACPU_1_POR
|
||||
#undef VERSAL_RST_OCM2_POR
|
||||
#undef VERSAL_RST_APU
|
||||
#undef VERSAL_RST_ACPU_0
|
||||
#undef VERSAL_RST_ACPU_1
|
||||
#undef VERSAL_RST_ACPU_L2
|
||||
#undef VERSAL_RST_RPU_ISLAND
|
||||
#undef VERSAL_RST_RPU_AMBA
|
||||
#undef VERSAL_RST_R5_0
|
||||
#undef VERSAL_RST_R5_1
|
||||
#undef VERSAL_RST_OCM2_RST
|
||||
#undef VERSAL_RST_I2C_PMC
|
||||
#undef VERSAL_RST_I2C_0
|
||||
#undef VERSAL_RST_I2C_1
|
||||
#undef VERSAL_RST_SWDT_FPD
|
||||
#undef VERSAL_RST_SWDT_LPD
|
||||
#undef VERSAL_RST_USB
|
||||
#undef VERSAL_RST_DPC
|
||||
#undef VERSAL_RST_DBG_TRACE
|
||||
#undef VERSAL_RST_DBG_TSTMP
|
||||
#undef VERSAL_RST_RPU0_DBG
|
||||
#undef VERSAL_RST_RPU1_DBG
|
||||
#undef VERSAL_RST_HSDP
|
||||
#undef VERSAL_RST_CPMDBG
|
||||
#undef VERSAL_RST_PCIE_CFG
|
||||
#undef VERSAL_RST_PCIE_CORE0
|
||||
#undef VERSAL_RST_PCIE_CORE1
|
||||
#undef VERSAL_RST_PCIE_DMA
|
||||
#undef VERSAL_RST_L2_0
|
||||
#undef VERSAL_RST_L2_1
|
||||
#undef VERSAL_RST_ADDR_REMAP
|
||||
#undef VERSAL_RST_CPI0
|
||||
#undef VERSAL_RST_CPI1
|
||||
#undef VERSAL_RST_XRAM
|
||||
#undef VERSAL_RST_AIE_ARRAY
|
||||
#undef VERSAL_RST_AIE_SHIM
|
||||
|
||||
#endif
|
||||
55
arch/arm64/boot/dts/xilinx/xlnx-versal-power.h
Normal file
55
arch/arm64/boot/dts/xilinx/xlnx-versal-power.h
Normal file
|
|
@ -0,0 +1,55 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (C) 2019 - 2022, Xilinx, Inc.
|
||||
* Copyright (C) 2022 - 2026, Advanced Micro Devices, Inc.
|
||||
*/
|
||||
|
||||
#ifndef _XLNX_VERSAL_POWER_H
|
||||
#define _XLNX_VERSAL_POWER_H
|
||||
|
||||
#define PM_DEV_RPU0_0 (0x18110005U)
|
||||
#define PM_DEV_RPU0_1 (0x18110006U)
|
||||
#define PM_DEV_OCM_0 (0x18314007U)
|
||||
#define PM_DEV_OCM_1 (0x18314008U)
|
||||
#define PM_DEV_OCM_2 (0x18314009U)
|
||||
#define PM_DEV_OCM_3 (0x1831400aU)
|
||||
#define PM_DEV_TCM_0_A (0x1831800bU)
|
||||
#define PM_DEV_TCM_0_B (0x1831800cU)
|
||||
#define PM_DEV_TCM_1_A (0x1831800dU)
|
||||
#define PM_DEV_TCM_1_B (0x1831800eU)
|
||||
#define PM_DEV_USB_0 (0x18224018U)
|
||||
#define PM_DEV_GEM_0 (0x18224019U)
|
||||
#define PM_DEV_GEM_1 (0x1822401aU)
|
||||
#define PM_DEV_SPI_0 (0x1822401bU)
|
||||
#define PM_DEV_SPI_1 (0x1822401cU)
|
||||
#define PM_DEV_I2C_0 (0x1822401dU)
|
||||
#define PM_DEV_I2C_1 (0x1822401eU)
|
||||
#define PM_DEV_CAN_FD_0 (0x1822401fU)
|
||||
#define PM_DEV_CAN_FD_1 (0x18224020U)
|
||||
#define PM_DEV_UART_0 (0x18224021U)
|
||||
#define PM_DEV_UART_1 (0x18224022U)
|
||||
#define PM_DEV_GPIO (0x18224023U)
|
||||
#define PM_DEV_TTC_0 (0x18224024U)
|
||||
#define PM_DEV_TTC_1 (0x18224025U)
|
||||
#define PM_DEV_TTC_2 (0x18224026U)
|
||||
#define PM_DEV_TTC_3 (0x18224027U)
|
||||
#define PM_DEV_SWDT_LPD (0x18224028U)
|
||||
#define PM_DEV_SWDT_FPD (0x18224029U)
|
||||
#define PM_DEV_OSPI (0x1822402aU)
|
||||
#define PM_DEV_QSPI (0x1822402bU)
|
||||
#define PM_DEV_GPIO_PMC (0x1822402cU)
|
||||
#define PM_DEV_I2C_PMC (0x1822402dU)
|
||||
#define PM_DEV_SDIO_0 (0x1822402eU)
|
||||
#define PM_DEV_SDIO_1 (0x1822402fU)
|
||||
#define PM_DEV_RTC (0x18224034U)
|
||||
#define PM_DEV_ADMA_0 (0x18224035U)
|
||||
#define PM_DEV_ADMA_1 (0x18224036U)
|
||||
#define PM_DEV_ADMA_2 (0x18224037U)
|
||||
#define PM_DEV_ADMA_3 (0x18224038U)
|
||||
#define PM_DEV_ADMA_4 (0x18224039U)
|
||||
#define PM_DEV_ADMA_5 (0x1822403aU)
|
||||
#define PM_DEV_ADMA_6 (0x1822403bU)
|
||||
#define PM_DEV_ADMA_7 (0x1822403cU)
|
||||
#define PM_DEV_AI (0x18224072U)
|
||||
|
||||
#endif
|
||||
106
arch/arm64/boot/dts/xilinx/xlnx-versal-resets.h
Normal file
106
arch/arm64/boot/dts/xilinx/xlnx-versal-resets.h
Normal file
|
|
@ -0,0 +1,106 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (C) 2020 - 2022, Xilinx, Inc.
|
||||
* Copyright (C) 2022 - 2026, Advanced Micro Devices, Inc.
|
||||
*/
|
||||
|
||||
#ifndef _XLNX_VERSAL_RESETS_H
|
||||
#define _XLNX_VERSAL_RESETS_H
|
||||
|
||||
#define VERSAL_RST_PMC_POR (0xc30c001U)
|
||||
#define VERSAL_RST_PMC (0xc410002U)
|
||||
#define VERSAL_RST_PS_POR (0xc30c003U)
|
||||
#define VERSAL_RST_PL_POR (0xc30c004U)
|
||||
#define VERSAL_RST_NOC_POR (0xc30c005U)
|
||||
#define VERSAL_RST_FPD_POR (0xc30c006U)
|
||||
#define VERSAL_RST_ACPU_0_POR (0xc30c007U)
|
||||
#define VERSAL_RST_ACPU_1_POR (0xc30c008U)
|
||||
#define VERSAL_RST_OCM2_POR (0xc30c009U)
|
||||
#define VERSAL_RST_PS_SRST (0xc41000aU)
|
||||
#define VERSAL_RST_PL_SRST (0xc41000bU)
|
||||
#define VERSAL_RST_NOC (0xc41000cU)
|
||||
#define VERSAL_RST_NPI (0xc41000dU)
|
||||
#define VERSAL_RST_SYS_RST_1 (0xc41000eU)
|
||||
#define VERSAL_RST_SYS_RST_2 (0xc41000fU)
|
||||
#define VERSAL_RST_SYS_RST_3 (0xc410010U)
|
||||
#define VERSAL_RST_FPD (0xc410011U)
|
||||
#define VERSAL_RST_PL0 (0xc410012U)
|
||||
#define VERSAL_RST_PL1 (0xc410013U)
|
||||
#define VERSAL_RST_PL2 (0xc410014U)
|
||||
#define VERSAL_RST_PL3 (0xc410015U)
|
||||
#define VERSAL_RST_APU (0xc410016U)
|
||||
#define VERSAL_RST_ACPU_0 (0xc410017U)
|
||||
#define VERSAL_RST_ACPU_1 (0xc410018U)
|
||||
#define VERSAL_RST_ACPU_L2 (0xc410019U)
|
||||
#define VERSAL_RST_ACPU_GIC (0xc41001aU)
|
||||
#define VERSAL_RST_RPU_ISLAND (0xc41001bU)
|
||||
#define VERSAL_RST_RPU_AMBA (0xc41001cU)
|
||||
#define VERSAL_RST_R5_0 (0xc41001dU)
|
||||
#define VERSAL_RST_R5_1 (0xc41001eU)
|
||||
#define VERSAL_RST_SYSMON_PMC_SEQ_RST (0xc41001fU)
|
||||
#define VERSAL_RST_SYSMON_PMC_CFG_RST (0xc410020U)
|
||||
#define VERSAL_RST_SYSMON_FPD_CFG_RST (0xc410021U)
|
||||
#define VERSAL_RST_SYSMON_FPD_SEQ_RST (0xc410022U)
|
||||
#define VERSAL_RST_SYSMON_LPD (0xc410023U)
|
||||
#define VERSAL_RST_PDMA_RST1 (0xc410024U)
|
||||
#define VERSAL_RST_PDMA_RST0 (0xc410025U)
|
||||
#define VERSAL_RST_ADMA (0xc410026U)
|
||||
#define VERSAL_RST_TIMESTAMP (0xc410027U)
|
||||
#define VERSAL_RST_OCM (0xc410028U)
|
||||
#define VERSAL_RST_OCM2_RST (0xc410029U)
|
||||
#define VERSAL_RST_IPI (0xc41002aU)
|
||||
#define VERSAL_RST_SBI (0xc41002bU)
|
||||
#define VERSAL_RST_LPD (0xc41002cU)
|
||||
#define VERSAL_RST_QSPI (0xc10402dU)
|
||||
#define VERSAL_RST_OSPI (0xc10402eU)
|
||||
#define VERSAL_RST_SDIO_0 (0xc10402fU)
|
||||
#define VERSAL_RST_SDIO_1 (0xc104030U)
|
||||
#define VERSAL_RST_I2C_PMC (0xc104031U)
|
||||
#define VERSAL_RST_GPIO_PMC (0xc104032U)
|
||||
#define VERSAL_RST_GEM_0 (0xc104033U)
|
||||
#define VERSAL_RST_GEM_1 (0xc104034U)
|
||||
#define VERSAL_RST_SPARE (0xc104035U)
|
||||
#define VERSAL_RST_USB_0 (0xc104036U)
|
||||
#define VERSAL_RST_UART_0 (0xc104037U)
|
||||
#define VERSAL_RST_UART_1 (0xc104038U)
|
||||
#define VERSAL_RST_SPI_0 (0xc104039U)
|
||||
#define VERSAL_RST_SPI_1 (0xc10403aU)
|
||||
#define VERSAL_RST_CAN_FD_0 (0xc10403bU)
|
||||
#define VERSAL_RST_CAN_FD_1 (0xc10403cU)
|
||||
#define VERSAL_RST_I2C_0 (0xc10403dU)
|
||||
#define VERSAL_RST_I2C_1 (0xc10403eU)
|
||||
#define VERSAL_RST_GPIO_LPD (0xc10403fU)
|
||||
#define VERSAL_RST_TTC_0 (0xc104040U)
|
||||
#define VERSAL_RST_TTC_1 (0xc104041U)
|
||||
#define VERSAL_RST_TTC_2 (0xc104042U)
|
||||
#define VERSAL_RST_TTC_3 (0xc104043U)
|
||||
#define VERSAL_RST_SWDT_FPD (0xc104044U)
|
||||
#define VERSAL_RST_SWDT_LPD (0xc104045U)
|
||||
#define VERSAL_RST_USB (0xc104046U)
|
||||
#define VERSAL_RST_DPC (0xc208047U)
|
||||
#define VERSAL_RST_PMCDBG (0xc208048U)
|
||||
#define VERSAL_RST_DBG_TRACE (0xc208049U)
|
||||
#define VERSAL_RST_DBG_FPD (0xc20804aU)
|
||||
#define VERSAL_RST_DBG_TSTMP (0xc20804bU)
|
||||
#define VERSAL_RST_RPU0_DBG (0xc20804cU)
|
||||
#define VERSAL_RST_RPU1_DBG (0xc20804dU)
|
||||
#define VERSAL_RST_HSDP (0xc20804eU)
|
||||
#define VERSAL_RST_DBG_LPD (0xc20804fU)
|
||||
#define VERSAL_RST_CPM_POR (0xc30c050U)
|
||||
#define VERSAL_RST_CPM (0xc410051U)
|
||||
#define VERSAL_RST_CPMDBG (0xc208052U)
|
||||
#define VERSAL_RST_PCIE_CFG (0xc410053U)
|
||||
#define VERSAL_RST_PCIE_CORE0 (0xc410054U)
|
||||
#define VERSAL_RST_PCIE_CORE1 (0xc410055U)
|
||||
#define VERSAL_RST_PCIE_DMA (0xc410056U)
|
||||
#define VERSAL_RST_CMN (0xc410057U)
|
||||
#define VERSAL_RST_L2_0 (0xc410058U)
|
||||
#define VERSAL_RST_L2_1 (0xc410059U)
|
||||
#define VERSAL_RST_ADDR_REMAP (0xc41005aU)
|
||||
#define VERSAL_RST_CPI0 (0xc41005bU)
|
||||
#define VERSAL_RST_CPI1 (0xc41005cU)
|
||||
#define VERSAL_RST_XRAM (0xc30c05dU)
|
||||
#define VERSAL_RST_AIE_ARRAY (0xc10405eU)
|
||||
#define VERSAL_RST_AIE_SHIM (0xc10405fU)
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue
Block a user