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media: iris: Add support for multiple TZ content protection(CP) configs
vpu4 needs an additional configuration with respect to CP regions. Make the CP configuration as array such that the multiple configuration can be managed per platform. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Co-developed-by: Vishnu Reddy <busanna.reddy@oss.qualcomm.com> Signed-off-by: Vishnu Reddy <busanna.reddy@oss.qualcomm.com> Signed-off-by: Vikash Garodia <vikash.garodia@oss.qualcomm.com> Reviewed-by: Dikshita Agarwal <dikshita.agarwal@oss.qualcomm.com> Signed-off-by: Bryan O'Donoghue <bod@kernel.org> Signed-off-by: Hans Verkuil <hverkuil+cisco@kernel.org>
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@ -64,9 +64,9 @@ static int iris_load_fw_to_memory(struct iris_core *core, const char *fw_name)
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int iris_fw_load(struct iris_core *core)
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{
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struct tz_cp_config *cp_config = core->iris_platform_data->tz_cp_config_data;
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const struct tz_cp_config *cp_config;
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const char *fwpath = NULL;
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int ret;
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int i, ret;
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ret = of_property_read_string_index(core->dev->of_node, "firmware-name", 0,
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&fwpath);
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@ -85,14 +85,17 @@ int iris_fw_load(struct iris_core *core)
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return ret;
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}
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ret = qcom_scm_mem_protect_video_var(cp_config->cp_start,
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cp_config->cp_size,
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cp_config->cp_nonpixel_start,
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cp_config->cp_nonpixel_size);
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if (ret) {
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dev_err(core->dev, "protect memory failed\n");
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qcom_scm_pas_shutdown(core->iris_platform_data->pas_id);
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return ret;
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for (i = 0; i < core->iris_platform_data->tz_cp_config_data_size; i++) {
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cp_config = &core->iris_platform_data->tz_cp_config_data[i];
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ret = qcom_scm_mem_protect_video_var(cp_config->cp_start,
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cp_config->cp_size,
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cp_config->cp_nonpixel_start,
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cp_config->cp_nonpixel_size);
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if (ret) {
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dev_err(core->dev, "qcom_scm_mem_protect_video_var failed: %d\n", ret);
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qcom_scm_pas_shutdown(core->iris_platform_data->pas_id);
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return ret;
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}
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}
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return ret;
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@ -237,7 +237,8 @@ struct iris_platform_data {
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u32 inst_fw_caps_dec_size;
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const struct platform_inst_fw_cap *inst_fw_caps_enc;
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u32 inst_fw_caps_enc_size;
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struct tz_cp_config *tz_cp_config_data;
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const struct tz_cp_config *tz_cp_config_data;
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u32 tz_cp_config_data_size;
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u32 core_arch;
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u32 hw_response_timeout;
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struct ubwc_config_data *ubwc_config;
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@ -294,11 +294,13 @@ static const char * const sm8250_opp_clk_table[] = {
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NULL,
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};
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static struct tz_cp_config tz_cp_config_sm8250 = {
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.cp_start = 0,
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.cp_size = 0x25800000,
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.cp_nonpixel_start = 0x01000000,
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.cp_nonpixel_size = 0x24800000,
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static const struct tz_cp_config tz_cp_config_sm8250[] = {
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{
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.cp_start = 0,
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.cp_size = 0x25800000,
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.cp_nonpixel_start = 0x01000000,
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.cp_nonpixel_size = 0x24800000,
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},
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};
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static const u32 sm8250_vdec_input_config_param_default[] = {
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@ -366,7 +368,8 @@ const struct iris_platform_data sm8250_data = {
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.inst_fw_caps_dec_size = ARRAY_SIZE(inst_fw_cap_sm8250_dec),
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.inst_fw_caps_enc = inst_fw_cap_sm8250_enc,
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.inst_fw_caps_enc_size = ARRAY_SIZE(inst_fw_cap_sm8250_enc),
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.tz_cp_config_data = &tz_cp_config_sm8250,
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.tz_cp_config_data = tz_cp_config_sm8250,
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.tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_sm8250),
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.hw_response_timeout = HW_RESPONSE_TIMEOUT_VALUE,
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.num_vpp_pipe = 4,
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.max_session_count = 16,
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@ -418,7 +421,8 @@ const struct iris_platform_data sc7280_data = {
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.inst_fw_caps_dec_size = ARRAY_SIZE(inst_fw_cap_sm8250_dec),
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.inst_fw_caps_enc = inst_fw_cap_sm8250_enc,
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.inst_fw_caps_enc_size = ARRAY_SIZE(inst_fw_cap_sm8250_enc),
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.tz_cp_config_data = &tz_cp_config_sm8250,
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.tz_cp_config_data = tz_cp_config_sm8250,
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.tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_sm8250),
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.hw_response_timeout = HW_RESPONSE_TIMEOUT_VALUE,
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.num_vpp_pipe = 1,
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.no_aon = true,
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@ -800,11 +800,13 @@ static struct ubwc_config_data ubwc_config_sm8550 = {
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.bank_spreading = 1,
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};
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static struct tz_cp_config tz_cp_config_sm8550 = {
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.cp_start = 0,
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.cp_size = 0x25800000,
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.cp_nonpixel_start = 0x01000000,
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.cp_nonpixel_size = 0x24800000,
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static const struct tz_cp_config tz_cp_config_sm8550[] = {
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{
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.cp_start = 0,
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.cp_size = 0x25800000,
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.cp_nonpixel_start = 0x01000000,
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.cp_nonpixel_size = 0x24800000,
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},
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};
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static const u32 sm8550_vdec_input_config_params_default[] = {
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@ -950,7 +952,8 @@ const struct iris_platform_data sm8550_data = {
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.inst_fw_caps_dec_size = ARRAY_SIZE(inst_fw_cap_sm8550_dec),
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.inst_fw_caps_enc = inst_fw_cap_sm8550_enc,
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.inst_fw_caps_enc_size = ARRAY_SIZE(inst_fw_cap_sm8550_enc),
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.tz_cp_config_data = &tz_cp_config_sm8550,
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.tz_cp_config_data = tz_cp_config_sm8550,
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.tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_sm8550),
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.core_arch = VIDEO_ARCH_LX,
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.hw_response_timeout = HW_RESPONSE_TIMEOUT_VALUE,
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.ubwc_config = &ubwc_config_sm8550,
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@ -1054,7 +1057,8 @@ const struct iris_platform_data sm8650_data = {
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.inst_fw_caps_dec_size = ARRAY_SIZE(inst_fw_cap_sm8550_dec),
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.inst_fw_caps_enc = inst_fw_cap_sm8550_enc,
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.inst_fw_caps_enc_size = ARRAY_SIZE(inst_fw_cap_sm8550_enc),
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.tz_cp_config_data = &tz_cp_config_sm8550,
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.tz_cp_config_data = tz_cp_config_sm8550,
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.tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_sm8550),
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.core_arch = VIDEO_ARCH_LX,
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.hw_response_timeout = HW_RESPONSE_TIMEOUT_VALUE,
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.ubwc_config = &ubwc_config_sm8550,
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@ -1149,7 +1153,8 @@ const struct iris_platform_data sm8750_data = {
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.inst_fw_caps_dec_size = ARRAY_SIZE(inst_fw_cap_sm8550_dec),
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.inst_fw_caps_enc = inst_fw_cap_sm8550_enc,
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.inst_fw_caps_enc_size = ARRAY_SIZE(inst_fw_cap_sm8550_enc),
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.tz_cp_config_data = &tz_cp_config_sm8550,
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.tz_cp_config_data = tz_cp_config_sm8550,
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.tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_sm8550),
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.core_arch = VIDEO_ARCH_LX,
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.hw_response_timeout = HW_RESPONSE_TIMEOUT_VALUE,
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.ubwc_config = &ubwc_config_sm8550,
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@ -1248,7 +1253,8 @@ const struct iris_platform_data qcs8300_data = {
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.inst_fw_caps_dec_size = ARRAY_SIZE(inst_fw_cap_sm8550_dec),
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.inst_fw_caps_enc = inst_fw_cap_sm8550_enc,
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.inst_fw_caps_enc_size = ARRAY_SIZE(inst_fw_cap_sm8550_enc),
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.tz_cp_config_data = &tz_cp_config_sm8550,
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.tz_cp_config_data = tz_cp_config_sm8550,
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.tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_sm8550),
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.core_arch = VIDEO_ARCH_LX,
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.hw_response_timeout = HW_RESPONSE_TIMEOUT_VALUE,
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.ubwc_config = &ubwc_config_sm8550,
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