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media: iris: Add support for multiple clock sources

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vpu4 depends on more than one clock source. Thus far hardware versions
up to vpu3x have been clocked by a single source.
This adds support for multiple clocks by,
- Adding a lookup table
- Configuring OPP table for video device with different video clocks
- Setting OPP for multiple clocks during dev_pm_opp_set_opp()

This patch extends the support for multiple clocks in driver, which
would be used in subsequent patch for kaanapali, when the platform data
is prepared.

Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Co-developed-by: Vishnu Reddy <busanna.reddy@oss.qualcomm.com>
Signed-off-by: Vishnu Reddy <busanna.reddy@oss.qualcomm.com>
Signed-off-by: Vikash Garodia <vikash.garodia@oss.qualcomm.com>
Reviewed-by: Dikshita Agarwal <dikshita.agarwal@oss.qualcomm.com>
Signed-off-by: Bryan O'Donoghue <bod@kernel.org>
Signed-off-by: Hans Verkuil <hverkuil+cisco@kernel.org>
This commit is contained in:
Vikash Garodia 2025-12-10 18:05:59 +05:30 committed by Hans Verkuil
parent 5ef0832c6e
commit 8744df0e89
9 changed files with 48 additions and 17 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
drivers/media/platform/qcom/iris/iris_platform_common.h
View File

@ -221,6 +221,7 @@ struct iris_platform_data {
const char * const *opp_pd_tbl;
unsigned int opp_pd_tbl_size;
const struct platform_clk_data *clk_tbl;
const char * const *opp_clk_tbl;
unsigned int clk_tbl_size;
const char * const *clk_rst_tbl;
unsigned int clk_rst_tbl_size;

7
drivers/media/platform/qcom/iris/iris_platform_gen1.c
View File

@ -289,6 +289,11 @@ static const struct platform_clk_data sm8250_clk_table[] = {
{IRIS_HW_CLK, "vcodec0_core" },
};
static const char * const sm8250_opp_clk_table[] = {
"vcodec0_core",
NULL,
};
static struct tz_cp_config tz_cp_config_sm8250 = {
.cp_start = 0,
.cp_size = 0x25800000,
@ -349,6 +354,7 @@ const struct iris_platform_data sm8250_data = {
.opp_pd_tbl_size = ARRAY_SIZE(sm8250_opp_pd_table),
.clk_tbl = sm8250_clk_table,
.clk_tbl_size = ARRAY_SIZE(sm8250_clk_table),
.opp_clk_tbl = sm8250_opp_clk_table,
/* Upper bound of DMA address range */
.dma_mask = 0xe0000000 - 1,
.fwname = "qcom/vpu-1.0/venus.mbn",
@ -400,6 +406,7 @@ const struct iris_platform_data sc7280_data = {
.opp_pd_tbl_size = ARRAY_SIZE(sc7280_opp_pd_table),
.clk_tbl = sc7280_clk_table,
.clk_tbl_size = ARRAY_SIZE(sc7280_clk_table),
.opp_clk_tbl = sc7280_opp_clk_table,
/* Upper bound of DMA address range */
.dma_mask = 0xe0000000 - 1,
.fwname = "qcom/vpu/vpu20_p1.mbn",

9
drivers/media/platform/qcom/iris/iris_platform_gen2.c
View File

@ -785,6 +785,11 @@ static const struct platform_clk_data sm8550_clk_table[] = {
{IRIS_HW_CLK, "vcodec0_core" },
};
static const char * const sm8550_opp_clk_table[] = {
"vcodec0_core",
NULL,
};
static struct ubwc_config_data ubwc_config_sm8550 = {
.max_channels = 8,
.mal_length = 32,
@ -933,6 +938,7 @@ const struct iris_platform_data sm8550_data = {
.opp_pd_tbl_size = ARRAY_SIZE(sm8550_opp_pd_table),
.clk_tbl = sm8550_clk_table,
.clk_tbl_size = ARRAY_SIZE(sm8550_clk_table),
.opp_clk_tbl = sm8550_opp_clk_table,
/* Upper bound of DMA address range */
.dma_mask = 0xe0000000 - 1,
.fwname = "qcom/vpu/vpu30_p4.mbn",
@ -1036,6 +1042,7 @@ const struct iris_platform_data sm8650_data = {
.opp_pd_tbl_size = ARRAY_SIZE(sm8550_opp_pd_table),
.clk_tbl = sm8550_clk_table,
.clk_tbl_size = ARRAY_SIZE(sm8550_clk_table),
.opp_clk_tbl = sm8550_opp_clk_table,
/* Upper bound of DMA address range */
.dma_mask = 0xe0000000 - 1,
.fwname = "qcom/vpu/vpu33_p4.mbn",
@ -1130,6 +1137,7 @@ const struct iris_platform_data sm8750_data = {
.opp_pd_tbl_size = ARRAY_SIZE(sm8550_opp_pd_table),
.clk_tbl = sm8750_clk_table,
.clk_tbl_size = ARRAY_SIZE(sm8750_clk_table),
.opp_clk_tbl = sm8550_opp_clk_table,
/* Upper bound of DMA address range */
.dma_mask = 0xe0000000 - 1,
.fwname = "qcom/vpu/vpu35_p4.mbn",
@ -1228,6 +1236,7 @@ const struct iris_platform_data qcs8300_data = {
.opp_pd_tbl_size = ARRAY_SIZE(sm8550_opp_pd_table),
.clk_tbl = sm8550_clk_table,
.clk_tbl_size = ARRAY_SIZE(sm8550_clk_table),
.opp_clk_tbl = sm8550_opp_clk_table,
/* Upper bound of DMA address range */
.dma_mask = 0xe0000000 - 1,
.fwname = "qcom/vpu/vpu30_p4_s6.mbn",

5
drivers/media/platform/qcom/iris/iris_platform_sc7280.h
View File

@ -23,4 +23,9 @@ static const struct platform_clk_data sc7280_clk_table[] = {
{IRIS_HW_AHB_CLK, "vcodec_bus" },
};
static const char * const sc7280_opp_clk_table[] = {
"vcodec_core",
NULL,
};
#endif

2
drivers/media/platform/qcom/iris/iris_power.c
View File

@ -91,7 +91,7 @@ static int iris_set_clocks(struct iris_inst *inst)
}
core->power.clk_freq = freq;
ret = dev_pm_opp_set_rate(core->dev, freq);
ret = iris_opp_set_rate(core->dev, freq);
mutex_unlock(&core->lock);
return ret;

20
drivers/media/platform/qcom/iris/iris_probe.c
View File

@ -40,8 +40,6 @@ static int iris_init_icc(struct iris_core *core)
static int iris_init_power_domains(struct iris_core *core)
{
const struct platform_clk_data *clk_tbl;
u32 clk_cnt, i;
int ret;
struct dev_pm_domain_attach_data iris_pd_data = {
@ -56,6 +54,11 @@ static int iris_init_power_domains(struct iris_core *core)
.pd_flags = PD_FLAG_DEV_LINK_ON | PD_FLAG_REQUIRED_OPP,
};
struct dev_pm_opp_config iris_opp_clk_data = {
.clk_names = core->iris_platform_data->opp_clk_tbl,
.config_clks = dev_pm_opp_config_clks_simple,
};
ret = devm_pm_domain_attach_list(core->dev, &iris_pd_data, &core->pmdomain_tbl);
if (ret < 0)
return ret;
@ -64,16 +67,9 @@ static int iris_init_power_domains(struct iris_core *core)
if (ret < 0)
return ret;
clk_tbl = core->iris_platform_data->clk_tbl;
clk_cnt = core->iris_platform_data->clk_tbl_size;
for (i = 0; i < clk_cnt; i++) {
if (clk_tbl[i].clk_type == IRIS_HW_CLK) {
ret = devm_pm_opp_set_clkname(core->dev, clk_tbl[i].clk_name);
if (ret)
return ret;
}
}
ret = devm_pm_opp_set_config(core->dev, &iris_opp_clk_data);
if (ret)
return ret;
return devm_pm_opp_of_add_table(core->dev);
}

16
drivers/media/platform/qcom/iris/iris_resources.c
View File

@ -4,6 +4,7 @@
*/
#include <linux/clk.h>
#include <linux/devfreq.h>
#include <linux/interconnect.h>
#include <linux/pm_domain.h>
#include <linux/pm_opp.h>
@ -58,11 +59,22 @@ int iris_unset_icc_bw(struct iris_core *core)
return icc_bulk_set_bw(core->icc_count, core->icc_tbl);
}
int iris_opp_set_rate(struct device *dev, unsigned long freq)
{
struct dev_pm_opp *opp __free(put_opp);
opp = devfreq_recommended_opp(dev, &freq, 0);
if (IS_ERR(opp))
return PTR_ERR(opp);
return dev_pm_opp_set_opp(dev, opp);
}
int iris_enable_power_domains(struct iris_core *core, struct device *pd_dev)
{
int ret;
ret = dev_pm_opp_set_rate(core->dev, ULONG_MAX);
ret = iris_opp_set_rate(core->dev, ULONG_MAX);
if (ret)
return ret;
@ -77,7 +89,7 @@ int iris_disable_power_domains(struct iris_core *core, struct device *pd_dev)
{
int ret;
ret = dev_pm_opp_set_rate(core->dev, 0);
ret = iris_opp_set_rate(core->dev, 0);
if (ret)
return ret;

1
drivers/media/platform/qcom/iris/iris_resources.h
View File

@ -8,6 +8,7 @@
struct iris_core;
int iris_opp_set_rate(struct device *dev, unsigned long freq);
int iris_enable_power_domains(struct iris_core *core, struct device *pd_dev);
int iris_disable_power_domains(struct iris_core *core, struct device *pd_dev);
int iris_unset_icc_bw(struct iris_core *core);

4
drivers/media/platform/qcom/iris/iris_vpu_common.c
View File

@ -270,7 +270,7 @@ void iris_vpu_power_off_hw(struct iris_core *core)
void iris_vpu_power_off(struct iris_core *core)
{
dev_pm_opp_set_rate(core->dev, 0);
iris_opp_set_rate(core->dev, 0);
core->iris_platform_data->vpu_ops->power_off_hw(core);
core->iris_platform_data->vpu_ops->power_off_controller(core);
iris_unset_icc_bw(core);
@ -368,7 +368,7 @@ int iris_vpu_power_on(struct iris_core *core)
freq = core->power.clk_freq ? core->power.clk_freq :
(u32)ULONG_MAX;
dev_pm_opp_set_rate(core->dev, freq);
iris_opp_set_rate(core->dev, freq);
core->iris_platform_data->set_preset_registers(core);