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ARM: dts: qcom: msm8960: reorder nodes and properties
Reorder the nodes in qcom-msm8960.dtsi by unit address and sort properties, as recommended in the Devicetree style guide. This is a cosmetic change only, with no functional impact. Tested-by: Rudraksha Gupta <guptarud@gmail.com> Tested-by: Shinjo Park <peremen@gmail.com> Signed-off-by: Antony Kurniawan Soemardi <linux@smankusors.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250921-msm8960-reorder-v2-1-26c478366d21@smankusors.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
This commit is contained in:
Antony Kurniawan Soemardi
Bjorn Andersson
parent
3a86608788
commit
df41d58048
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@ -15,6 +15,35 @@ / {
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compatible = "qcom,msm8960";
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interrupt-parent = <&intc>;
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clocks {
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cxo_board: cxo_board {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <19200000>;
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clock-output-names = "cxo_board";
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};
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pxo_board: pxo_board {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <27000000>;
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clock-output-names = "pxo_board";
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};
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sleep_clk: sleep_clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <32768>;
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clock-output-names = "sleep_clk";
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};
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};
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cpu-pmu {
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compatible = "qcom,krait-pmu";
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interrupts = <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
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qcom,no-pc-write;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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@ -22,9 +51,9 @@ cpus {
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cpu@0 {
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compatible = "qcom,krait";
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reg = <0>;
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enable-method = "qcom,kpss-acc-v1";
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device_type = "cpu";
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reg = <0>;
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next-level-cache = <&l2>;
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qcom,acc = <&acc0>;
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qcom,saw = <&saw0>;
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@ -32,9 +61,9 @@ cpu@0 {
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cpu@1 {
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compatible = "qcom,krait";
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reg = <1>;
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enable-method = "qcom,kpss-acc-v1";
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device_type = "cpu";
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reg = <1>;
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next-level-cache = <&l2>;
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qcom,acc = <&acc1>;
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qcom,saw = <&saw1>;
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@ -52,6 +81,411 @@ memory@80000000 {
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reg = <0x80000000 0>;
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};
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soc: soc {
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compatible = "simple-bus";
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ranges;
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#address-cells = <1>;
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#size-cells = <1>;
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rpm: rpm@108000 {
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compatible = "qcom,rpm-msm8960";
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reg = <0x108000 0x1000>;
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qcom,ipc = <&l2cc 0x8 2>;
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interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
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interrupt-names = "ack",
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"err",
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"wakeup";
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};
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ssbi: ssbi@500000 {
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compatible = "qcom,ssbi";
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reg = <0x500000 0x1000>;
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qcom,controller-type = "pmic-arbiter";
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};
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qfprom: efuse@700000 {
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compatible = "qcom,msm8960-qfprom", "qcom,qfprom";
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reg = <0x00700000 0x1000>;
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#address-cells = <1>;
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#size-cells = <1>;
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tsens_calib: calib@404 {
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reg = <0x404 0x10>;
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};
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tsens_backup: backup-calib@414 {
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reg = <0x414 0x10>;
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};
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};
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msmgpio: pinctrl@800000 {
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compatible = "qcom,msm8960-pinctrl";
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reg = <0x800000 0x4000>;
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gpio-controller;
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gpio-ranges = <&msmgpio 0 0 152>;
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#gpio-cells = <2>;
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interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gcc: clock-controller@900000 {
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compatible = "qcom,gcc-msm8960", "syscon";
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reg = <0x900000 0x4000>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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clocks = <&cxo_board>,
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<&pxo_board>,
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<&lcc PLL4>;
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clock-names = "cxo",
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"pxo",
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"pll4";
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tsens: thermal-sensor {
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compatible = "qcom,msm8960-tsens";
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nvmem-cells = <&tsens_calib>, <&tsens_backup>;
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nvmem-cell-names = "calib", "calib_backup";
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interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "uplow";
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#qcom,sensors = <5>;
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#thermal-sensor-cells = <1>;
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};
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};
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intc: interrupt-controller@2000000 {
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compatible = "qcom,msm-qgic2";
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reg = <0x02000000 0x1000>,
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<0x02002000 0x1000>;
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interrupt-controller;
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#interrupt-cells = <3>;
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};
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timer@200a000 {
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compatible = "qcom,kpss-wdt-msm8960", "qcom,kpss-timer",
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"qcom,msm-timer";
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reg = <0x0200a000 0x100>;
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interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>,
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<GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>,
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<GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>;
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clock-frequency = <27000000>;
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clocks = <&sleep_clk>;
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clock-names = "sleep";
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cpu-offset = <0x80000>;
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};
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l2cc: clock-controller@2011000 {
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compatible = "qcom,kpss-gcc-msm8960", "qcom,kpss-gcc", "syscon";
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reg = <0x2011000 0x1000>;
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clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
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clock-names = "pll8_vote", "pxo";
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#clock-cells = <0>;
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};
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acc0: clock-controller@2088000 {
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compatible = "qcom,kpss-acc-v1";
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reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
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clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
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clock-names = "pll8_vote", "pxo";
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clock-output-names = "acpu0_aux";
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#clock-cells = <0>;
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};
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saw0: power-manager@2089000 {
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compatible = "qcom,msm8960-saw2-cpu", "qcom,saw2";
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reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
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saw0_vreg: regulator {
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regulator-min-microvolt = <850000>;
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regulator-max-microvolt = <1300000>;
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};
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};
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acc1: clock-controller@2098000 {
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compatible = "qcom,kpss-acc-v1";
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reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
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clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
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clock-names = "pll8_vote", "pxo";
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clock-output-names = "acpu1_aux";
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#clock-cells = <0>;
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};
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saw1: power-manager@2099000 {
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compatible = "qcom,msm8960-saw2-cpu", "qcom,saw2";
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reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
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saw1_vreg: regulator {
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regulator-min-microvolt = <850000>;
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regulator-max-microvolt = <1300000>;
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};
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};
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clock-controller@4000000 {
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compatible = "qcom,mmcc-msm8960";
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reg = <0x4000000 0x1000>;
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#clock-cells = <1>;
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#power-domain-cells = <1>;
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#reset-cells = <1>;
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clocks = <&pxo_board>,
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<&gcc PLL3>,
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<&gcc PLL8_VOTE>,
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<0>,
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<0>,
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<0>,
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<0>,
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<0>;
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clock-names = "pxo",
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"pll3",
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"pll8_vote",
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"dsi1pll",
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"dsi1pllbyte",
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"dsi2pll",
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"dsi2pllbyte",
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"hdmipll";
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};
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sdcc3: mmc@12180000 {
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compatible = "arm,pl18x", "arm,primecell";
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reg = <0x12180000 0x2000>;
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arm,primecell-periphid = <0x00051180>;
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interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
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clock-names = "mclk", "apb_pclk";
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bus-width = <4>;
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cap-sd-highspeed;
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cap-mmc-highspeed;
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max-frequency = <192000000>;
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no-1-8-v;
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vmmc-supply = <&vsdcc_fixed>;
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dmas = <&sdcc3bam 2>, <&sdcc3bam 1>;
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dma-names = "tx", "rx";
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status = "disabled";
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};
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sdcc3bam: dma-controller@12182000 {
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compatible = "qcom,bam-v1.3.0";
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reg = <0x12182000 0x4000>;
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interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc SDC3_H_CLK>;
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clock-names = "bam_clk";
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#dma-cells = <1>;
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qcom,ee = <0>;
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};
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sdcc1: mmc@12400000 {
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compatible = "arm,pl18x", "arm,primecell";
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reg = <0x12400000 0x2000>;
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arm,primecell-periphid = <0x00051180>;
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interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
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clock-names = "mclk", "apb_pclk";
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bus-width = <8>;
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max-frequency = <96000000>;
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non-removable;
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cap-sd-highspeed;
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cap-mmc-highspeed;
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vmmc-supply = <&vsdcc_fixed>;
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dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
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dma-names = "tx", "rx";
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status = "disabled";
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};
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sdcc1bam: dma-controller@12402000 {
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compatible = "qcom,bam-v1.3.0";
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reg = <0x12402000 0x4000>;
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interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc SDC1_H_CLK>;
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clock-names = "bam_clk";
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#dma-cells = <1>;
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qcom,ee = <0>;
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};
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usb1: usb@12500000 {
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compatible = "qcom,ci-hdrc";
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reg = <0x12500000 0x200>,
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<0x12500200 0x200>;
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interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc USB_HS1_XCVR_CLK>, <&gcc USB_HS1_H_CLK>;
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clock-names = "core", "iface";
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assigned-clocks = <&gcc USB_HS1_XCVR_CLK>;
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assigned-clock-rates = <60000000>;
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resets = <&gcc USB_HS1_RESET>;
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reset-names = "core";
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phy_type = "ulpi";
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ahb-burst-config = <0>;
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phys = <&usb_hs1_phy>;
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phy-names = "usb-phy";
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#reset-cells = <1>;
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status = "disabled";
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ulpi {
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usb_hs1_phy: phy {
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compatible = "qcom,usb-hs-phy-msm8960",
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"qcom,usb-hs-phy";
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clocks = <&sleep_clk>, <&cxo_board>;
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clock-names = "sleep", "ref";
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resets = <&usb1 0>;
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reset-names = "por";
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#phy-cells = <0>;
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};
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};
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};
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gsbi1: gsbi@16000000 {
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compatible = "qcom,gsbi-v1.0.0";
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reg = <0x16000000 0x100>;
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ranges;
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cell-index = <1>;
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clocks = <&gcc GSBI1_H_CLK>;
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clock-names = "iface";
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#address-cells = <1>;
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#size-cells = <1>;
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status = "disabled";
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gsbi1_spi: spi@16080000 {
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compatible = "qcom,spi-qup-v1.1.1";
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reg = <0x16080000 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
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cs-gpios = <&msmgpio 8 0>;
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clocks = <&gcc GSBI1_QUP_CLK>,
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<&gcc GSBI1_H_CLK>;
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clock-names = "core",
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"iface";
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status = "disabled";
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};
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};
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gsbi3: gsbi@16200000 {
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compatible = "qcom,gsbi-v1.0.0";
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reg = <0x16200000 0x100>;
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ranges;
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cell-index = <3>;
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clocks = <&gcc GSBI3_H_CLK>;
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clock-names = "iface";
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#address-cells = <1>;
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#size-cells = <1>;
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status = "disabled";
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gsbi3_i2c: i2c@16280000 {
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compatible = "qcom,i2c-qup-v1.1.1";
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reg = <0x16280000 0x1000>;
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pinctrl-0 = <&i2c3_default_state>;
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pinctrl-1 = <&i2c3_sleep_state>;
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pinctrl-names = "default", "sleep";
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interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GSBI3_QUP_CLK>,
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<&gcc GSBI3_H_CLK>;
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clock-names = "core",
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"iface";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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};
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gsbi5: gsbi@16400000 {
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compatible = "qcom,gsbi-v1.0.0";
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reg = <0x16400000 0x100>;
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ranges;
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cell-index = <5>;
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clocks = <&gcc GSBI5_H_CLK>;
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clock-names = "iface";
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#address-cells = <1>;
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#size-cells = <1>;
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syscon-tcsr = <&tcsr>;
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status = "disabled";
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gsbi5_serial: serial@16440000 {
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compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
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reg = <0x16440000 0x1000>,
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<0x16400000 0x1000>;
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interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GSBI5_UART_CLK>,
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<&gcc GSBI5_H_CLK>;
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clock-names = "core",
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"iface";
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status = "disabled";
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};
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};
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gsbi8: gsbi@1a000000 {
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compatible = "qcom,gsbi-v1.0.0";
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reg = <0x1a000000 0x100>;
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ranges;
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cell-index = <8>;
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clocks = <&gcc GSBI8_H_CLK>;
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clock-names = "iface";
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#address-cells = <1>;
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#size-cells = <1>;
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syscon-tcsr = <&tcsr>;
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status = "disabled";
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gsbi8_serial: serial@1a040000 {
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compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
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reg = <0x1a040000 0x1000>,
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<0x1a000000 0x1000>;
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interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GSBI8_UART_CLK>,
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<&gcc GSBI8_H_CLK>;
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clock-names = "core",
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"iface";
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status = "disabled";
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};
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};
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tcsr: syscon@1a400000 {
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compatible = "qcom,tcsr-msm8960", "syscon";
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reg = <0x1a400000 0x100>;
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};
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rng@1a500000 {
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compatible = "qcom,prng";
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reg = <0x1a500000 0x200>;
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clocks = <&gcc PRNG_CLK>;
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clock-names = "core";
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};
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lcc: clock-controller@28000000 {
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compatible = "qcom,lcc-msm8960";
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reg = <0x28000000 0x1000>;
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#clock-cells = <1>;
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#reset-cells = <1>;
|
||||
clocks = <&pxo_board>,
|
||||
<&gcc PLL4_VOTE>,
|
||||
<0>,
|
||||
<0>,
|
||||
<0>,
|
||||
<0>,
|
||||
<0>,
|
||||
<0>;
|
||||
clock-names = "pxo",
|
||||
"pll4_vote",
|
||||
"mi2s_codec_clk",
|
||||
"codec_i2s_mic_codec_clk",
|
||||
"spare_i2s_mic_codec_clk",
|
||||
"codec_i2s_spkr_codec_clk",
|
||||
"spare_i2s_spkr_codec_clk",
|
||||
"pcm_codec_clk";
|
||||
};
|
||||
};
|
||||
|
||||
thermal-zones {
|
||||
cpu0-thermal {
|
||||
polling-delay-passive = <250>;
|
||||
|
|
@ -94,35 +528,6 @@ cpu_crit1: trip1 {
|
|||
};
|
||||
};
|
||||
|
||||
cpu-pmu {
|
||||
compatible = "qcom,krait-pmu";
|
||||
interrupts = <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
|
||||
qcom,no-pc-write;
|
||||
};
|
||||
|
||||
clocks {
|
||||
cxo_board: cxo_board {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <19200000>;
|
||||
clock-output-names = "cxo_board";
|
||||
};
|
||||
|
||||
pxo_board: pxo_board {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <27000000>;
|
||||
clock-output-names = "pxo_board";
|
||||
};
|
||||
|
||||
sleep_clk: sleep_clk {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <32768>;
|
||||
clock-output-names = "sleep_clk";
|
||||
};
|
||||
};
|
||||
|
||||
/* Temporary fixed regulator */
|
||||
vsdcc_fixed: vsdcc-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
|
|
@ -131,395 +536,5 @@ vsdcc_fixed: vsdcc-regulator {
|
|||
regulator-max-microvolt = <2700000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
soc: soc {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
compatible = "simple-bus";
|
||||
|
||||
intc: interrupt-controller@2000000 {
|
||||
compatible = "qcom,msm-qgic2";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <3>;
|
||||
reg = <0x02000000 0x1000>,
|
||||
<0x02002000 0x1000>;
|
||||
};
|
||||
|
||||
timer@200a000 {
|
||||
compatible = "qcom,kpss-wdt-msm8960", "qcom,kpss-timer",
|
||||
"qcom,msm-timer";
|
||||
interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>,
|
||||
<GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>,
|
||||
<GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>;
|
||||
reg = <0x0200a000 0x100>;
|
||||
clock-frequency = <27000000>;
|
||||
clocks = <&sleep_clk>;
|
||||
clock-names = "sleep";
|
||||
cpu-offset = <0x80000>;
|
||||
};
|
||||
|
||||
qfprom: efuse@700000 {
|
||||
compatible = "qcom,msm8960-qfprom", "qcom,qfprom";
|
||||
reg = <0x00700000 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
tsens_calib: calib@404 {
|
||||
reg = <0x404 0x10>;
|
||||
};
|
||||
|
||||
tsens_backup: backup-calib@414 {
|
||||
reg = <0x414 0x10>;
|
||||
};
|
||||
};
|
||||
|
||||
msmgpio: pinctrl@800000 {
|
||||
compatible = "qcom,msm8960-pinctrl";
|
||||
gpio-controller;
|
||||
gpio-ranges = <&msmgpio 0 0 152>;
|
||||
#gpio-cells = <2>;
|
||||
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x800000 0x4000>;
|
||||
};
|
||||
|
||||
gcc: clock-controller@900000 {
|
||||
compatible = "qcom,gcc-msm8960", "syscon";
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
reg = <0x900000 0x4000>;
|
||||
clocks = <&cxo_board>,
|
||||
<&pxo_board>,
|
||||
<&lcc PLL4>;
|
||||
clock-names = "cxo", "pxo", "pll4";
|
||||
|
||||
tsens: thermal-sensor {
|
||||
compatible = "qcom,msm8960-tsens";
|
||||
|
||||
nvmem-cells = <&tsens_calib>, <&tsens_backup>;
|
||||
nvmem-cell-names = "calib", "calib_backup";
|
||||
interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "uplow";
|
||||
|
||||
#qcom,sensors = <5>;
|
||||
#thermal-sensor-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
lcc: clock-controller@28000000 {
|
||||
compatible = "qcom,lcc-msm8960";
|
||||
reg = <0x28000000 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
clocks = <&pxo_board>,
|
||||
<&gcc PLL4_VOTE>,
|
||||
<0>,
|
||||
<0>, <0>,
|
||||
<0>, <0>,
|
||||
<0>;
|
||||
clock-names = "pxo",
|
||||
"pll4_vote",
|
||||
"mi2s_codec_clk",
|
||||
"codec_i2s_mic_codec_clk",
|
||||
"spare_i2s_mic_codec_clk",
|
||||
"codec_i2s_spkr_codec_clk",
|
||||
"spare_i2s_spkr_codec_clk",
|
||||
"pcm_codec_clk";
|
||||
};
|
||||
|
||||
clock-controller@4000000 {
|
||||
compatible = "qcom,mmcc-msm8960";
|
||||
reg = <0x4000000 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
clocks = <&pxo_board>,
|
||||
<&gcc PLL3>,
|
||||
<&gcc PLL8_VOTE>,
|
||||
<0>,
|
||||
<0>,
|
||||
<0>,
|
||||
<0>,
|
||||
<0>;
|
||||
clock-names = "pxo",
|
||||
"pll3",
|
||||
"pll8_vote",
|
||||
"dsi1pll",
|
||||
"dsi1pllbyte",
|
||||
"dsi2pll",
|
||||
"dsi2pllbyte",
|
||||
"hdmipll";
|
||||
};
|
||||
|
||||
l2cc: clock-controller@2011000 {
|
||||
compatible = "qcom,kpss-gcc-msm8960", "qcom,kpss-gcc", "syscon";
|
||||
reg = <0x2011000 0x1000>;
|
||||
clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
|
||||
clock-names = "pll8_vote", "pxo";
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
|
||||
rpm: rpm@108000 {
|
||||
compatible = "qcom,rpm-msm8960";
|
||||
reg = <0x108000 0x1000>;
|
||||
qcom,ipc = <&l2cc 0x8 2>;
|
||||
|
||||
interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
|
||||
interrupt-names = "ack", "err", "wakeup";
|
||||
};
|
||||
|
||||
acc0: clock-controller@2088000 {
|
||||
compatible = "qcom,kpss-acc-v1";
|
||||
reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
|
||||
clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
|
||||
clock-names = "pll8_vote", "pxo";
|
||||
clock-output-names = "acpu0_aux";
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
|
||||
acc1: clock-controller@2098000 {
|
||||
compatible = "qcom,kpss-acc-v1";
|
||||
reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
|
||||
clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
|
||||
clock-names = "pll8_vote", "pxo";
|
||||
clock-output-names = "acpu1_aux";
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
|
||||
saw0: power-manager@2089000 {
|
||||
compatible = "qcom,msm8960-saw2-cpu", "qcom,saw2";
|
||||
reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
|
||||
|
||||
saw0_vreg: regulator {
|
||||
regulator-min-microvolt = <850000>;
|
||||
regulator-max-microvolt = <1300000>;
|
||||
};
|
||||
};
|
||||
|
||||
saw1: power-manager@2099000 {
|
||||
compatible = "qcom,msm8960-saw2-cpu", "qcom,saw2";
|
||||
reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
|
||||
|
||||
saw1_vreg: regulator {
|
||||
regulator-min-microvolt = <850000>;
|
||||
regulator-max-microvolt = <1300000>;
|
||||
};
|
||||
};
|
||||
|
||||
gsbi5: gsbi@16400000 {
|
||||
compatible = "qcom,gsbi-v1.0.0";
|
||||
cell-index = <5>;
|
||||
reg = <0x16400000 0x100>;
|
||||
clocks = <&gcc GSBI5_H_CLK>;
|
||||
clock-names = "iface";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
syscon-tcsr = <&tcsr>;
|
||||
|
||||
status = "disabled";
|
||||
|
||||
gsbi5_serial: serial@16440000 {
|
||||
compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
|
||||
reg = <0x16440000 0x1000>,
|
||||
<0x16400000 0x1000>;
|
||||
interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
|
||||
clock-names = "core", "iface";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
gsbi8: gsbi@1a000000 {
|
||||
compatible = "qcom,gsbi-v1.0.0";
|
||||
cell-index = <8>;
|
||||
reg = <0x1a000000 0x100>;
|
||||
clocks = <&gcc GSBI8_H_CLK>;
|
||||
clock-names = "iface";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
syscon-tcsr = <&tcsr>;
|
||||
|
||||
status = "disabled";
|
||||
|
||||
gsbi8_serial: serial@1a040000 {
|
||||
compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
|
||||
reg = <0x1a040000 0x1000>,
|
||||
<0x1a000000 0x1000>;
|
||||
interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&gcc GSBI8_UART_CLK>,
|
||||
<&gcc GSBI8_H_CLK>;
|
||||
clock-names = "core",
|
||||
"iface";
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
ssbi: ssbi@500000 {
|
||||
compatible = "qcom,ssbi";
|
||||
reg = <0x500000 0x1000>;
|
||||
qcom,controller-type = "pmic-arbiter";
|
||||
};
|
||||
|
||||
rng@1a500000 {
|
||||
compatible = "qcom,prng";
|
||||
reg = <0x1a500000 0x200>;
|
||||
clocks = <&gcc PRNG_CLK>;
|
||||
clock-names = "core";
|
||||
};
|
||||
|
||||
sdcc3: mmc@12180000 {
|
||||
compatible = "arm,pl18x", "arm,primecell";
|
||||
arm,primecell-periphid = <0x00051180>;
|
||||
status = "disabled";
|
||||
reg = <0x12180000 0x2000>;
|
||||
interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
|
||||
clock-names = "mclk", "apb_pclk";
|
||||
bus-width = <4>;
|
||||
cap-sd-highspeed;
|
||||
cap-mmc-highspeed;
|
||||
max-frequency = <192000000>;
|
||||
no-1-8-v;
|
||||
vmmc-supply = <&vsdcc_fixed>;
|
||||
dmas = <&sdcc3bam 2>, <&sdcc3bam 1>;
|
||||
dma-names = "tx", "rx";
|
||||
};
|
||||
|
||||
sdcc3bam: dma-controller@12182000 {
|
||||
compatible = "qcom,bam-v1.3.0";
|
||||
reg = <0x12182000 0x4000>;
|
||||
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&gcc SDC3_H_CLK>;
|
||||
clock-names = "bam_clk";
|
||||
#dma-cells = <1>;
|
||||
qcom,ee = <0>;
|
||||
};
|
||||
|
||||
sdcc1: mmc@12400000 {
|
||||
status = "disabled";
|
||||
compatible = "arm,pl18x", "arm,primecell";
|
||||
arm,primecell-periphid = <0x00051180>;
|
||||
reg = <0x12400000 0x2000>;
|
||||
interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
|
||||
clock-names = "mclk", "apb_pclk";
|
||||
bus-width = <8>;
|
||||
max-frequency = <96000000>;
|
||||
non-removable;
|
||||
cap-sd-highspeed;
|
||||
cap-mmc-highspeed;
|
||||
vmmc-supply = <&vsdcc_fixed>;
|
||||
dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
|
||||
dma-names = "tx", "rx";
|
||||
};
|
||||
|
||||
sdcc1bam: dma-controller@12402000 {
|
||||
compatible = "qcom,bam-v1.3.0";
|
||||
reg = <0x12402000 0x4000>;
|
||||
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&gcc SDC1_H_CLK>;
|
||||
clock-names = "bam_clk";
|
||||
#dma-cells = <1>;
|
||||
qcom,ee = <0>;
|
||||
};
|
||||
|
||||
tcsr: syscon@1a400000 {
|
||||
compatible = "qcom,tcsr-msm8960", "syscon";
|
||||
reg = <0x1a400000 0x100>;
|
||||
};
|
||||
|
||||
gsbi1: gsbi@16000000 {
|
||||
compatible = "qcom,gsbi-v1.0.0";
|
||||
cell-index = <1>;
|
||||
reg = <0x16000000 0x100>;
|
||||
clocks = <&gcc GSBI1_H_CLK>;
|
||||
clock-names = "iface";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
status = "disabled";
|
||||
|
||||
gsbi1_spi: spi@16080000 {
|
||||
compatible = "qcom,spi-qup-v1.1.1";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x16080000 0x1000>;
|
||||
interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
|
||||
cs-gpios = <&msmgpio 8 0>;
|
||||
|
||||
clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
|
||||
clock-names = "core", "iface";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
usb1: usb@12500000 {
|
||||
compatible = "qcom,ci-hdrc";
|
||||
reg = <0x12500000 0x200>,
|
||||
<0x12500200 0x200>;
|
||||
interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&gcc USB_HS1_XCVR_CLK>, <&gcc USB_HS1_H_CLK>;
|
||||
clock-names = "core", "iface";
|
||||
assigned-clocks = <&gcc USB_HS1_XCVR_CLK>;
|
||||
assigned-clock-rates = <60000000>;
|
||||
resets = <&gcc USB_HS1_RESET>;
|
||||
reset-names = "core";
|
||||
phy_type = "ulpi";
|
||||
ahb-burst-config = <0>;
|
||||
phys = <&usb_hs1_phy>;
|
||||
phy-names = "usb-phy";
|
||||
#reset-cells = <1>;
|
||||
status = "disabled";
|
||||
|
||||
ulpi {
|
||||
usb_hs1_phy: phy {
|
||||
compatible = "qcom,usb-hs-phy-msm8960",
|
||||
"qcom,usb-hs-phy";
|
||||
clocks = <&sleep_clk>, <&cxo_board>;
|
||||
clock-names = "sleep", "ref";
|
||||
resets = <&usb1 0>;
|
||||
reset-names = "por";
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
gsbi3: gsbi@16200000 {
|
||||
compatible = "qcom,gsbi-v1.0.0";
|
||||
reg = <0x16200000 0x100>;
|
||||
ranges;
|
||||
cell-index = <3>;
|
||||
clocks = <&gcc GSBI3_H_CLK>;
|
||||
clock-names = "iface";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
status = "disabled";
|
||||
|
||||
gsbi3_i2c: i2c@16280000 {
|
||||
compatible = "qcom,i2c-qup-v1.1.1";
|
||||
reg = <0x16280000 0x1000>;
|
||||
pinctrl-0 = <&i2c3_default_state>;
|
||||
pinctrl-1 = <&i2c3_sleep_state>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&gcc GSBI3_QUP_CLK>,
|
||||
<&gcc GSBI3_H_CLK>;
|
||||
clock-names = "core", "iface";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
#include "qcom-msm8960-pins.dtsi"
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user