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perf vendor events amd: Add Zen 6 uncore events
Add uncore events taken from Section 1.6 "L3 Cache Performance Monitor Counters" and Section 2.2 "UMC Performance Monitor Events" of the Performance Monitor Counters for AMD Family 1Ah Model 50h-57h Processors document available at the link below. This constitutes events which capture L3 cache and UMC command activity. Reviewed-by: Ian Rogers <irogers@google.com> Signed-off-by: Sandipan Das <sandipan.das@amd.com> Cc: Adrian Hunter <adrian.hunter@intel.com> Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: Ananth Narayan <ananth.narayan@amd.com> Cc: Caleb Biggers <caleb.biggers@intel.com> Cc: Ingo Molnar <mingo@redhat.com> Cc: James Clark <james.clark@linaro.org> Cc: Jiri Olsa <jolsa@kernel.org> Cc: Kan Liang <kan.liang@linux.intel.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Namhyung Kim <namhyung@kernel.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Ravi Bangoria <ravi.bangoria@amd.com> Cc: Stephane Eranian <eranian@google.com> Link: https://bugzilla.kernel.org/attachment.cgi?id=309149 Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
This commit is contained in:
Sandipan Das
Arnaldo Carvalho de Melo
parent
2f42fb0661
commit
de18394f8f
177
tools/perf/pmu-events/arch/x86/amdzen6/l3-cache.json
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177
tools/perf/pmu-events/arch/x86/amdzen6/l3-cache.json
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[
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{
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"EventName": "l3_lookup_state.l3_miss",
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"EventCode": "0x04",
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"BriefDescription": "L3 cache misses.",
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"UMask": "0x01",
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"Unit": "L3PMC"
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},
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{
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"EventName": "l3_lookup_state.l3_hit",
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"EventCode": "0x04",
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"BriefDescription": "L3 cache hits.",
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"UMask": "0xfe",
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"Unit": "L3PMC"
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},
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{
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"EventName": "l3_lookup_state.all_coherent_accesses_to_l3",
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"EventCode": "0x04",
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"BriefDescription": "L3 cache requests for all coherent accesses.",
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"UMask": "0xff",
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"Unit": "L3PMC"
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},
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{
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"EventName": "l3_xi_sampled_latency.dram_near",
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"EventCode": "0xac",
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"BriefDescription": "Average sampled latency for L3 requests where data is returned from DRAM in the same NUMA node.",
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"UMask": "0x01",
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"EnAllCores": "0x1",
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"EnAllSlices": "0x1",
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"SliceId": "0x3",
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"ThreadMask": "0x3",
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"Unit": "L3PMC"
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},
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{
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"EventName": "l3_xi_sampled_latency.dram_far",
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"EventCode": "0xac",
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"BriefDescription": "Average sampled latency for L3 requests where data is returned from DRAM in a different NUMA node.",
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"UMask": "0x02",
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"EnAllCores": "0x1",
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"EnAllSlices": "0x1",
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"SliceId": "0x3",
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"ThreadMask": "0x3",
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"Unit": "L3PMC"
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},
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{
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"EventName": "l3_xi_sampled_latency.near_cache",
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"EventCode": "0xac",
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"BriefDescription": "Average sampled latency for L3 requests where data is returned from cache of another CCX in the same NUMA node.",
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"UMask": "0x04",
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"EnAllCores": "0x1",
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"EnAllSlices": "0x1",
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"SliceId": "0x3",
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"ThreadMask": "0x3",
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"Unit": "L3PMC"
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},
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{
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"EventName": "l3_xi_sampled_latency.far_cache",
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"EventCode": "0xac",
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"BriefDescription": "Average sampled latency for L3 requests where data is returned from cache of another CCX in a different NUMA node.",
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"UMask": "0x08",
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"EnAllCores": "0x1",
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"EnAllSlices": "0x1",
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"SliceId": "0x3",
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"ThreadMask": "0x3",
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"Unit": "L3PMC"
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},
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{
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"EventName": "l3_xi_sampled_latency.ext_near",
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"EventCode": "0xac",
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"BriefDescription": "Average sampled latency for L3 requests where data is returned from extension memory (CXL) in the same NUMA node.",
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"UMask": "0x10",
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"EnAllCores": "0x1",
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"EnAllSlices": "0x1",
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"SliceId": "0x3",
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"ThreadMask": "0x3",
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"Unit": "L3PMC"
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},
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{
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"EventName": "l3_xi_sampled_latency.ext_far",
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"EventCode": "0xac",
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"BriefDescription": "Average sampled latency for L3 requests where data is returned from extension memory (CXL) in a different NUMA node.",
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"UMask": "0x20",
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"EnAllCores": "0x1",
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"EnAllSlices": "0x1",
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"SliceId": "0x3",
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"ThreadMask": "0x3",
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"Unit": "L3PMC"
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},
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{
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"EventName": "l3_xi_sampled_latency.all",
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"EventCode": "0xac",
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"BriefDescription": "Average sampled latency for L3 requests where data is returned from all types of sources.",
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"UMask": "0x3f",
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"EnAllCores": "0x1",
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"EnAllSlices": "0x1",
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"SliceId": "0x3",
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"ThreadMask": "0x3",
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"Unit": "L3PMC"
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},
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{
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"EventName": "l3_xi_sampled_latency_requests.dram_near",
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"EventCode": "0xad",
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"BriefDescription": "Average sampled L3 requests where data is returned from DRAM in the same NUMA node.",
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"UMask": "0x01",
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"EnAllCores": "0x1",
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"EnAllSlices": "0x1",
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"SliceId": "0x3",
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"ThreadMask": "0x3",
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"Unit": "L3PMC"
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},
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{
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"EventName": "l3_xi_sampled_latency_requests.dram_far",
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"EventCode": "0xad",
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"BriefDescription": "Average sampled L3 requests where data is returned from DRAM in a different NUMA node.",
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"UMask": "0x02",
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"EnAllCores": "0x1",
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"EnAllSlices": "0x1",
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"SliceId": "0x3",
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"ThreadMask": "0x3",
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"Unit": "L3PMC"
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},
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{
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"EventName": "l3_xi_sampled_latency_requests.near_cache",
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"EventCode": "0xad",
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"BriefDescription": "Average sampled L3 requests where data is returned from cache of another CCX in the same NUMA node.",
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"UMask": "0x04",
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"EnAllCores": "0x1",
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"EnAllSlices": "0x1",
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"SliceId": "0x3",
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"ThreadMask": "0x3",
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"Unit": "L3PMC"
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},
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{
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"EventName": "l3_xi_sampled_latency_requests.far_cache",
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"EventCode": "0xad",
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"BriefDescription": "Average sampled L3 requests where data is returned from cache of another CCX in a different NUMA node.",
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"UMask": "0x08",
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"EnAllCores": "0x1",
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"EnAllSlices": "0x1",
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"SliceId": "0x3",
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"ThreadMask": "0x3",
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"Unit": "L3PMC"
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},
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{
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"EventName": "l3_xi_sampled_latency_requests.ext_near",
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"EventCode": "0xad",
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"BriefDescription": "Average sampled L3 requests where data is returned from extension memory (CXL) in the same NUMA node.",
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"UMask": "0x10",
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"EnAllCores": "0x1",
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"EnAllSlices": "0x1",
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"SliceId": "0x3",
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"ThreadMask": "0x3",
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"Unit": "L3PMC"
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},
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{
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"EventName": "l3_xi_sampled_latency_requests.ext_far",
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"EventCode": "0xad",
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"BriefDescription": "Average sampled L3 requests where data is returned from extension memory (CXL) in a different NUMA node.",
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"UMask": "0x20",
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"EnAllCores": "0x1",
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"EnAllSlices": "0x1",
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"SliceId": "0x3",
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"ThreadMask": "0x3",
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"Unit": "L3PMC"
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},
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{
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"EventName": "l3_xi_sampled_latency_requests.all",
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"EventCode": "0xad",
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"BriefDescription": "Average sampled L3 requests where data is returned from all types of sources.",
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"UMask": "0x3f",
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"EnAllCores": "0x1",
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"EnAllSlices": "0x1",
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"SliceId": "0x3",
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"ThreadMask": "0x3",
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"Unit": "L3PMC"
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}
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]
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101
tools/perf/pmu-events/arch/x86/amdzen6/memory-controller.json
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101
tools/perf/pmu-events/arch/x86/amdzen6/memory-controller.json
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[
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{
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"EventName": "umc_mem_clk",
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"PublicDescription": "Memory clock (MEMCLK) cycles.",
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"EventCode": "0x00",
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"PerPkg": "1",
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"Unit": "UMCPMC"
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},
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{
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"EventName": "umc_act_cmd.all",
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"PublicDescription": "ACTIVATE commands sent.",
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"EventCode": "0x05",
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"PerPkg": "1",
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"Unit": "UMCPMC"
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},
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{
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"EventName": "umc_act_cmd.rd",
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"PublicDescription": "ACTIVATE commands sent for reads.",
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"EventCode": "0x05",
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"RdWrMask": "0x1",
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"PerPkg": "1",
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"Unit": "UMCPMC"
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},
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{
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"EventName": "umc_act_cmd.wr",
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"PublicDescription": "ACTIVATE commands sent for writes.",
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"EventCode": "0x05",
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"RdWrMask": "0x2",
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"PerPkg": "1",
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"Unit": "UMCPMC"
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},
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{
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"EventName": "umc_pchg_cmd.all",
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"PublicDescription": "PRECHARGE commands sent.",
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"EventCode": "0x06",
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"PerPkg": "1",
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"Unit": "UMCPMC"
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},
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{
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"EventName": "umc_pchg_cmd.rd",
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"PublicDescription": "PRECHARGE commands sent for reads.",
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"EventCode": "0x06",
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"RdWrMask": "0x1",
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"PerPkg": "1",
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"Unit": "UMCPMC"
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},
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{
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"EventName": "umc_pchg_cmd.wr",
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"PublicDescription": "PRECHARGE commands sent for writes.",
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"EventCode": "0x06",
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"RdWrMask": "0x2",
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"PerPkg": "1",
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"Unit": "UMCPMC"
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},
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{
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"EventName": "umc_cas_cmd.all",
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"PublicDescription": "CAS commands sent.",
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"EventCode": "0x0a",
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"PerPkg": "1",
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"Unit": "UMCPMC"
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},
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{
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"EventName": "umc_cas_cmd.rd",
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"PublicDescription": "CAS commands sent for reads.",
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"EventCode": "0x0a",
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"RdWrMask": "0x1",
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"PerPkg": "1",
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"Unit": "UMCPMC"
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},
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{
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"EventName": "umc_cas_cmd.wr",
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"PublicDescription": "CAS commands sent for writes.",
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"EventCode": "0x0a",
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"RdWrMask": "0x2",
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"PerPkg": "1",
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"Unit": "UMCPMC"
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},
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{
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"EventName": "umc_data_slot_clks.all",
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"PublicDescription": "Clock cycles where the data bus is utilized.",
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"EventCode": "0x14",
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"PerPkg": "1",
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"Unit": "UMCPMC"
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},
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{
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"EventName": "umc_data_slot_clks.rd",
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"PublicDescription": "Clock cycles where the data bus is utilized for reads.",
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"EventCode": "0x14",
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"RdWrMask": "0x1",
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"PerPkg": "1",
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"Unit": "UMCPMC"
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},
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{
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"EventName": "umc_data_slot_clks.wr",
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"PublicDescription": "Clock cycles where the data bus is utilized for writes.",
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"EventCode": "0x14",
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"RdWrMask": "0x2",
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"PerPkg": "1",
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"Unit": "UMCPMC"
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}
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]
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