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perf vendor events amd: Add Zen 6 core events
Add core events taken from Section 1.5 "Core Performance Monitor Counters" of the Performance Monitor Counters for AMD Family 1Ah Model 50h-57h Processors document available at the link below. This constitutes events which capture information on op dispatch, execution and retirement, branch prediction, L1 and L2 cache activity, TLB activity, etc. Reviewed-by: Ian Rogers <irogers@google.com> Signed-off-by: Sandipan Das <sandipan.das@amd.com> Cc: Adrian Hunter <adrian.hunter@intel.com> Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: Ananth Narayan <ananth.narayan@amd.com> Cc: Caleb Biggers <caleb.biggers@intel.com> Cc: Ingo Molnar <mingo@redhat.com> Cc: James Clark <james.clark@linaro.org> Cc: Jiri Olsa <jolsa@kernel.org> Cc: Kan Liang <kan.liang@linux.intel.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Namhyung Kim <namhyung@kernel.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Ravi Bangoria <ravi.bangoria@amd.com> Cc: Stephane Eranian <eranian@google.com> Link: https://bugzilla.kernel.org/attachment.cgi?id=309149 Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
This commit is contained in:
Sandipan Das
Arnaldo Carvalho de Melo
parent
2c3cd43d27
commit
2f42fb0661
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@ -0,0 +1,93 @@
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[
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{
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"EventName": "bp_l1_tlb_miss_l2_tlb_hit",
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"EventCode": "0x84",
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"BriefDescription": "Instruction fetches that miss in the L1 ITLB but hit in the L2 ITLB."
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},
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{
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"EventName": "bp_l1_tlb_miss_l2_tlb_miss.if4k",
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"EventCode": "0x85",
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"BriefDescription": "Instruction fetches that miss in both the L1 and L2 ITLBs (page-table walks requested) for 4k pages.",
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"UMask": "0x01"
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},
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{
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"EventName": "bp_l1_tlb_miss_l2_tlb_miss.if2m",
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"EventCode": "0x85",
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"BriefDescription": "Instruction fetches that miss in both the L1 and L2 ITLBs (page-table walks requested) for 2M pages.",
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"UMask": "0x02"
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},
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{
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"EventName": "bp_l1_tlb_miss_l2_tlb_miss.if1g",
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"EventCode": "0x85",
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"BriefDescription": "Instruction fetches that miss in both the L1 and L2 ITLBs (page-table walks requested) for 1G pages.",
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"UMask": "0x04"
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},
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{
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"EventName": "bp_l1_tlb_miss_l2_tlb_miss.coalesced_4k",
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"EventCode": "0x85",
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"BriefDescription": "Instruction fetches that miss in both the L1 and L2 ITLBs (page-table walks requested) for coalesced pages (16k pages created from four adjacent 4k pages).",
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"UMask": "0x08"
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},
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{
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"EventName": "bp_l1_tlb_miss_l2_tlb_miss.all",
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"EventCode": "0x85",
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"BriefDescription": "Instruction fetches that miss in both the L1 and L2 ITLBs (page-table walks requested) for all page sizes.",
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"UMask": "0x0f"
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},
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{
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"EventName": "bp_pipe_correct",
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"EventCode": "0x8b",
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"BriefDescription": "Branch predictor pipeline flushes due to internal conditions such as a second level prediction structure."
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},
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{
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"EventName": "bp_var_target_pred",
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"EventCode": "0x8e",
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"BriefDescription": "Indirect predictions (branch used the indirect predictor to make a prediction)."
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},
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{
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"EventName": "bp_early_redir",
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"EventCode": "0x91",
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"BriefDescription": "Early redirects sent to branch predictor. This happens when either the decoder or dispatch logic is able to detect that the branch predictor needs to be redirected."
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},
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{
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"EventName": "bp_l1_tlb_fetch_hit.if4k",
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"EventCode": "0x94",
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"BriefDescription": "Instruction fetches that hit in the L1 ITLB for 4k or coalesced pages (16k pages created from four adjacent 4k pages).",
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"UMask": "0x01"
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},
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{
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"EventName": "bp_l1_tlb_fetch_hit.if2m",
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"EventCode": "0x94",
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"BriefDescription": "Instruction fetches that hit in the L1 ITLB for 2M pages.",
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"UMask": "0x02"
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},
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{
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"EventName": "bp_l1_tlb_fetch_hit.if1g",
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"EventCode": "0x94",
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"BriefDescription": "Instruction fetches that hit in the L1 ITLB for 1G pages.",
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"UMask": "0x04"
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},
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{
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"EventName": "bp_l1_tlb_fetch_hit.all",
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"EventCode": "0x94",
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"BriefDescription": "Instruction fetches that hit in the L1 ITLB for all page sizes.",
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"UMask": "0x07"
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},
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{
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"EventName": "bp_fe_redir.resync",
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"EventCode": "0x9f",
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"BriefDescription": "Redirects of the pipeline frontend caused by resyncs. These are retire time pipeline restarts.",
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"UMask": "0x01"
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},
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{
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"EventName": "bp_fe_redir.ex_redir",
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"EventCode": "0x9f",
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"BriefDescription": "Redirects of the pipeline frontend caused by mispredicts. These are used for branch direction correction and handling indirect branch target mispredicts.",
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"UMask": "0x02"
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},
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{
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"EventName": "bp_fe_redir.all",
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"EventCode": "0x9f",
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"BriefDescription": "Redirects of the pipeline frontend caused by any reason."
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}
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]
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139
tools/perf/pmu-events/arch/x86/amdzen6/decode.json
Normal file
139
tools/perf/pmu-events/arch/x86/amdzen6/decode.json
Normal file
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@ -0,0 +1,139 @@
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[
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{
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"EventName": "de_op_queue_empty",
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"EventCode": "0xa9",
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"BriefDescription": "Cycles where the op queue is empty. Such cycles indicate that the frontend is not delivering instructions fast enough."
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},
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{
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"EventName": "de_src_op_disp.x86_decoder",
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"EventCode": "0xaa",
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"BriefDescription": "Ops dispatched from x86 decoder.",
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"UMask": "0x01"
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},
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{
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"EventName": "de_src_op_disp.op_cache",
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"EventCode": "0xaa",
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"BriefDescription": "Ops dispatched from op cache.",
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"UMask": "0x02"
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},
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{
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"EventName": "de_src_op_disp.all",
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"EventCode": "0xaa",
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"BriefDescription": "Ops dispatched from any source.",
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"UMask": "0x07"
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},
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{
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"EventName": "de_dis_ops_from_decoder.any_fp",
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"EventCode": "0xab",
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"BriefDescription": "Ops dispatched from the decoder to a floating-point unit.",
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"UMask": "0x04"
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},
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{
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"EventName": "de_dis_ops_from_decoder.any_int",
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"EventCode": "0xab",
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"BriefDescription": "Ops dispatched from the decoder to an integer unit.",
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"UMask": "0x08"
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},
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{
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"EventName": "de_disp_stall_cycles_dynamic_tokens_part1.int_phy_reg_file_rsrc_stall",
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"EventCode": "0xae",
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"BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to integer physical register file resource stalls.",
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"UMask": "0x01"
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},
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{
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"EventName": "de_dispatch_stall_cycle_dynamic_tokens_part1.load_queue_rsrc_stall",
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"EventCode": "0xae",
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"BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to load queue token stalls.",
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"UMask": "0x02"
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},
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{
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"EventName": "de_dispatch_stall_cycle_dynamic_tokens_part1.store_queue_rsrc_stall",
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"EventCode": "0xae",
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"BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to store queue token stalls.",
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"UMask": "0x04"
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},
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{
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"EventName": "de_dispatch_stall_cycle_dynamic_tokens_part1.taken_brnch_buffer_rsrc",
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"EventCode": "0xae",
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"BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to taken branch buffer resource stalls.",
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"UMask": "0x10"
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},
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{
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"EventName": "de_dispatch_stall_cycle_dynamic_tokens_part1.fp_sch_rsrc_stall",
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"EventCode": "0xae",
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"BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to floating-point non-schedulable queue token stalls.",
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"UMask": "0x40"
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},
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{
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"EventName": "de_dispatch_stall_cycle_dynamic_tokens_part2.int_sq0",
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"EventCode": "0xaf",
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"BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to unavailability of integer scheduler 0 tokens.",
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"UMask": "0x01"
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},
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{
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"EventName": "de_dispatch_stall_cycle_dynamic_tokens_part2.int_sq1",
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"EventCode": "0xaf",
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"BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to unavailability of integer scheduler 1 tokens.",
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"UMask": "0x02"
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},
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{
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"EventName": "de_dispatch_stall_cycle_dynamic_tokens_part2.int_sq2",
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"EventCode": "0xaf",
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"BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to unavailability of integer scheduler 2 tokens.",
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"UMask": "0x04"
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},
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{
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"EventName": "de_dispatch_stall_cycle_dynamic_tokens_part2.int_sq3",
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"EventCode": "0xaf",
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"BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to unavailability of integer scheduler 3 tokens.",
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"UMask": "0x08"
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},
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{
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"EventName": "de_dispatch_stall_cycle_dynamic_tokens_part2.int_sq4",
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"EventCode": "0xaf",
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"BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to unavailability of integer scheduler 4 tokens.",
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"UMask": "0x10"
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},
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{
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"EventName": "de_dispatch_stall_cycle_dynamic_tokens_part2.int_sq5",
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"EventCode": "0xaf",
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"BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to unavailability of integer scheduler 5 tokens.",
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"UMask": "0x20"
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},
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{
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"EventName": "de_dispatch_stall_cycle_dynamic_tokens_part2.ret_q",
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"EventCode": "0xaf",
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"BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to unavailability of retire queue tokens.",
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"UMask": "0x80"
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},
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{
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"EventName": "de_dispatch_stall_cycle_dynamic_tokens_part2.all",
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"EventCode": "0xaf",
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"BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to any token stalls.",
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"UMask": "0xbf"
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},
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{
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"EventName": "de_no_dispatch_per_slot.no_ops_from_frontend",
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"EventCode": "0x1a0",
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"BriefDescription": "Dispatch slots in each cycle that were empty because the frontend did not supply ops.",
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"UMask": "0x01"
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},
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{
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"EventName": "de_no_dispatch_per_slot.backend_stalls",
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"EventCode": "0x1a0",
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"BriefDescription": "Dispatch slots in each cycle that were unused because of backend stalls.",
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"UMask": "0x1e"
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},
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{
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"EventName": "de_no_dispatch_per_slot.smt_contention",
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"EventCode": "0x1a0",
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"BriefDescription": "Dispatch slots in each cycle that were unused because the dispatch cycle was granted to the other SMT thread.",
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"UMask": "0x60"
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},
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{
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"EventName": "de_additional_resource_stalls.dispatch_stalls",
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"EventCode": "0x1a2",
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"BriefDescription": "Counts additional cycles where dispatch is stalled due to a lack of dispatch resources.",
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"UMask": "0x30"
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}
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]
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192
tools/perf/pmu-events/arch/x86/amdzen6/execution.json
Normal file
192
tools/perf/pmu-events/arch/x86/amdzen6/execution.json
Normal file
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[
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{
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"EventName": "ex_ret_instr",
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"EventCode": "0xc0",
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"BriefDescription": "Retired instructions."
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},
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{
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"EventName": "ex_ret_ops",
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"EventCode": "0xc1",
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"BriefDescription": "Retired macro-ops."
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},
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{
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"EventName": "ex_ret_brn",
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"EventCode": "0xc2",
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"BriefDescription": "Retired branch instructions (all types of architectural control flow changes, including exceptions and interrupts)."
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},
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{
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"EventName": "ex_ret_brn_misp",
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"EventCode": "0xc3",
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"BriefDescription": "Retired branch instructions that were mispredicted."
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},
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{
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"EventName": "ex_ret_brn_tkn",
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"EventCode": "0xc4",
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"BriefDescription": "Retired taken branch instructions (all types of architectural control flow changes, including exceptions and interrupts)."
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},
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{
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"EventName": "ex_ret_brn_tkn_misp",
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"EventCode": "0xc5",
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"BriefDescription": "Retired taken branch instructions that were mispredicted."
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},
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{
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"EventName": "ex_ret_brn_far",
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"EventCode": "0xc6",
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"BriefDescription": "Retired far control transfers (far call, far jump, far return, IRET, SYSCALL and SYSRET, plus exceptions and interrupts). Far control transfers are not subject to branch prediction."
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},
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{
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"EventName": "ex_ret_near_ret",
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"EventCode": "0xc8",
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"BriefDescription": "Retired near returns (RET or RET Iw)."
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},
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{
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"EventName": "ex_ret_near_ret_mispred",
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"EventCode": "0xc9",
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"BriefDescription": "Retired near returns that were mispredicted. Each misprediction incurs the same penalty as that of a mispredicted conditional branch instruction."
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},
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{
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"EventName": "ex_ret_brn_ind_misp",
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"EventCode": "0xca",
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"BriefDescription": "Retired indirect branch instructions that were mispredicted (only EX mispredicts). Each misprediction incurs the same penalty as that of a mispredicted conditional branch instruction."
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},
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{
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"EventName": "ex_ret_brn_ind",
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"EventCode": "0xcc",
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"BriefDescription": "Retired indirect branch instructions."
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},
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{
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"EventName": "ex_ret_brn_cond",
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"EventCode": "0xd1",
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"BriefDescription": "Retired conditional branch instructions."
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},
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{
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"EventName": "ex_div_busy",
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"EventCode": "0xd3",
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"BriefDescription": "Cycles where the divider is busy."
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},
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{
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"EventName": "ex_div_count",
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"EventCode": "0xd4",
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"BriefDescription": "Divide ops executed."
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},
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{
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"EventName": "ex_no_retire.empty",
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"EventCode": "0xd6",
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"BriefDescription": "Cycles where the thread does not retire any ops due to a lack of valid ops in the retire queue (may be caused by front-end bottlenecks or pipeline redirects).",
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"UMask": "0x01"
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},
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{
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"EventName": "ex_no_retire.not_complete",
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"EventCode": "0xd6",
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"BriefDescription": "Cycles where the thread does not retire any ops as the oldest retire slot is waiting to be marked as completed.",
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"UMask": "0x02"
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},
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{
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"EventName": "ex_no_retire.other",
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"EventCode": "0xd6",
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"BriefDescription": "Cycles where the thread does not retire any ops due to other reasons (retire breaks, traps, faults, etc.).",
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"UMask": "0x08"
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},
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{
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"EventName": "ex_no_retire.thread_not_selected",
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"EventCode": "0xd6",
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"BriefDescription": "Cycles where the thread does not retire any ops as thread arbitration did not select the current thread.",
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"UMask": "0x10"
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},
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{
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"EventName": "ex_no_retire.load_not_complete",
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"EventCode": "0xd6",
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"BriefDescription": "Cycles where the thread does not retire any ops due to missing load completion.",
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"UMask": "0xa2"
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},
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{
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"EventName": "ex_ret_ucode_instr",
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"EventCode": "0x1c1",
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"BriefDescription": "Retired microcoded instructions."
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},
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{
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"EventName": "ex_ret_ucode_ops",
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"EventCode": "0x1c2",
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"BriefDescription": "Retired microcode ops."
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},
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{
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"EventName": "ex_ret_brn_cond_misp",
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"EventCode": "0x1c7",
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"BriefDescription": "Retired conditional branch instructions that were mispredicted due to direction mismatch."
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},
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{
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"EventName": "ex_ret_brn_uncond_ind_near_misp",
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"EventCode": "0x1c8",
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"BriefDescription": "Retired unconditional indirect near branch instructions that were mispredicted."
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},
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{
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"EventName": "ex_ret_brn_uncond",
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"EventCode": "0x1c9",
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"BriefDescription": "Retired unconditional branch instructions."
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},
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{
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"EventName": "ex_tagged_ibs_ops.tagged",
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"EventCode": "0x1cf",
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"BriefDescription": "Execution IBS tagged ops.",
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"UMask": "0x01"
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},
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{
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"EventName": "ex_tagged_ibs_ops.tagged_ret",
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"EventCode": "0x1cf",
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"BriefDescription": "Execution IBS tagged ops that retired.",
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"UMask": "0x02"
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},
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{
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"EventName": "ex_tagged_ibs_ops.rollovers",
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"EventCode": "0x1cf",
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"BriefDescription": "Execution IBS periodic counter rollovers due to a previous tagged op not being IBS complete.",
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"UMask": "0x04"
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},
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{
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"EventName": "ex_tagged_ibs_ops.filtered",
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"EventCode": "0x1cf",
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"BriefDescription": "Execution IBS tagged ops that retired but were discarded due to IBS filtering.",
|
||||
"UMask": "0x08"
|
||||
},
|
||||
{
|
||||
"EventName": "ex_tagged_ibs_ops.valid",
|
||||
"EventCode": "0x1cf",
|
||||
"BriefDescription": "Execution IBS tagged ops that resulted in a valid sample and an IBS interrupt.",
|
||||
"UMask": "0x10"
|
||||
},
|
||||
{
|
||||
"EventName": "ex_ret_fused_instr",
|
||||
"EventCode": "0x1d0",
|
||||
"BriefDescription": "Retired fused instructions."
|
||||
},
|
||||
{
|
||||
"EventName": "ex_mprof_ibs_ops.tagged",
|
||||
"EventCode": "0x2c0",
|
||||
"BriefDescription": "Memory Profiler IBS tagged ops.",
|
||||
"UMask": "0x01"
|
||||
},
|
||||
{
|
||||
"EventName": "ex_mprof_ibs_ops.tagged_ret",
|
||||
"EventCode": "0x2c0",
|
||||
"BriefDescription": "Memory Profiler IBS tagged ops that retired.",
|
||||
"UMask": "0x02"
|
||||
},
|
||||
{
|
||||
"EventName": "ex_mprof_ibs_ops.rollovers",
|
||||
"EventCode": "0x2c0",
|
||||
"BriefDescription": "Memory Profiler IBS periodic counter rollovers due to a previous tagged op not being IBS complete.",
|
||||
"UMask": "0x04"
|
||||
},
|
||||
{
|
||||
"EventName": "ex_mprof_ibs_ops.filtered",
|
||||
"EventCode": "0x2c0",
|
||||
"BriefDescription": "Memory Profiler IBS tagged ops that retired but were discarded due to IBS filtering.",
|
||||
"UMask": "0x08"
|
||||
},
|
||||
{
|
||||
"EventName": "ex_mprof_ibs_ops.valid",
|
||||
"EventCode": "0x2c0",
|
||||
"BriefDescription": "Memory Profiler IBS tagged ops that resulted in a valid sample and an IBS interrupt.",
|
||||
"UMask": "0x10"
|
||||
}
|
||||
]
|
||||
1106
tools/perf/pmu-events/arch/x86/amdzen6/floating-point.json
Normal file
1106
tools/perf/pmu-events/arch/x86/amdzen6/floating-point.json
Normal file
File diff suppressed because it is too large
Load Diff
120
tools/perf/pmu-events/arch/x86/amdzen6/inst-cache.json
Normal file
120
tools/perf/pmu-events/arch/x86/amdzen6/inst-cache.json
Normal file
|
|
@ -0,0 +1,120 @@
|
|||
[
|
||||
{
|
||||
"EventName": "ic_cache_fill_l2",
|
||||
"EventCode": "0x82",
|
||||
"BriefDescription": "Instruction cache lines (64 bytes) fulfilled from the L2 cache."
|
||||
},
|
||||
{
|
||||
"EventName": "ic_cache_fill_sys",
|
||||
"EventCode": "0x83",
|
||||
"BriefDescription": "Instruction cache lines (64 bytes) fulfilled from system memory or another cache."
|
||||
},
|
||||
{
|
||||
"EventName": "ic_fetch_ibs_events.tagged",
|
||||
"EventCode": "0x188",
|
||||
"BriefDescription": "Fetch IBS tagged fetches. Not all tagged fetches result in a valid sample and an IBS interrupt.",
|
||||
"UMask": "0x02"
|
||||
},
|
||||
{
|
||||
"EventName": "ic_fetch_ibs_events.filtered",
|
||||
"EventCode": "0x188",
|
||||
"BriefDescription": "Fetch IBS tagged fetches that were discarded due to IBS filtering.",
|
||||
"UMask": "0x08"
|
||||
},
|
||||
{
|
||||
"EventName": "ic_fetch_ibs_events.valid",
|
||||
"EventCode": "0x188",
|
||||
"BriefDescription": "Fetch IBS tagged fetches that resulted in a valid sample and an IBS interrupt.",
|
||||
"UMask": "0x10"
|
||||
},
|
||||
{
|
||||
"EventName": "op_cache_hit_miss.hit",
|
||||
"EventCode": "0x28f",
|
||||
"BriefDescription": "Op cache fetch hits.",
|
||||
"UMask": "0x03"
|
||||
},
|
||||
{
|
||||
"EventName": "op_cache_hit_miss.miss",
|
||||
"EventCode": "0x28f",
|
||||
"BriefDescription": "Op cache fetch misses.",
|
||||
"UMask": "0x04"
|
||||
},
|
||||
{
|
||||
"EventName": "op_cache_hit_miss.all",
|
||||
"EventCode": "0x28f",
|
||||
"BriefDescription": "Op cache fetches of all types.",
|
||||
"UMask": "0x07"
|
||||
},
|
||||
{
|
||||
"EventName": "ic_fills_from_sys.local_l2",
|
||||
"EventCode": "0x29c",
|
||||
"BriefDescription": "Instruction cache fills where data is returned from local L2 cache.",
|
||||
"UMask": "0x01"
|
||||
},
|
||||
{
|
||||
"EventName": "ic_fills_from_sys.local_ccx",
|
||||
"EventCode": "0x29c",
|
||||
"BriefDescription": "Instruction cache fills where data is returned from L3 cache or different L2 cache in the same CCX.",
|
||||
"UMask": "0x02"
|
||||
},
|
||||
{
|
||||
"EventName": "ic_fills_from_sys.local_all",
|
||||
"EventCode": "0x29c",
|
||||
"BriefDescription": "Instruction cache fills where data is returned from local L2 cache, L3 cache or different L2 cache in the same CCX.",
|
||||
"UMask": "0x03"
|
||||
},
|
||||
{
|
||||
"EventName": "ic_fills_from_sys.near_cache",
|
||||
"EventCode": "0x29c",
|
||||
"BriefDescription": "Instruction cache fills where data is returned from cache of another CCX in the same NUMA node.",
|
||||
"UMask": "0x04"
|
||||
},
|
||||
{
|
||||
"EventName": "ic_fills_from_sys.dram_io_near",
|
||||
"EventCode": "0x29c",
|
||||
"BriefDescription": "Instruction cache fills where data is returned from either DRAM or MMIO in the same NUMA node.",
|
||||
"UMask": "0x08"
|
||||
},
|
||||
{
|
||||
"EventName": "ic_fills_from_sys.far_cache",
|
||||
"EventCode": "0x29c",
|
||||
"BriefDescription": "Instruction cache fills where data is returned from cache of another CCX in a different NUMA node.",
|
||||
"UMask": "0x10"
|
||||
},
|
||||
{
|
||||
"EventName": "ic_fills_from_sys.remote_cache",
|
||||
"EventCode": "0x29c",
|
||||
"BriefDescription": "Instruction cache fills where data is returned from cache of another CCX in the same or a different NUMA node.",
|
||||
"UMask": "0x14"
|
||||
},
|
||||
{
|
||||
"EventName": "ic_fills_from_sys.dram_io_far",
|
||||
"EventCode": "0x29c",
|
||||
"BriefDescription": "Instruction cache fills where data is returned from either DRAM or MMIO in a different NUMA node.",
|
||||
"UMask": "0x40"
|
||||
},
|
||||
{
|
||||
"EventName": "ic_fills_from_sys.dram_io_all",
|
||||
"EventCode": "0x29c",
|
||||
"BriefDescription": "Instruction cache fills where data is returned from either DRAM or MMIO in the same or a different NUMA node.",
|
||||
"UMask": "0x48"
|
||||
},
|
||||
{
|
||||
"EventName": "ic_fills_from_sys.far_all",
|
||||
"EventCode": "0x29c",
|
||||
"BriefDescription": "Instruction cache fills where data is returned from either cache of another CCX, DRAM or MMIO in a different NUMA node.",
|
||||
"UMask": "0x50"
|
||||
},
|
||||
{
|
||||
"EventName": "ic_fills_from_sys.alt_mem",
|
||||
"EventCode": "0x29c",
|
||||
"BriefDescription": "Instruction cache fills where data is returned from extension memory (CXL).",
|
||||
"UMask": "0x80"
|
||||
},
|
||||
{
|
||||
"EventName": "ic_fills_from_sys.all",
|
||||
"EventCode": "0x29c",
|
||||
"BriefDescription": "Instruction cache fills where data is returned from all types of sources.",
|
||||
"UMask": "0xdf"
|
||||
}
|
||||
]
|
||||
326
tools/perf/pmu-events/arch/x86/amdzen6/l2-cache.json
Normal file
326
tools/perf/pmu-events/arch/x86/amdzen6/l2-cache.json
Normal file
|
|
@ -0,0 +1,326 @@
|
|||
[
|
||||
{
|
||||
"EventName": "l2_request_g1.group2",
|
||||
"EventCode": "0x60",
|
||||
"BriefDescription": "L2 cache requests of non-cacheable type (non-cached data and instructions reads, self-modifying code checks).",
|
||||
"UMask": "0x01"
|
||||
},
|
||||
{
|
||||
"EventName": "l2_request_g1.l2_hwpf",
|
||||
"EventCode": "0x60",
|
||||
"BriefDescription": "L2 cache requests from hardware prefetchers to prefetch directly into L2 (hit or miss).",
|
||||
"UMask": "0x02"
|
||||
},
|
||||
{
|
||||
"EventName": "l2_request_g1.prefetch_l2_cmd",
|
||||
"EventCode": "0x60",
|
||||
"BriefDescription": "L2 cache requests to prefetch directly into L2.",
|
||||
"UMask": "0x04"
|
||||
},
|
||||
{
|
||||
"EventName": "l2_request_g1.cacheable_ic_read",
|
||||
"EventCode": "0x60",
|
||||
"BriefDescription": "L2 cache requests for instruction cache reads.",
|
||||
"UMask": "0x10"
|
||||
},
|
||||
{
|
||||
"EventName": "l2_request_g1.ls_rd_blk_c_s",
|
||||
"EventCode": "0x60",
|
||||
"BriefDescription": "L2 cache requests for data cache shared reads.",
|
||||
"UMask": "0x20"
|
||||
},
|
||||
{
|
||||
"EventName": "l2_request_g1.rd_blk_x",
|
||||
"EventCode": "0x60",
|
||||
"BriefDescription": "L2 cache requests for data cache stores.",
|
||||
"UMask": "0x40"
|
||||
},
|
||||
{
|
||||
"EventName": "l2_request_g1.rd_blk_l",
|
||||
"EventCode": "0x60",
|
||||
"BriefDescription": "L2 cache requests for data cache reads (includes hardware and software prefetches).",
|
||||
"UMask": "0x80"
|
||||
},
|
||||
{
|
||||
"EventName": "l2_request_g1.dc_all",
|
||||
"EventCode": "0x60",
|
||||
"BriefDescription": "L2 cache requests of common types from data cache (includes prefetches).",
|
||||
"UMask": "0xe0"
|
||||
},
|
||||
{
|
||||
"EventName": "l2_request_g1.no_pf_all",
|
||||
"EventCode": "0x60",
|
||||
"BriefDescription": "L2 cache requests of common types not including prefetches.",
|
||||
"UMask": "0xf1"
|
||||
},
|
||||
{
|
||||
"EventName": "l2_request_g1.all",
|
||||
"EventCode": "0x60",
|
||||
"BriefDescription": "L2 cache requests of all types.",
|
||||
"UMask": "0xf7"
|
||||
},
|
||||
{
|
||||
"EventName": "l2_request_g2.ls_rd_sized_nc",
|
||||
"EventCode": "0x61",
|
||||
"BriefDescription": "L2 cache requests for non-coherent, non-cacheable LS sized reads.",
|
||||
"UMask": "0x20"
|
||||
},
|
||||
{
|
||||
"EventName": "l2_request_g2.ls_rd_sized",
|
||||
"EventCode": "0x61",
|
||||
"BriefDescription": "L2 cache requests for coherent, non-cacheable LS sized reads.",
|
||||
"UMask": "0x40"
|
||||
},
|
||||
{
|
||||
"EventName": "l2_request_g2.all",
|
||||
"EventCode": "0x61",
|
||||
"BriefDescription": "L2 cache requests of all rare types.",
|
||||
"UMask": "0x40"
|
||||
},
|
||||
{
|
||||
"EventName": "l2_wcb_req.wcb_close",
|
||||
"EventCode": "0x63",
|
||||
"BriefDescription": "Write Combining Buffer (WCB) closures.",
|
||||
"UMask": "0x20"
|
||||
},
|
||||
{
|
||||
"EventName": "l2_cache_req_stat.ic_fill_miss",
|
||||
"EventCode": "0x64",
|
||||
"BriefDescription": "Core to L2 cache requests (not including L2 prefetch) from the instruction cache that result in L2 misses.",
|
||||
"UMask": "0x01"
|
||||
},
|
||||
{
|
||||
"EventName": "l2_cache_req_stat.ic_fill_hit_s",
|
||||
"EventCode": "0x64",
|
||||
"BriefDescription": "Core to L2 cache requests (not including L2 prefetch) from the instruction cache that result in L2 hits on non-modifiable lines.",
|
||||
"UMask": "0x02"
|
||||
},
|
||||
{
|
||||
"EventName": "l2_cache_req_stat.ic_fill_hit_x",
|
||||
"EventCode": "0x64",
|
||||
"BriefDescription": "Core to L2 cache requests (not including L2 prefetch) from the instruction cache that result in L2 hits on modifiable lines.",
|
||||
"UMask": "0x04"
|
||||
},
|
||||
{
|
||||
"EventName": "l2_cache_req_stat.ic_hit_in_l2",
|
||||
"EventCode": "0x64",
|
||||
"BriefDescription": "Core to L2 cache requests (not including L2 prefetch) from the instruction cache that result in L2 hits.",
|
||||
"UMask": "0x06"
|
||||
},
|
||||
{
|
||||
"EventName": "l2_cache_req_stat.ic_access_in_l2",
|
||||
"EventCode": "0x64",
|
||||
"BriefDescription": "Core to L2 cache requests (not including L2 prefetch) from the instruction cache that result in L2 accesses.",
|
||||
"UMask": "0x07"
|
||||
},
|
||||
{
|
||||
"EventName": "l2_cache_req_stat.ls_rd_blk_c",
|
||||
"EventCode": "0x64",
|
||||
"BriefDescription": "Core to L2 cache requests (not including L2 prefetch) from the data cache that result in L2 misses.",
|
||||
"UMask": "0x08"
|
||||
},
|
||||
{
|
||||
"EventName": "l2_cache_req_stat.ic_dc_miss_in_l2",
|
||||
"EventCode": "0x64",
|
||||
"BriefDescription": "Core to L2 cache requests (not including L2 prefetch) from the data cache and the instruction cache that result in L2 misses.",
|
||||
"UMask": "0x09"
|
||||
},
|
||||
{
|
||||
"EventName": "l2_cache_req_stat.ls_rd_blk_x",
|
||||
"EventCode": "0x64",
|
||||
"BriefDescription": "Core to L2 cache requests (not including L2 prefetch) that result in data cache stores or L2 state change hits.",
|
||||
"UMask": "0x10"
|
||||
},
|
||||
{
|
||||
"EventName": "l2_cache_req_stat.ls_rd_blk_l_hit_s",
|
||||
"EventCode": "0x64",
|
||||
"BriefDescription": "Core to L2 cache requests (not including L2 prefetch) from the data cache that result in L2 hits on non-modifiable lines.",
|
||||
"UMask": "0x20"
|
||||
},
|
||||
{
|
||||
"EventName": "l2_cache_req_stat.ls_rd_blk_l_hit_x",
|
||||
"EventCode": "0x64",
|
||||
"BriefDescription": "Core to L2 cache requests (not including L2 prefetch) from the data cache that result in L2 hits on modifiable lines.",
|
||||
"UMask": "0x40"
|
||||
},
|
||||
{
|
||||
"EventName": "l2_cache_req_stat.ls_rd_blk_cs",
|
||||
"EventCode": "0x64",
|
||||
"BriefDescription": "Core to L2 cache requests (not including L2 prefetch) from the data cache that result in L2 read hits on shared lines.",
|
||||
"UMask": "0x80"
|
||||
},
|
||||
{
|
||||
"EventName": "l2_cache_req_stat.dc_hit_in_l2",
|
||||
"EventCode": "0x64",
|
||||
"BriefDescription": "Core to L2 cache requests (not including L2 prefetch) from the data cache that result in L2 hits.",
|
||||
"UMask": "0xf0"
|
||||
},
|
||||
{
|
||||
"EventName": "l2_cache_req_stat.ic_dc_hit_in_l2",
|
||||
"EventCode": "0x64",
|
||||
"BriefDescription": "Core to L2 cache requests (not including L2 prefetch) from the data cache and the instruction cache that result in L2 hits.",
|
||||
"UMask": "0xf6"
|
||||
},
|
||||
{
|
||||
"EventName": "l2_cache_req_stat.dc_access_in_l2",
|
||||
"EventCode": "0x64",
|
||||
"BriefDescription": "Core to L2 cache requests (not including L2 prefetch) from the data cache that result in L2 accesses.",
|
||||
"UMask": "0xf8"
|
||||
},
|
||||
{
|
||||
"EventName": "l2_cache_req_stat.all",
|
||||
"EventCode": "0x64",
|
||||
"BriefDescription": "Core to L2 cache requests (not including L2 prefetch) from the data cache and the instruction cache that result in L2 accesses.",
|
||||
"UMask": "0xff"
|
||||
},
|
||||
{
|
||||
"EventName": "l2_pf_hit_l2.l2_hwpf",
|
||||
"EventCode": "0x70",
|
||||
"BriefDescription": "L2 prefetches accepted by the L2 pipeline which hit in the L2 cache and are generated from L2 hardware prefetchers.",
|
||||
"UMask": "0x1f"
|
||||
},
|
||||
{
|
||||
"EventName": "l2_pf_hit_l2.l1_dc_hwpf",
|
||||
"EventCode": "0x70",
|
||||
"BriefDescription": "L2 prefetches accepted by the L2 pipeline which hit in the L2 cache and are generated from L1 data hardware prefetchers.",
|
||||
"UMask": "0xe0"
|
||||
},
|
||||
{
|
||||
"EventName": "l2_pf_hit_l2.l1_dc_l2_hwpf",
|
||||
"EventCode": "0x70",
|
||||
"BriefDescription": "L2 prefetches accepted by the L2 pipeline which hit in the L2 cache and are generated from L1 data and L2 hardware prefetchers.",
|
||||
"UMask": "0xff"
|
||||
},
|
||||
{
|
||||
"EventName": "l2_pf_miss_l2_hit_l3.l2_hwpf",
|
||||
"EventCode": "0x71",
|
||||
"BriefDescription": "L2 prefetches accepted by the L2 pipeline which miss the L2 cache but hit in the L3 cache and are generated from L2 hardware prefetchers.",
|
||||
"UMask": "0x1f"
|
||||
},
|
||||
{
|
||||
"EventName": "l2_pf_miss_l2_hit_l3.l1_dc_hwpf",
|
||||
"EventCode": "0x71",
|
||||
"BriefDescription": "L2 prefetches accepted by the L2 pipeline which miss the L2 cache but hit in the L3 cache and are generated from L1 data hardware prefetchers.",
|
||||
"UMask": "0xe0"
|
||||
},
|
||||
{
|
||||
"EventName": "l2_pf_miss_l2_hit_l3.l1_dc_l2_hwpf",
|
||||
"EventCode": "0x71",
|
||||
"BriefDescription": "L2 prefetches accepted by the L2 pipeline which miss the L2 cache but hit in the L3 cache and are generated from L1 data and L2 hardware prefetchers.",
|
||||
"UMask": "0xff"
|
||||
},
|
||||
{
|
||||
"EventName": "l2_pf_miss_l2_l3.l2_hwpf",
|
||||
"EventCode": "0x72",
|
||||
"BriefDescription": "L2 prefetches accepted by the L2 pipeline which miss the L2 as well as the L3 caches and are generated from L2 hardware prefetchers.",
|
||||
"UMask": "0x1f"
|
||||
},
|
||||
{
|
||||
"EventName": "l2_pf_miss_l2_l3.l1_dc_hwpf",
|
||||
"EventCode": "0x72",
|
||||
"BriefDescription": "L2 prefetches accepted by the L2 pipeline which miss the L2 as well as the L3 caches and are generated from L1 data hardware prefetchers.",
|
||||
"UMask": "0xe0"
|
||||
},
|
||||
{
|
||||
"EventName": "l2_pf_miss_l2_l3.l1_dc_l2_hwpf",
|
||||
"EventCode": "0x72",
|
||||
"BriefDescription": "L2 prefetches accepted by the L2 pipeline which miss the L2 as well as the L3 caches and are generated from L1 data and L2 hardware prefetchers.",
|
||||
"UMask": "0xff"
|
||||
},
|
||||
{
|
||||
"EventName": "l2_fill_rsp_src.local_ccx",
|
||||
"EventCode": "0x165",
|
||||
"BriefDescription": "L2 cache fills where data is returned from L3 cache or different L2 cache in the same CCX.",
|
||||
"UMask": "0x02"
|
||||
},
|
||||
{
|
||||
"EventName": "l2_fill_rsp_src.near_cache",
|
||||
"EventCode": "0x165",
|
||||
"BriefDescription": "L2 cache fills where data is returned from cache of another CCX in the same NUMA node.",
|
||||
"UMask": "0x04"
|
||||
},
|
||||
{
|
||||
"EventName": "l2_fill_rsp_src.dram_io_near",
|
||||
"EventCode": "0x165",
|
||||
"BriefDescription": "L2 cache fills where data is returned from either DRAM or MMIO in the same NUMA node.",
|
||||
"UMask": "0x08"
|
||||
},
|
||||
{
|
||||
"EventName": "l2_fill_rsp_src.far_cache",
|
||||
"EventCode": "0x165",
|
||||
"BriefDescription": "L2 cache fills where data is returned from cache of another CCX in a different NUMA node.",
|
||||
"UMask": "0x10"
|
||||
},
|
||||
{
|
||||
"EventName": "l2_fill_rsp_src.dram_io_far",
|
||||
"EventCode": "0x165",
|
||||
"BriefDescription": "L2 cache fills where data is returned from either DRAM or MMIO in a different NUMA node.",
|
||||
"UMask": "0x40"
|
||||
},
|
||||
{
|
||||
"EventName": "l2_fill_rsp_src.dram_io_all",
|
||||
"EventCode": "0x165",
|
||||
"BriefDescription": "L2 cache fills where data is returned from either DRAM or MMIO in the same or a different NUMA node.",
|
||||
"UMask": "0x48"
|
||||
},
|
||||
{
|
||||
"EventName": "l2_fill_rsp_src.far_all",
|
||||
"EventCode": "0x165",
|
||||
"BriefDescription": "L2 cache fills where data is returned from either cache of another CCX, DRAM or MMIO in a different NUMA node.",
|
||||
"UMask": "0x50"
|
||||
},
|
||||
{
|
||||
"EventName": "l2_fill_rsp_src.alt_mem",
|
||||
"EventCode": "0x165",
|
||||
"BriefDescription": "L2 cache fills where data is returned from extension memory (CXL).",
|
||||
"UMask": "0x80"
|
||||
},
|
||||
{
|
||||
"EventName": "l2_fill_rsp_src.all",
|
||||
"EventCode": "0x165",
|
||||
"BriefDescription": "L2 cache fills where data is returned from all types of sources.",
|
||||
"UMask": "0xde"
|
||||
},
|
||||
{
|
||||
"EventName": "l2_sys_bw.local_dram_fill",
|
||||
"EventCode": "0x175",
|
||||
"BriefDescription": "System bandwidth utilization for fill events that target the same NUMA node and return from DRAM in the same NUMA node.",
|
||||
"UMask": "0x01"
|
||||
},
|
||||
{
|
||||
"EventName": "l2_sys_bw.remote_dram_fill",
|
||||
"EventCode": "0x175",
|
||||
"BriefDescription": "System bandwidth utilization for fill events that target a different NUMA node and return from DRAM in a different NUMA node.",
|
||||
"UMask": "0x02"
|
||||
},
|
||||
{
|
||||
"EventName": "l2_sys_bw.nt_write",
|
||||
"EventCode": "0x175",
|
||||
"BriefDescription": "System bandwidth utilization for non-temporal write events that target all NUMA nodes.",
|
||||
"UMask": "0x04"
|
||||
},
|
||||
{
|
||||
"EventName": "l2_sys_bw.local_scm_fill",
|
||||
"EventCode": "0x175",
|
||||
"BriefDescription": "System bandwidth utilization for fill events that target the same NUMA node and return from extension memory (CXL) in the same NUMA node.",
|
||||
"UMask": "0x10"
|
||||
},
|
||||
{
|
||||
"EventName": "l2_sys_bw.remote_scm_fill",
|
||||
"EventCode": "0x175",
|
||||
"BriefDescription": "System bandwidth utilization for fill events that target a different NUMA node and return from extension memory (CXL) in a different NUMA node.",
|
||||
"UMask": "0x20"
|
||||
},
|
||||
{
|
||||
"EventName": "l2_sys_bw.victim",
|
||||
"EventCode": "0x175",
|
||||
"BriefDescription": "System bandwidth utilization for cache victim events that target all NUMA nodes.",
|
||||
"UMask": "0x40"
|
||||
},
|
||||
{
|
||||
"EventName": "l2_sys_bw.all",
|
||||
"EventCode": "0x175",
|
||||
"BriefDescription": "System bandwidth utilization for all types of events (total utilization).",
|
||||
"UMask": "0xff"
|
||||
}
|
||||
]
|
||||
523
tools/perf/pmu-events/arch/x86/amdzen6/load-store.json
Normal file
523
tools/perf/pmu-events/arch/x86/amdzen6/load-store.json
Normal file
|
|
@ -0,0 +1,523 @@
|
|||
[
|
||||
{
|
||||
"EventName": "ls_bad_status2.stli_other",
|
||||
"EventCode": "0x24",
|
||||
"BriefDescription": "Store-to-load conflicts (loads unable to complete due to a non-forwardable conflict with an older store).",
|
||||
"UMask": "0x02"
|
||||
},
|
||||
{
|
||||
"EventName": "ls_locks.bus_lock",
|
||||
"EventCode": "0x25",
|
||||
"BriefDescription": "Retired lock instructions which caused a bus lock (non-cacheable or cache-misaligned lock).",
|
||||
"UMask": "0x01"
|
||||
},
|
||||
{
|
||||
"EventName": "ls_locks.all",
|
||||
"EventCode": "0x25",
|
||||
"BriefDescription": "Retired lock instructions of all types.",
|
||||
"UMask": "0x1f"
|
||||
},
|
||||
{
|
||||
"EventName": "ls_ret_cl_flush",
|
||||
"EventCode": "0x26",
|
||||
"BriefDescription": "Retired CLFLUSH instructions."
|
||||
},
|
||||
{
|
||||
"EventName": "ls_ret_cpuid",
|
||||
"EventCode": "0x27",
|
||||
"BriefDescription": "Retired CPUID instructions."
|
||||
},
|
||||
{
|
||||
"EventName": "ls_dispatch.pure_ld",
|
||||
"EventCode": "0x29",
|
||||
"BriefDescription": "Memory load operations dispatched to the load-store unit.",
|
||||
"UMask": "0x01"
|
||||
},
|
||||
{
|
||||
"EventName": "ls_dispatch.pure_st",
|
||||
"EventCode": "0x29",
|
||||
"BriefDescription": "Memory store operations dispatched to the load-store unit.",
|
||||
"UMask": "0x02"
|
||||
},
|
||||
{
|
||||
"EventName": "ls_dispatch.ld_st",
|
||||
"EventCode": "0x29",
|
||||
"BriefDescription": "Memory load-store operations (load from and store to the same memory address) dispatched to the load-store unit.",
|
||||
"UMask": "0x04"
|
||||
},
|
||||
{
|
||||
"EventName": "ls_dispatch.all",
|
||||
"EventCode": "0x29",
|
||||
"BriefDescription": "Memory operations dispatched to the load-store unit of all types.",
|
||||
"UMask": "0x07"
|
||||
},
|
||||
{
|
||||
"EventName": "ls_smi_rx",
|
||||
"EventCode": "0x2b",
|
||||
"BriefDescription": "System Management Interrupts (SMIs) received."
|
||||
},
|
||||
{
|
||||
"EventName": "ls_int_taken",
|
||||
"EventCode": "0x2c",
|
||||
"BriefDescription": "Interrupts taken."
|
||||
},
|
||||
{
|
||||
"EventName": "ls_stlf",
|
||||
"EventCode": "0x35",
|
||||
"BriefDescription": "Store-to-load-forward (STLF) hits."
|
||||
},
|
||||
{
|
||||
"EventName": "ls_st_commit_cancel.older_st_vis_dep",
|
||||
"EventCode": "0x37",
|
||||
"BriefDescription": "Store commits cancelled due to an older store, that the thread was waiting on to become globally visible, was unable to become globally visible.",
|
||||
"UMask": "0x01"
|
||||
},
|
||||
{
|
||||
"EventName": "ls_mab_alloc.ls",
|
||||
"EventCode": "0x41",
|
||||
"BriefDescription": "Miss Address Buffer (MAB) entries allocated by a Load-Store (LS) pipe for load-store allocations.",
|
||||
"UMask": "0x07"
|
||||
},
|
||||
{
|
||||
"EventName": "ls_mab_alloc.hwpf",
|
||||
"EventCode": "0x41",
|
||||
"BriefDescription": "Miss Address Buffer (MAB) entries allocated by a Load-Store (LS) pipe for hardware prefetcher allocations.",
|
||||
"UMask": "0x08"
|
||||
},
|
||||
{
|
||||
"EventName": "ls_mab_alloc.all",
|
||||
"EventCode": "0x41",
|
||||
"BriefDescription": "Miss Address Buffer (MAB) entries allocated by a Load-Store (LS) pipe for all types of allocations.",
|
||||
"UMask": "0x0f"
|
||||
},
|
||||
{
|
||||
"EventName": "ls_dmnd_fills_from_sys.local_l2",
|
||||
"EventCode": "0x43",
|
||||
"BriefDescription": "Demand data cache fills where data is returned from local L2 cache.",
|
||||
"UMask": "0x01"
|
||||
},
|
||||
{
|
||||
"EventName": "ls_dmnd_fills_from_sys.local_ccx",
|
||||
"EventCode": "0x43",
|
||||
"BriefDescription": "Demand data cache fills where data is returned from L3 cache or different L2 cache in the same CCX.",
|
||||
"UMask": "0x02"
|
||||
},
|
||||
{
|
||||
"EventName": "ls_dmnd_fills_from_sys.local_all",
|
||||
"EventCode": "0x43",
|
||||
"BriefDescription": "Demand data cache fills where data is returned from local L2 cache, L3 cache or different L2 cache in the same CCX.",
|
||||
"UMask": "0x03"
|
||||
},
|
||||
{
|
||||
"EventName": "ls_dmnd_fills_from_sys.near_cache",
|
||||
"EventCode": "0x43",
|
||||
"BriefDescription": "Demand data cache fills where data is returned from cache of another CCX in the same NUMA node.",
|
||||
"UMask": "0x04"
|
||||
},
|
||||
{
|
||||
"EventName": "ls_dmnd_fills_from_sys.dram_io_near",
|
||||
"EventCode": "0x43",
|
||||
"BriefDescription": "Demand data cache fills where data is returned from either DRAM or MMIO in the same NUMA node.",
|
||||
"UMask": "0x08"
|
||||
},
|
||||
{
|
||||
"EventName": "ls_dmnd_fills_from_sys.far_cache",
|
||||
"EventCode": "0x43",
|
||||
"BriefDescription": "Demand data cache fills where data is returned from cache of another CCX in a different NUMA node.",
|
||||
"UMask": "0x10"
|
||||
},
|
||||
{
|
||||
"EventName": "ls_dmnd_fills_from_sys.remote_cache",
|
||||
"EventCode": "0x43",
|
||||
"BriefDescription": "Demand data cache fills where data is returned from cache of another CCX in the same or a different NUMA node.",
|
||||
"UMask": "0x14"
|
||||
},
|
||||
{
|
||||
"EventName": "ls_dmnd_fills_from_sys.dram_io_far",
|
||||
"EventCode": "0x43",
|
||||
"BriefDescription": "Demand data cache fills where data is returned from either DRAM or MMIO in a different NUMA node.",
|
||||
"UMask": "0x40"
|
||||
},
|
||||
{
|
||||
"EventName": "ls_dmnd_fills_from_sys.dram_io_all",
|
||||
"EventCode": "0x43",
|
||||
"BriefDescription": "Demand data cache fills where data is returned from either DRAM or MMIO in the same or a different NUMA node.",
|
||||
"UMask": "0x48"
|
||||
},
|
||||
{
|
||||
"EventName": "ls_dmnd_fills_from_sys.far_all",
|
||||
"EventCode": "0x43",
|
||||
"BriefDescription": "Demand data cache fills where data is returned from either cache of another CCX, DRAM or MMIO in a different NUMA node.",
|
||||
"UMask": "0x50"
|
||||
},
|
||||
{
|
||||
"EventName": "ls_dmnd_fills_from_sys.alt_mem",
|
||||
"EventCode": "0x43",
|
||||
"BriefDescription": "Demand data cache fills where data is returned from extension memory (CXL).",
|
||||
"UMask": "0x80"
|
||||
},
|
||||
{
|
||||
"EventName": "ls_dmnd_fills_from_sys.all",
|
||||
"EventCode": "0x43",
|
||||
"BriefDescription": "Demand data cache fills where data is returned from all types of sources.",
|
||||
"UMask": "0xdf"
|
||||
},
|
||||
{
|
||||
"EventName": "ls_any_fills_from_sys.local_l2",
|
||||
"EventCode": "0x44",
|
||||
"BriefDescription": "Any data cache fills where data is returned from local L2 cache.",
|
||||
"UMask": "0x01"
|
||||
},
|
||||
{
|
||||
"EventName": "ls_any_fills_from_sys.local_ccx",
|
||||
"EventCode": "0x44",
|
||||
"BriefDescription": "Any data cache fills where data is returned from L3 cache or different L2 cache in the same CCX.",
|
||||
"UMask": "0x02"
|
||||
},
|
||||
{
|
||||
"EventName": "ls_any_fills_from_sys.local_all",
|
||||
"EventCode": "0x44",
|
||||
"BriefDescription": "Any data cache fills where data is returned from local L2 cache, L3 cache or different L2 cache in the same CCX.",
|
||||
"UMask": "0x03"
|
||||
},
|
||||
{
|
||||
"EventName": "ls_any_fills_from_sys.near_cache",
|
||||
"EventCode": "0x44",
|
||||
"BriefDescription": "Any data cache fills where data is returned from cache of another CCX in the same NUMA node.",
|
||||
"UMask": "0x04"
|
||||
},
|
||||
{
|
||||
"EventName": "ls_any_fills_from_sys.dram_io_near",
|
||||
"EventCode": "0x44",
|
||||
"BriefDescription": "Any data cache fills where data is returned from either DRAM or MMIO in the same NUMA node.",
|
||||
"UMask": "0x08"
|
||||
},
|
||||
{
|
||||
"EventName": "ls_any_fills_from_sys.far_cache",
|
||||
"EventCode": "0x44",
|
||||
"BriefDescription": "Any data cache fills where data is returned from cache of another CCX in a different NUMA node.",
|
||||
"UMask": "0x10"
|
||||
},
|
||||
{
|
||||
"EventName": "ls_any_fills_from_sys.remote_cache",
|
||||
"EventCode": "0x44",
|
||||
"BriefDescription": "Any data cache fills where data is returned from cache of another CCX in the same or a different NUMA node.",
|
||||
"UMask": "0x14"
|
||||
},
|
||||
{
|
||||
"EventName": "ls_any_fills_from_sys.dram_io_far",
|
||||
"EventCode": "0x44",
|
||||
"BriefDescription": "Any data cache fills where data is returned from either DRAM or MMIO in a different NUMA node.",
|
||||
"UMask": "0x40"
|
||||
},
|
||||
{
|
||||
"EventName": "ls_any_fills_from_sys.dram_io_all",
|
||||
"EventCode": "0x44",
|
||||
"BriefDescription": "Any data cache fills where data is returned from either DRAM or MMIO in the same or a different NUMA node.",
|
||||
"UMask": "0x48"
|
||||
},
|
||||
{
|
||||
"EventName": "ls_any_fills_from_sys.far_all",
|
||||
"EventCode": "0x44",
|
||||
"BriefDescription": "Any data cache fills where data is returned from either cache of another CCX, DRAM or MMIO when the address was in a different NUMA node.",
|
||||
"UMask": "0x50"
|
||||
},
|
||||
{
|
||||
"EventName": "ls_any_fills_from_sys.alt_mem",
|
||||
"EventCode": "0x44",
|
||||
"BriefDescription": "Any data cache fills where data is returned from extension memory (CXL).",
|
||||
"UMask": "0x80"
|
||||
},
|
||||
{
|
||||
"EventName": "ls_any_fills_from_sys.all",
|
||||
"EventCode": "0x44",
|
||||
"BriefDescription": "Any data cache fills where data is returned from all types of data sources.",
|
||||
"UMask": "0xff"
|
||||
},
|
||||
{
|
||||
"EventName": "ls_l1_d_tlb_miss.tlb_reload_4k_l2_hit",
|
||||
"EventCode": "0x45",
|
||||
"BriefDescription": "L1 DTLB misses with L2 DTLB hits for 4k pages.",
|
||||
"UMask": "0x01"
|
||||
},
|
||||
{
|
||||
"EventName": "ls_l1_d_tlb_miss.tlb_reload_coalesced_page_hit",
|
||||
"EventCode": "0x45",
|
||||
"BriefDescription": "L1 DTLB misses with L2 DTLB hits for coalesced pages (16k pages created from four adjacent 4k pages).",
|
||||
"UMask": "0x02"
|
||||
},
|
||||
{
|
||||
"EventName": "ls_l1_d_tlb_miss.tlb_reload_2m_l2_hit",
|
||||
"EventCode": "0x45",
|
||||
"BriefDescription": "L1 DTLB misses with L2 DTLB hits for 2M pages.",
|
||||
"UMask": "0x04"
|
||||
},
|
||||
{
|
||||
"EventName": "ls_l1_d_tlb_miss.tlb_reload_1g_l2_hit",
|
||||
"EventCode": "0x45",
|
||||
"BriefDescription": "L1 DTLB misses with L2 DTLB hits for 1G pages.",
|
||||
"UMask": "0x08"
|
||||
},
|
||||
{
|
||||
"EventName": "ls_l1_d_tlb_miss.tlb_reload_4k_l2_miss",
|
||||
"EventCode": "0x45",
|
||||
"BriefDescription": "L1 DTLB misses with L2 DTLB misses (page-table walks requested) for 4k pages.",
|
||||
"UMask": "0x10"
|
||||
},
|
||||
{
|
||||
"EventName": "ls_l1_d_tlb_miss.tlb_reload_coalesced_page_miss",
|
||||
"EventCode": "0x45",
|
||||
"BriefDescription": "L1 DTLB misses with L2 DTLB misses (page-table walks requested) for coalesced pages (16k pages created from four adjacent 4k pages).",
|
||||
"UMask": "0x20"
|
||||
},
|
||||
{
|
||||
"EventName": "ls_l1_d_tlb_miss.tlb_reload_2m_l2_miss",
|
||||
"EventCode": "0x45",
|
||||
"BriefDescription": "L1 DTLB misses with L2 DTLB misses (page-table walks requested) for 2M pages.",
|
||||
"UMask": "0x40"
|
||||
},
|
||||
{
|
||||
"EventName": "ls_l1_d_tlb_miss.tlb_reload_1g_l2_miss",
|
||||
"EventCode": "0x45",
|
||||
"BriefDescription": "L1 DTLB misses with L2 DTLB misses (page-table walks requested) for 1G pages.",
|
||||
"UMask": "0x80"
|
||||
},
|
||||
{
|
||||
"EventName": "ls_l1_d_tlb_miss.l2_miss_all",
|
||||
"EventCode": "0x45",
|
||||
"BriefDescription": "L1 DTLB misses with L2 DTLB misses (page-table walks requested) for all page sizes.",
|
||||
"UMask": "0xf0"
|
||||
},
|
||||
{
|
||||
"EventName": "ls_l1_d_tlb_miss.all",
|
||||
"EventCode": "0x45",
|
||||
"BriefDescription": "L1 DTLB misses for all page sizes.",
|
||||
"UMask": "0xff"
|
||||
},
|
||||
{
|
||||
"EventName": "ls_misal_loads.ma64",
|
||||
"EventCode": "0x47",
|
||||
"BriefDescription": "64B misaligned (cacheline crossing) loads.",
|
||||
"UMask": "0x01"
|
||||
},
|
||||
{
|
||||
"EventName": "ls_misal_loads.ma4k",
|
||||
"EventCode": "0x47",
|
||||
"BriefDescription": "4kB misaligned (page crossing) loads.",
|
||||
"UMask": "0x02"
|
||||
},
|
||||
{
|
||||
"EventName": "ls_pref_instr_disp.prefetch",
|
||||
"EventCode": "0x4b",
|
||||
"BriefDescription": "Software prefetch instructions dispatched (speculative) of type PrefetchT0 (move data to all cache levels), T1 (move data to all cache levels except L1) and T2 (move data to all cache levels except L1 and L2).",
|
||||
"UMask": "0x01"
|
||||
},
|
||||
{
|
||||
"EventName": "ls_pref_instr_disp.prefetch_w",
|
||||
"EventCode": "0x4b",
|
||||
"BriefDescription": "Software prefetch instructions dispatched (speculative) of type PrefetchW (move data to L1 cache and mark it modifiable).",
|
||||
"UMask": "0x02"
|
||||
},
|
||||
{
|
||||
"EventName": "ls_pref_instr_disp.prefetch_nta",
|
||||
"EventCode": "0x4b",
|
||||
"BriefDescription": "Software prefetch instructions dispatched (speculative) of type PrefetchNTA (move data with minimum cache pollution i.e. non-temporal access).",
|
||||
"UMask": "0x04"
|
||||
},
|
||||
{
|
||||
"EventName": "ls_pref_instr_disp.all",
|
||||
"EventCode": "0x4b",
|
||||
"BriefDescription": "Software prefetch instructions dispatched (speculative) of all types.",
|
||||
"UMask": "0x07"
|
||||
},
|
||||
{
|
||||
"EventName": "wcb_close.full_line_64b",
|
||||
"EventCode": "0x50",
|
||||
"BriefDescription": "Events that caused a Write Combining Buffer (WCB) entry to close because all 64 bytes of the entry have been written to.",
|
||||
"UMask": "0x01"
|
||||
},
|
||||
{
|
||||
"EventName": "ls_inef_sw_pref.dc_hit",
|
||||
"EventCode": "0x52",
|
||||
"BriefDescription": "Software prefetches that did not fetch data outside of the processor core as the PREFETCH instruction saw a data cache hit.",
|
||||
"UMask": "0x01"
|
||||
},
|
||||
{
|
||||
"EventName": "ls_inef_sw_pref.mab_hit",
|
||||
"EventCode": "0x52",
|
||||
"BriefDescription": "Software prefetches that did not fetch data outside of the processor core as the PREFETCH instruction saw a match on an already allocated miss request (MAB).",
|
||||
"UMask": "0x02"
|
||||
},
|
||||
{
|
||||
"EventName": "ls_inef_sw_pref.all",
|
||||
"EventCode": "0x52",
|
||||
"BriefDescript6ion": "Software prefetches that did not fetch data outside of the processor core for any reason.",
|
||||
"UMask": "0x03"
|
||||
},
|
||||
{
|
||||
"EventName": "ls_sw_pf_dc_fills.local_l2",
|
||||
"EventCode": "0x59",
|
||||
"BriefDescription": "Software prefetch data cache fills where data is returned from local L2 cache.",
|
||||
"UMask": "0x01"
|
||||
},
|
||||
{
|
||||
"EventName": "ls_sw_pf_dc_fills.local_ccx",
|
||||
"EventCode": "0x59",
|
||||
"BriefDescription": "Software prefetch data cache fills where data is returned from L3 cache or different L2 cache in the same CCX.",
|
||||
"UMask": "0x02"
|
||||
},
|
||||
{
|
||||
"EventName": "ls_sw_pf_dc_fills.local_all",
|
||||
"EventCode": "0x59",
|
||||
"BriefDescription": "Software prefetch data cache fills where data is returned from local L2 cache, L3 cache or different L2 cache in the same CCX.",
|
||||
"UMask": "0x03"
|
||||
},
|
||||
{
|
||||
"EventName": "ls_sw_pf_dc_fills.near_cache",
|
||||
"EventCode": "0x59",
|
||||
"BriefDescription": "Software prefetch data cache fills where data is returned from cache of another CCX in the same NUMA node.",
|
||||
"UMask": "0x04"
|
||||
},
|
||||
{
|
||||
"EventName": "ls_sw_pf_dc_fills.dram_io_near",
|
||||
"EventCode": "0x59",
|
||||
"BriefDescription": "Software prefetch data cache fills where data is returned from either DRAM or MMIO in the same NUMA node.",
|
||||
"UMask": "0x08"
|
||||
},
|
||||
{
|
||||
"EventName": "ls_sw_pf_dc_fills.far_cache",
|
||||
"EventCode": "0x59",
|
||||
"BriefDescription": "Software prefetch data cache fills where data is returned from cache of another CCX in a different NUMA node.",
|
||||
"UMask": "0x10"
|
||||
},
|
||||
{
|
||||
"EventName": "ls_sw_pf_dc_fills.remote_cache",
|
||||
"EventCode": "0x59",
|
||||
"BriefDescription": "Software prefetch data cache fills where data is returned from cache of another CCX in the same or a different NUMA node.",
|
||||
"UMask": "0x14"
|
||||
},
|
||||
{
|
||||
"EventName": "ls_sw_pf_dc_fills.dram_io_far",
|
||||
"EventCode": "0x59",
|
||||
"BriefDescription": "Software prefetch data cache fills where data is returned from either DRAM or MMIO in a different NUMA node.",
|
||||
"UMask": "0x40"
|
||||
},
|
||||
{
|
||||
"EventName": "ls_sw_pf_dc_fills.dram_io_all",
|
||||
"EventCode": "0x59",
|
||||
"BriefDescription": "Software prefetch data cache fills where data is returned from either DRAM or MMIO in the same or a different NUMA node.",
|
||||
"UMask": "0x48"
|
||||
},
|
||||
{
|
||||
"EventName": "ls_sw_pf_dc_fills.far_all",
|
||||
"EventCode": "0x59",
|
||||
"BriefDescription": "Software prefetch data cache fills where data is returned from either cache of another CCX, DRAM or MMIO in a different NUMA node.",
|
||||
"UMask": "0x50"
|
||||
},
|
||||
{
|
||||
"EventName": "ls_sw_pf_dc_fills.alt_mem",
|
||||
"EventCode": "0x59",
|
||||
"BriefDescription": "Software prefetch data cache fills where data is returned from extension memory (CXL).",
|
||||
"UMask": "0x80"
|
||||
},
|
||||
{
|
||||
"EventName": "ls_sw_pf_dc_fills.all",
|
||||
"EventCode": "0x59",
|
||||
"BriefDescription": "Software prefetch data cache fills where data is returned from all types of data sources.",
|
||||
"UMask": "0xdf"
|
||||
},
|
||||
{
|
||||
"EventName": "ls_hw_pf_dc_fills.local_l2",
|
||||
"EventCode": "0x5a",
|
||||
"BriefDescription": "Hardware prefetch data cache fills where data is returned from local L2 cache.",
|
||||
"UMask": "0x01"
|
||||
},
|
||||
{
|
||||
"EventName": "ls_hw_pf_dc_fills.local_ccx",
|
||||
"EventCode": "0x5a",
|
||||
"BriefDescription": "Hardware prefetch data cache fills where data is returned from L3 cache or different L2 cache in the same CCX.",
|
||||
"UMask": "0x02"
|
||||
},
|
||||
{
|
||||
"EventName": "ls_hw_pf_dc_fills.local_all",
|
||||
"EventCode": "0x5a",
|
||||
"BriefDescription": "Hardware prefetch data cache fills where data is returned from local L2 cache, L3 cache or different L2 cache in the same CCX.",
|
||||
"UMask": "0x03"
|
||||
},
|
||||
{
|
||||
"EventName": "ls_hw_pf_dc_fills.near_cache",
|
||||
"EventCode": "0x5a",
|
||||
"BriefDescription": "Hardware prefetch data cache fills where data is returned from cache of another CCX in the same NUMA node.",
|
||||
"UMask": "0x04"
|
||||
},
|
||||
{
|
||||
"EventName": "ls_hw_pf_dc_fills.dram_io_near",
|
||||
"EventCode": "0x5a",
|
||||
"BriefDescription": "Hardware prefetch data cache fills where data is returned from either DRAM or MMIO in the same NUMA node.",
|
||||
"UMask": "0x08"
|
||||
},
|
||||
{
|
||||
"EventName": "ls_hw_pf_dc_fills.far_cache",
|
||||
"EventCode": "0x5a",
|
||||
"BriefDescription": "Hardware prefetch data cache fills where data is returned from cache of another CCX in a different NUMA node.",
|
||||
"UMask": "0x10"
|
||||
},
|
||||
{
|
||||
"EventName": "ls_hw_pf_dc_fills.remote_cache",
|
||||
"EventCode": "0x5a",
|
||||
"BriefDescription": "Hardware prefetch data cache fills where data is returned from cache of another CCX in the same or a different NUMA node.",
|
||||
"UMask": "0x14"
|
||||
},
|
||||
{
|
||||
"EventName": "ls_hw_pf_dc_fills.dram_io_far",
|
||||
"EventCode": "0x5a",
|
||||
"BriefDescription": "Hardware prefetch data cache fills where data is returned from either DRAM or MMIO in a different NUMA node.",
|
||||
"UMask": "0x40"
|
||||
},
|
||||
{
|
||||
"EventName": "ls_hw_pf_dc_fills.dram_io_all",
|
||||
"EventCode": "0x5a",
|
||||
"BriefDescription": "Hardware prefetch data cache fills where data is returned from either DRAM or MMIO in the same or a different NUMA node.",
|
||||
"UMask": "0x48"
|
||||
},
|
||||
{
|
||||
"EventName": "ls_hw_pf_dc_fills.far_all",
|
||||
"EventCode": "0x5a",
|
||||
"BriefDescription": "Hardware prefetch data cache fills where data is returned from either cache of another CCX, DRAM or MMIO in a different NUMA node.",
|
||||
"UMask": "0x50"
|
||||
},
|
||||
{
|
||||
"EventName": "ls_hw_pf_dc_fills.alt_mem",
|
||||
"EventCode": "0x5a",
|
||||
"BriefDescription": "Hardware prefetch data cache fills where data is returned from extension memory (CXL).",
|
||||
"UMask": "0x80"
|
||||
},
|
||||
{
|
||||
"EventName": "ls_hw_pf_dc_fills.all",
|
||||
"EventCode": "0x5a",
|
||||
"BriefDescription": "Hardware prefetch data cache fills where data is returned from all types of data sources.",
|
||||
"UMask": "0xdf"
|
||||
},
|
||||
{
|
||||
"EventName": "ls_alloc_mab_count",
|
||||
"EventCode": "0x5f",
|
||||
"BriefDescription": "In-flight L1 data cache misses i.e. Miss Address Buffer (MAB) allocations each cycle."
|
||||
},
|
||||
{
|
||||
"EventName": "ls_not_halted_cyc",
|
||||
"EventCode": "0x76",
|
||||
"BriefDescription": "Core cycles where the thread is not in halted state."
|
||||
},
|
||||
{
|
||||
"EventName": "ls_tlb_flush.all",
|
||||
"EventCode": "0x78",
|
||||
"BriefDescription": "All TLB flushes.",
|
||||
"UMask": "0xff"
|
||||
},
|
||||
{
|
||||
"EventName": "ls_not_halted_p0_cyc.p0_freq_cyc",
|
||||
"EventCode": "0x120",
|
||||
"BriefDescription": "Reference cycles (P0 frequency) where the thread is not in halted state.",
|
||||
"UMask": "0x1"
|
||||
}
|
||||
]
|
||||
Loading…
Reference in New Issue
Block a user